CN215868589U - Driving device of amplitude type spatial light modulator - Google Patents

Abstract

The utility model provides a driving device of an amplitude type spatial light modulator, which solves the problems of complex software and hardware circuits, high design difficulty and long development period of the conventional driving device of the spatial light modulator. The driving device comprises an interface module, a data decoding module, an LCOS driving module, a storage module and a microcontroller; the interface module is used for transmitting the input TMDS signals to the data decoding module, and the storage module is connected with the interface module; the microcontroller is respectively connected with the data decoding module and the LCOS driving module and is used for controlling the working states of the data decoding module and the LCOS driving module; the TMDS signal input by the interface module is decoded by the data decoding module to generate an image signal, a pixel clock signal, a data effective signal and a field synchronization signal, the signals are received by the LCOS driving module, and the LCOS driving module outputs an LCOS driving signal through GAMMA correction, shading correction, color configuration and time sequence generator processing.

Description

Driving device of amplitude type spatial light modulator

Technical Field

The utility model belongs to the field of spatial light modulator driving, and particularly relates to a driving device of an amplitude type spatial light modulator.

Background

A spatial light modulator is a device that modulates the spatial distribution of an optical wave. In general, a spatial light modulator refers to a device that, under the control of a signal source signal (control signal), can spatially and temporally transform or modulate a one-dimensional or two-dimensional distribution of one or some characteristics (e.g., phase, amplitude or intensity, frequency, polarization, etc.) of an optical wave to write information carried by the source signal into an incident optical wave. The spatial light modulator is generally classified into a reflection type and a transmission type according to a reading method of the reading light, and classified into an amplitude type, a phase type, an amplitude and phase type, and the like according to an optical parameter changing term generated by the reading light.

One of the core components of the spatial light modulator is a liquid crystal light valve, and its modulation characteristic is to change the phase or amplitude of readout light by changing the birefringence effect by applying a voltage to a liquid crystal cell mainly using the electro-optical effect of liquid crystal. The principle is that twisted nematic liquid crystal is in twisted arrangement when no voltage is applied, the liquid crystal tilts after the voltage is applied, when the voltage value applied to a liquid crystal box is between a Freedericksz transition threshold value and an optical threshold value, liquid crystal molecules rotate, the birefringence effect is reduced, but the liquid crystal molecules do not twist greatly, the liquid crystal box has similar functions with an optical waveguide, and the optical phase is mainly modulated; when the voltage value applied to the liquid crystal box is larger than the optical threshold, the liquid crystal molecules are arranged along the direction of the electric field, and simultaneously the optical waveguide and the effective birefringence of the liquid crystal molecules become weak, so that the light intensity is mainly modulated.

When the spatial light modulator is used for phase modulation, generally, as optical wave correction functions such as beam deflection, beam shaping, dynamic holography, laser optical tweezers, etc., it is required that the phase is stable and the phase resolution is as small as possible to ensure sufficient phase modulation accuracy. When the spatial light modulator is used for amplitude modulation, generally, as a display function, a luminance gradation of a reproduced source image without distortion is required, so that it is necessary to control the luminance change in a linear relationship with the luminance of the reproduced image, otherwise, image gradation distortion is caused. Therefore, when designing the driving of the amplitude-type spatial light modulator, it is necessary to fully consider the GAMMA correction scheme to ensure the reality of the image gray scale.

When the existing spatial light modulator is driven, most of the existing spatial light modulators adopt separated functional ICs to realize GAMMA correction, color correction, shadow correction, time sequence generation, data storage and the like in image display, and meanwhile, the compatibility problem among functional modules needs to be considered, so that the whole software and hardware circuit is very complex, the design difficulty is high, and the development period is long.

Disclosure of Invention

The utility model aims to solve the problems of complex software and hardware circuits, high design difficulty and long development period of the conventional spatial light modulator driving device, and provides a driving device of an amplitude type spatial light modulator, which is used for driving a reflective spatial light modulator of an LCOS (liquid crystal on silicon) type panel.

In order to achieve the purpose, the utility model adopts the following technical scheme:

a driving device of an amplitude type spatial light modulator comprises an interface module, a data decoding module, an LCOS driving module, a storage module and a microcontroller; the interface module is used for transmitting the input TMDS signals to the data decoding module; the storage module is connected with the interface module and is used for storing EDID information carried by the display data channel; the microcontroller is respectively connected with the data decoding module and the LCOS driving module and is used for controlling the working states of the data decoding module and the LCOS driving module; the TMDS signal input by the interface module is decoded by the data decoding module, an image signal, a pixel clock signal, a data effective signal and a field synchronization signal are generated under the control of the microcontroller, the signals are received by the LCOS driving module, and the driving signals are output to the LCOS device through GAMMA correction, shadow correction, color configuration and time sequence generator processing in the LCOS driving module.

Further, a core chip of the data decoding module is SiI1161, and a core chip of the LCOS driving module is ASI 6103.

Further, the microcontroller passes through I²And the C bus is connected with the LCOS driving module.

Further, the microcontroller is communicated with the upper computer through an RS232 communication module.

Furthermore, the interface module is a DVI interface module, and the interface of the DVI interface module adopts a standard DVI-D type.

Further, DVI interface module includes DVI port, protection diode, the DVI port passes through protection diode and is connected with data decoding module, simultaneously, storage module passes through I through pull-up resistance and DVI interface module²And C, bus connection.

Further, the protection diode adopts a bidirectional protection tube BAV99L and is connected at the four pairs of TMDS signal input positions.

Further, the core chip of the microcontroller adopts P89LV 51.

Further, a core chip of the RS232 communication module adopts MAX 3232.

Further, the core chip of the memory module adopts 24C 16.

Compared with the prior art, the utility model has the following beneficial technical effects:

1. the LCOS driving module of the driving device adopts the control chip integrating the GAMMA lookup table, the shadow correction table and the color lookup table, can independently complete the GAMMA correction function, the shadow correction function and the color correction function under the control of the microcontroller, does not need other functional ICs, realizes high integration level and low power consumption of the driving device, and simultaneously reduces the complexity of hardware design.

2. The GAMMA correction and color correction functions in the driving device adopt a lookup table mode, so that complicated formula calculation is avoided, and the characteristic of high efficiency is realized.

3. The driving device can lead in external GAMMA correction and image adjustment data through a serial port, realize the functions of GAMMA correction, gray scale adjustment, phase adjustment and the like, and can modify the gray scale linearity of the liquid crystal spatial light modulator in real time.

Drawings

FIG. 1 is a schematic block diagram of a driving apparatus of an amplitude type spatial light modulator according to the present invention;

FIG. 2 is a schematic diagram of the operation of a SiI1161 chip in the driving apparatus of the present invention;

FIG. 3 is a schematic diagram of the operation of an ASI6103 chip in the driving apparatus of the present invention;

fig. 4 is a circuit diagram of the interface module of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention and are not intended to limit the scope of the present invention.

The utility model provides a driving device of an amplitude type spatial light modulator, wherein an LCOS driving module of the device adopts a control chip integrating a GAMMA lookup table, a shadow correction table and a color lookup table, can independently complete the GAMMA correction function, the shadow correction function and the color correction function under the control of a microcontroller, does not need other functional ICs, realizes the characteristics of high integration level and low power consumption of the driving device, and simultaneously reduces the complexity of hardware design.

The driving device of the amplitude type spatial light modulator comprises an interface module, a data decoding module LCOS driving module, a storage module, an RS232 communication module and a microcontroller. The interface module is used for transmitting the input TMDS signals to the data decoding module; the storage module is connected with the interface module and used for storing the EDID information carried by the display data channel. Microcontroller pass I²The C bus is connected with the LCOS driving module and used for controlling the working states of the data decoding module and the LCOS driving module. By the interface moduleThe TMDS signal inputted by the block is decoded by the data decoding module, under the coordination of the microcontroller, an image signal is generated, and simultaneously a pixel clock signal, a data effective signal and a field synchronization signal are generated, the signals are received by the LCOS driving module, and are processed by the GAMMA correction, the shadow correction, the color configuration and the time sequence generator in the LCOS driving module, and the LCOS driving signal is outputted and provided for the LCOS.

The device has the key points that the hardware frame of the device is built by adopting the existing functional modules, the driving device of the spatial light modulator can be realized only by the existing functions of the modules, the modules only adopt the existing functions in the modules during working, the functions in the modules are not improved, and chips and functions adopted by the modules are described below.

As shown in fig. 4, the interface module of the present invention accesses and drives the input image signal, performs voltage limiting protection on the data signal, and provides a suitable high/low level for the control signal. The interface of the DVI interface module adopts a standard DVI-D type, and four pairs of TMDS signals are all provided with bidirectional voltage limiting protection diodes. The interface module can be a DVI interface module, the DVI interface module mainly comprises a DVI port and a protection diode, in figure 4, J1 is the DVI port, D1-D8 is the protection diode, RX0+/-, RX1+/-, RX2+/-, RXC +/-are TMDS signals, the signals are input into the data decoding module under the protection of the protection diode after being input from the DVI port, and meanwhile, the storage module and the DVI interface module pass through I through an I resistor²And C, bus connection.

The data decoding module mainly comprises a core chip SiI1161 and peripheral circuits thereof, wherein the SiI1161 is a DVI1.0 receiver which can provide 24-bit or 48-bit data output and can support a display panel with the highest UXGA resolution. The SiI1161 supports DVI1.0 protocol, has HSYNC debounce function and enables, the pixel selection type is selected to be two pixels (48 bits at the highest) per clock mode, the data output uses QO [16:23] & QE [16:23], the low-intensity current output driving mode is used, and the data on all odd-numbered and even-numbered data lines adopt the normal synchronous output mode.

The LCOS driving module mainly comprises a core chip ASI6103, a minimum system circuit and an operational amplifier circuit. The ASI6103 is a special driving chip, supports 8/10bit image signal input, and integrates a double-channel DDR memory inside. An external crystal oscillator of the ASI6103 adopts 14.318MHz, a hardware reset function is controlled by a microcontroller, DDR storage is integrated inside, and DDR is not designed outside. ASI6103 and microcontroller communication adopt I²And the C bus mode and the lookup table mode are adopted to configure GAMMA correction, shadow elimination correction and color configuration.

The storage module is an EEPROM chip which is separately configured for a DVI interface module and mainly comprises a core chip 24C16 and peripheral circuits thereof, and the core chip 24C16 is an EEPROM chip for I2C communication and is used for storing EDID information of input video signals.

The RS232 communication module mainly comprises a core device MAX3232 and a peripheral circuit thereof, wherein the MAX3232 is a multi-channel RS-232 line driver and a receiver, and the communication function of a microcontroller and an upper computer is realized.

The microcontroller mainly comprises a core device P89LV51 and a minimum system circuit thereof, and mainly comprises a clock module, an input/output pin module, a FLASH memory module, an initialization of an analog I2C module and a serial port module, an interrupt service function, default data, external LUT lookup table data and register address mapping function configuration.

As shown in fig. 1, image signals (the image signals include three TMDS data signals and one TMDS clock signal) sent by a computer display card are input to a driving board through a DVI interface, a panelllink receiver SiI1161 receives the TMDS signals, and under the control of a microcontroller and a SiI1161 peripheral circuit, the TMDS signals are synchronized, decoded and the like and converted into 10-bit image signals, field synchronizing signals, line synchronizing signals and other control signals, the converted signals are received by an LCOS driving module, and are processed by a GAMMA correction, a shadow correction, a color configuration and a timing generator inside the LCOS driving module, and LCOS driving signals are output and provided for the LCOS. The functions of the respective modules are explained in detail below.

The interface of DVI interface module of the utility model adopts DVI-D type which only transmits digital signal, and standard interface definition. The protection diode adopts a bidirectional protection tube BAV99L and is connected at the input of the four pairs of TMDS signals. I is²The C bus is used for communicating with the storage module, and other peripheral circuits in the DVI interface module refer to filter circuits of PIN14 and PIN16(5V power supply) of the DVI interface and adopt tantalum capacitor for filtering.

The core device SiI1161 of the data decoding module is a receiving chip supporting DVI1.0 protocol, the internal structure and the working principle are shown in figure 2, three pairs of TMDS data signals and one pair of TMDS clock signals are received and input, 8-bit image signals are output, 24-bit or 48-bit data are supported by one-way or two-way, and the driving method uses 16-bit data output: QO [16:23] & QE [16:23 ]. Other output signals are: the pixel clock signal ODCK is used for synchronizing 16-bit output data, the polarity is controlled by the PIN100 (OCK _ INV), and the drive method performs pull-down operation of 1K resistor on the OCK _ INV signal, so that ODCK is normally output without polarity inversion operation. The data effective signal DE is used for limiting a pixel effective data interval, a high level represents an effective display interval, and a low level represents a shadow elimination interval; a vertical synchronous output control signal VSYNC; the horizontal synchronization outputs a control signal HSYNC.

Other peripheral circuits in the data decoding module refer to capacitance filter circuits of all power supplies of the SiI 1161; impedance matching control PIN96(EXT _ RES), a 390 Ω resistor; a power-off control PIN PIN2(PD #), which disables all inputs and switches all output drivers to a high-impedance state when the PIN is at a low level, and which is controlled by the microcontroller; DVI link detection PIN PIN8(SCDT), high level indicates that DVI link is in working state, the signal is received and detected by microcontroller; an HSYNC debounce enabling PIN PIN (HS _ DJTR), a debounce function is enabled at a high level, and the HSYNC debounce function is enabled by a method of pulling up the signal; the driving method comprises the steps that an output intensity control PIN PIN3(ST), low-intensity current output at a low level, and high-intensity current output at a high level, and the driving method uses a pull-down ST PIN and uses the low-intensity current output; a pixel selection PIN PIN4(PIXS), a low level indicating one pixel (24 bits maximum) per clock mode using QE [23:0], a high level indicating two pixels (48 bits maximum) per clock mode, a first pixel using QE [23:0], and a second pixel using QO [23:0], the driving method defining a pixel selection pattern of two pixels per clock mode by a configuration of pulling up the PIXS PIN; the staggered output selection PIN PIN7(STAG _ OUT #), the high level selects the normal synchronous output of data on all the odd and even data lines, and the low level selects the staggered output drive.

The core device ASI6103 in the LCOS drive module of the utility model is an LCOS drive chip integrating DDR storage, the internal structure and the working principle are shown in figure 3, wherein GAMMA correction, shadow correction and color configuration are all carried out by a lookup table, and the microcontroller is carried out by I²The C bus operates the relevant register, the data buffering is completed by the DDR integrated in the LCOS driving chip, the buffered data is output in a specific time sequence through the time sequence generation module under the control of the microcontroller, and then the LCOS can be driven.

The minimal system of the ASI6103 in the LCOS driving module includes a hardware reset circuit, a PIN AF9(reset _ l) associated with the PIN is connected through a collector of a transistor, and the collector is configured to be in a pull-up state, a base of the transistor is controlled by a microcontroller, an emitter of the transistor is grounded, during power-up, after all VDD of the ASI6103 are stabilized, the microcontroller provides a high level signal of at least 200ns to the base of the transistor, at this time, the transistor is in a state of conducting 200ns, so that the reset _ l continues to be in a low level state of at least 200 ns; the driving method adopts an 14.318MHz crystal oscillator, two phase-locked loop clock generators in the ASI6103 are both driven by the crystal oscillator, one is used for a memory clock and a system clock, the clock frequency can be adjusted through a phase-locked loop register (0x7B, 0x7C), and the other is used for an LCOS clock, the clock frequency can be adjusted through a phase-locked loop register (0x7D, 0x 7E). In the operational amplifier circuit of the LCOS driving module, the associated pins a7(vitoref), B8(v1refb), and C8(vitorefb) refer to the vitoref, v1refb, and vitorefb output by the ASI6103 as three independent voltage signals.

The storage module of the utility model is an EEPROM circuit configured at a DVI interface and used for storing EDID information of video signals, an I2C bus of the storage is communicated with an external host of the DVI interface and respectively connected with PIN6(SCL signal) and PIN7(SDA signal) of the DVI interface.

The RS232 communication module realizes the function of 232 communication between the driver and external equipment through an RS232 interface chip MAX3232, and can realize operations such as GAMMA correction, phase quantity adjustment and the like through the interface.

The microcontroller mainly comprises a core device P89LV51 and a minimum system circuit thereof. The P89LV51 is a mixed signal system level microprocessor with functions of an 80C51 kernel, a FLASH memory and the like, realizes data interaction and control of an upper computer and a lower computer by controlling each device on an I2C bus simulated by an I/O port and connecting the devices with upper computer software of a control computer through a serial port. When the microcontroller works, firstly, a clock module, an input/output pin module, a FLASH memory module, an I2C module and a serial port module in the system are initialized, an interrupt service function, default data, external LUT lookup table data and a configuration function of a register address mapping function are declared, then using default data to define GAMMA correction, clock generation and variable value of phase-locked loop module register in turn and writing them into internal FLASH memory, then, after the data are read out, the bus of I2C is opened, the data are written into the register address of the LCOS driving module, and finally the circulation flow of judging whether the external serial port data are input or not is entered, after receiving an interrupt signal of external data input, the external GAMMA correction and image adjustment data are written into a FLASH memory for updating, and then the flow of data reading and I2C writing into the slave is executed again.

Claims (10)

1. A driving device of an amplitude type spatial light modulator, characterized in that: the LCOS drive module comprises an interface module, a data decoding module, an LCOS drive module, a storage module and a microcontroller;

the interface module is used for transmitting the input TMDS signals to the data decoding module;

the storage module is connected with the interface module and is used for storing EDID information carried by the display data channel;

the microcontroller is respectively connected with the data decoding module and the LCOS driving module and is used for controlling the working states of the data decoding module and the LCOS driving module;

the TMDS signal input by the interface module is decoded by the data decoding module, an image signal, a pixel clock signal, a data effective signal and a field synchronization signal are generated under the control of the microcontroller, the signals are received by the LCOS driving module, and the driving signals are output to the LCOS device through GAMMA correction, shadow correction, color configuration and time sequence generator processing in the LCOS driving module.

2. The driving device of the amplitude type spatial light modulator according to claim 1, characterized in that: the core chip of the data decoding module is SiI1161, and the core chip of the LCOS driving module is ASI 6103.

3. The driving device of the amplitude type spatial light modulator according to claim 2, characterized in that: the microcontroller passes through I²And the C bus is connected with the LCOS driving module.

4. The driving apparatus of an amplitude type spatial light modulator according to claim 1, 2 or 3, wherein: and the microcontroller is communicated with the upper computer through an RS232 communication module.

5. The driving apparatus of the amplitude type spatial light modulator according to claim 4, wherein: the interface module is a DVI interface module, and the interface of the DVI interface module adopts a standard DVI-D type.

6. The driving apparatus of the amplitude type spatial light modulator according to claim 5, wherein: the DVI interface module comprises a DVI port and a protection diode, wherein the DVI portIs connected with the data decoding module through a protection diode, and simultaneously, the storage module is connected with the DVI interface module through an I through a pull-up resistor²And C, bus connection.

7. The driving device of the amplitude type spatial light modulator according to claim 6, wherein: the protection diode adopts a bidirectional protection tube BAV99L and is connected at the input position of four pairs of TMDS signals.

8. The driving device of the amplitude type spatial light modulator according to claim 7, wherein: the core chip of the microcontroller adopts P89LV 51.

9. The driving device of the amplitude type spatial light modulator according to claim 8, wherein: the core chip of the RS232 communication module adopts MAX 3232.

10. The driving apparatus of the amplitude type spatial light modulator according to claim 9, wherein: the core chip of the memory module adopts 24C 16.

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