CN215771069U - Wafer-level chip packaging structure - Google Patents

Abstract

The invention discloses a wafer-level chip packaging structure, and belongs to the technical field of semiconductors. The wafer-level chip packaging structure and the manufacturing process thereof comprise the steps of uniformly coating photoresist on a passivation layer of a first chip, forming a film through hot plate soft baking and shaping, exposing a first bonding pad by using a developing solution through an exposure-development mode, and then manufacturing a metal bump through a physical vapor deposition process, a chemical vapor deposition process, sputtering, electroplating, chemical plating or ball planting process. The plastic package body is provided with the connecting column, so that the problem of stress inside the plastic package body can be effectively solved. The invention combines the advantages of the wafer level chip packaging and the system integration method, reduces the area of the packaging structure, reduces the manufacturing cost and improves the yield of the wafer level chip production.

Description

Wafer-level chip packaging structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a wafer-level chip packaging structure.

Background

With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.

The main component of the electronic device for realizing the preset function is a chip, along with the continuous progress of the integrated circuit technology, the integration level of the chip is higher and higher, the function of the chip is stronger and stronger, and the size of the chip is smaller and smaller, so that the chip needs to form a packaging structure through packaging so as to be convenient for the chip to be electrically connected with an external circuit.

The chip can also combine a plurality of logic elements, analog elements and active elements with different functions, and other elements such as passive elements, micro-electro-mechanical systems (MEMS), optical elements and the like into a unit to form a system or subsystem which can provide multiple functions, different ICs are integrated, a more complex system can be realized, the chip with the same function has smaller size, shorter design period and market period and lower cost.

Wafer Level Package (WLP) is a process for completing package integration on a substrate, and has the advantages of greatly reducing the area of a package structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batch, and the like, and can significantly reduce the workload and the requirements of equipment.

Conventional wafer level packaging methods generally include: providing a substrate, forming a dielectric layer on the substrate, then attaching one or more first chips to the dielectric layer through an adhesive layer on the substrate, then forming another dielectric layer on the substrate, then forming a conductive layer in the dielectric layer, then stacking a second chip on the first chip, and then forming a molding material on the dielectric layer to surround the second chip.

However, the above method has a complicated process and poor stability, and under an external force or thermal shock, the package structure may be deformed, and a large stress may be generated between the substrate and the chip inside the plastic package body, which may cause the chip package structure to fail in a serious case.

Disclosure of Invention

The invention aims to overcome the defects of the existing chip packaging structure, and provides a method which is simple in structure, reasonable in design and capable of reducing the probability of deformation of the chip packaging structure under external force or thermal shock and reducing larger stress between a substrate and a chip in a plastic packaging body by adopting a connecting column to improve the traditional packaging structure.

In order to achieve the purpose, the invention adopts the technical scheme that: a wafer level chip package structure, comprising: the chip package structure comprises a first chip, a conductive column, a substrate, a second chip, a plastic package body, a connecting column, an outer package body, a conductive bump, a second bonding pad, a dielectric layer, a passivation layer, a second opening, a bonding pad, a first bonding pad, a metal bump, a glue layer, a first opening and a mold.

Further, the first chip is arranged on the mold, and the surface of the first chip is upwards exposed out of the second bonding pad.

Further, a substrate is arranged on the mold, and a conductive column is arranged on the substrate.

Further, the conductive posts are electrically connected with the first bonding pads and the second bonding pads arranged on the surface of the first chip.

Further, the conductive posts extend to the back surface of the substrate and are buried in the substrate.

Further, a connection post is disposed on the substrate.

Further, the connecting column penetrates through the first chip and points to the second chip.

Further, a passivation layer is arranged on the second bonding pad of the first chip.

Further, the passivation layer is provided with a second opening, and a conductive bump is manufactured in the second opening.

Further, the second chip is placed on the conductive bump and electrically connected with the first chip through the conductive bump.

Further, a plastic package material in a molten state is injected into the mold, and after the plastic package material is solidified and solidified, a plastic package body is formed.

Further, after the secondary treatment, an outer packaging body is formed on the plastic packaging body.

Further, a first bonding pad is arranged on the first chip.

Further, a passivation layer is disposed on the first chip and covers the first bonding pad.

Furthermore, a first opening is formed above the first bonding pad, and at least part of the surface of the first bonding pad is exposed.

Further, a metal bump is disposed on an exposed surface of the first pad.

Further, the dielectric layer is provided with at least one semiconductor material of silicon dioxide SiO2, fluorocarbon CF, carbon-doped silicon oxide SiOC or silicon carbonitride SiCN.

Further, the material of the first bonding pad, the second bonding pad, or the bonding pad is at least one metal selected from silver Ag, gold Au, copper Cu, palladium Pd, chromium Cr, molybdenum Mo, titanium Ti, tantalum Ta, tin Sn, tungsten W, and aluminum Al.

Furthermore, the shape structure of the conductive bump is set as a solder ball, a copper pillar, a metal bump, or an alloy bump, and may also be other bump structures suitable for conduction.

Further, the material of the conductive bump is at least one metal or alloy material of tin, copper, nickel, silver-tin-copper alloy or tin-based alloy.

Further, the material of the passivation layer is at least one of insulating layers such as silicon oxide, silicon nitride, silicon oxynitride, polysilazane, polyvinyl phenol, polyimide, or siloxane.

Further, the manufacturing process of the passivation layer is provided by deposition by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, or by droplet discharge method, lithography, or spin coating method, or by stacking these films to form the passivation layer.

The plastic package body is made of at least one of thermosetting resins such as silica gel, phenolic resin, urea resin, melamine-formaldehyde resin, epoxy resin, unsaturated resin, polyurethane and polyimide.

Further, the plastic package body is provided with at least one additive such as a curing agent, a modifier, a release agent, a thermochromatic agent, a flame retardant and the like.

Further, the outer package body is provided with at least one material of epoxy-based resin (epoxy-based resin) and silicon-based resin (silicone-based resin), and high thermal conductive materials such as alumina thermal conductive powder and nano alumina can be added to achieve high thermal conductivity of the product.

Further, the substrate has a front side and a back side, and the encapsulation material covers the front side and the back side of the substrate.

Further, the substrate is provided with at least one semiconductor material of silicon Si, germanium Ge, silicon germanium SiGe, silicon carbide SiC, silicon germanium carbon SiGeC, indium arsenide InAs, gallium arsenide GaAs, indium phosphide InP, indium gallium arsenide InGaAs, silicon on insulator SOI, stacked silicon on insulator SSOI, stacked silicon on insulator S-SiGeOI, silicon on insulator SiGeOI, and germanium on insulator GeOI.

Further, the conductive column is provided with a metal conductive column or a silicon conductive column, the material of the metal conductive column includes, but is not limited to, at least one metal of silver Ag, gold Au, copper Cu, palladium Pd, chromium Cr, molybdenum Mo, titanium Ti, tantalum Ta, tin Sn, tungsten W, and aluminum Al, and the material of the silicon conductive column includes at least one silicon material of doped polysilicon or undoped polysilicon.

Further, the connecting columns are provided with at least one material of polyethylene, polypropylene, epoxy resin or phenolic resin.

Further, the glue layer is provided with at least one of a UV glue layer, an adhesive glue, an Epoxy resin (Epoxy), a Polyimide (PI), and the like.

Further, the mold is provided with at least one material of glass, silicon oxide, or metal. Further, the die is provided with a device capable of eliminating the tail warping problem in the chip manufacturing process.

Further, the manufacturing process of the metal bump comprises the steps of uniformly coating photoresist on a passivation layer of the first chip by a coating machine in a rotating mode, then carrying out soft baking and shaping on a hot plate to form a film, removing an unexposed area by using a developing solution in an exposure-development mode, exposing the first bonding pad, preparing the metal bump by at least one of a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a sputtering process, an electroplating process, a chemical plating process or a ball-planting process, and finally removing organic pollution on the surface of the metal bump by using a plasma residual glue removing machine.

The basic working principle of the invention is as follows: the method comprises the steps of obtaining one or more first chips, arranging a metal gasket on a second surface of each first chip, arranging the first surface of each first chip on a mold by utilizing a semiconductor process, wrapping the first surface and the side surface of each first chip by a plastic package body to expose the metal gasket, arranging a connecting hole on the plastic package body, filling a conductive material to form a conductive column between the first surface and the second surface of each first chip, arranging a connecting hole between the plastic package bodies between the first chips and the second chips, filling a connecting column in the connecting hole, obtaining one or more second chips, arranging the second chips on a substrate, connecting the first chips and the second chips through a conductive bump, arranging the metal gasket on the first surface of each first chip, arranging a passivation layer, and manufacturing a metal bump after opening.

After the chip packaging method is adopted, the invention has the beneficial effects that:

1. external force or thermal shock is reduced, more buffer space is reserved between the aluminum pad and the metal bump, and the aluminum pad is not easy to break and fail;

2. the connecting column is arranged in the plastic package body, and can be deformed preferentially when the package structure is deformed, so that the problem of stress in the plastic package body can be effectively solved;

3. the wafer level chip packaging and system integration method is combined, the advantages of integration of various chips and package manufacturing on the substrate are achieved, the area of the formed packaging structure can be greatly reduced, the manufacturing cost is reduced, the electrical performance and batch manufacturing of the packaging structure are optimized, the workload and the requirements of equipment are obviously reduced, and therefore the yield of the wafer level system packaging method is finally improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a package structure according to the present invention.

FIG. 2 is a schematic diagram of an opening formed in a passivation layer in a chip manufacturing process according to the present invention.

Fig. 3 is a schematic view of a first pad with an opening in the chip manufacturing process of the invention.

FIG. 4 is a schematic diagram of a system packaging structure according to the present invention.

Description of reference numerals:

the chip package comprises a first chip 1, a conductive pillar 11, a substrate 12, a second chip 2, a plastic package body 21, a connecting pillar 3, an outer package body 4, a conductive bump 5, a second pad 51, a dielectric layer 52, a passivation layer 521, a second opening 522, a pad 53, a first pad 61, a metal bump 62, a glue layer 63, a first opening 64 and a mold 7.

Detailed Description

The invention will be further described with reference to the accompanying drawings.

Referring to fig. 1 to 4, the technical solution adopted by the present embodiment is: a wafer level chip package structure, comprising: the chip package comprises a first chip 1, conductive pillars 11, a substrate 12, a second chip 2, a plastic package body 21, connection posts 3, an outer package body 4, conductive bumps 5, second pads 51, a dielectric layer 52, a passivation layer 521, second openings 522, pads 53, first pads 61, metal bumps 62, a glue layer 63, first openings 64 and a mold 7.

Further, the first chip 1 is disposed on the mold 7, and the surface of the first chip 1 is exposed upward to the second pad 51.

Further, a substrate 12 is disposed on the mold 7, and a conductive post 11 is disposed on the substrate 12.

Further, the conductive posts 11 are electrically connected to the first pads 61 and the second pads 51 provided on the surface of the first chip 1.

Further, the conductive post 11 extends toward the back surface of the substrate 12 and is buried in the substrate 12.

Further, the substrate 12 is provided with connection posts 3.

Further, the connection stud 3 penetrates the first chip 1 and points to the second chip 2.

Further, a passivation layer 521 is disposed on the second pad 51 of the first chip 1.

Further, the passivation layer 521 is provided with a second opening 522, and a conductive bump 5 is formed in the second opening 522.

Further, the second chip 2 is placed on the conductive bump 5, and is electrically connected to the first chip 1 through the conductive bump 5.

Further, a plastic package material in a molten state is injected into the mold 7, and after the plastic package material is solidified and solidified, a plastic package body 21 is formed.

Further, after the second treatment, the outer package 4 is formed on the plastic package 21.

Further, a first pad 61 is disposed on the first chip 1.

Further, a passivation layer is disposed on the first chip 1 and covers the first pad 61.

Further, a first opening 64 is opened above the first pad 61, exposing at least a portion of the surface of the first pad 61.

Further, a metal bump 62 is provided on an exposed surface of the first pad 61.

Further, the dielectric layer 52 is provided with at least one semiconductor material such as silicon dioxide SiO2, fluorocarbon CF, carbon-doped silicon oxide SiOC, or silicon carbonitride SiCN.

Further, the material of the first pad 61, the second pad 51, or the pad 53 is at least one metal selected from silver Ag, gold Au, copper Cu, palladium Pd, chromium Cr, molybdenum Mo, titanium Ti, tantalum Ta, tin Sn, tungsten W, and aluminum Al.

Further, the shape structure of the conductive bump 5 is configured as a solder ball, a copper pillar, a metal bump, or an alloy bump, and may also be other bump structures suitable for conduction.

Further, the material of the conductive bump 5 is at least one metal or alloy material of tin, copper, nickel, silver-tin-copper alloy or tin-based alloy.

Further, the material of the passivation layer 521 is at least one insulating layer of silicon oxide, silicon nitride, silicon oxynitride, polysilazane, polyvinyl phenol, polyimide, siloxane, or the like.

Further, the manufacturing process of the passivation layer 521 is provided by depositing and forming by a deposition method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, or by a droplet discharge method, a printing method, or a spin coating method, and the passivation layer may be formed by stacking these films.

The plastic package body 21 is made of at least one of thermosetting resins such as silica gel, phenol resin, urea resin, melamine-formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, and polyimide.

Further, the molded body 21 is provided with at least one additive such as a curing agent, a modifier, a release agent, a thermochromatic agent, and a flame retardant.

Further, the outer package 4 is provided with at least one material of epoxy-based resin (epoxy-based resin) and silicon-based resin (silicone-based resin), and high thermal conductive materials such as alumina thermal conductive powder and nano alumina can be added to achieve high thermal conductivity of the product.

Further, the substrate 12 has a front side and a back side, and the encapsulation material covers the front side and the back side of the substrate 12.

Further, the substrate 12 is provided with at least one semiconductor material of silicon Si, germanium Ge, silicon germanium SiGe, silicon carbide SiC, silicon germanium carbon SiGeC, indium arsenide InAs, gallium arsenide GaAs, indium phosphide InP, indium gallium arsenide InGaAs, silicon on insulator SOI, stacked silicon on insulator SSOI, stacked silicon on insulator S-SiGeOI, silicon on insulator SiGeOI, and germanium on insulator GeOI.

Further, the conductive column 11 is provided with a metal conductive column or a silicon conductive column, the material of the metal conductive column includes, but is not limited to, at least one metal of silver Ag, gold Au, copper Cu, palladium Pd, chromium Cr, molybdenum Mo, titanium Ti, tantalum Ta, tin Sn, tungsten W, and aluminum Al, and the material of the silicon conductive column includes at least one silicon material of doped polysilicon or undoped polysilicon.

Further, the connection column 3 is provided with at least one material of polyethylene, polypropylene, epoxy resin, or phenolic resin.

Further, the glue layer 63 is provided with at least one of a UV glue layer, an adhesive glue, an Epoxy resin (Epoxy), a Polyimide (PI), and the like.

Further, the mold 7 is provided with at least one material of glass, silicon oxide, or metal. Further, the mold 7 is provided with a device capable of eliminating the problem of tail warping in the chip manufacturing process.

Further, the manufacturing process of the metal bump 62 includes uniformly coating a photoresist on the passivation layer of the first chip 1 by a spin coating machine, soft baking and forming a film by a hot plate, removing an unexposed region by a developing solution in an exposure-development manner to expose the first pad 61, preparing the metal bump 62 by at least one of a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a sputtering process, an electroplating process, a chemical plating process, or a ball-planting process, and finally removing organic contamination on the surface of the metal bump 62 by using a plasma residual glue removing machine.

It should be noted that, if there is a directional indication (such as up, down, left, right, front, and back) in the embodiment of the present invention, it is only used to explain the relative position relationship between the components, the motion situation, and the like in a certain posture, and if the certain posture is changed, the directional indication is changed accordingly.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms, which are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, such that a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures.

It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures, for example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "under" would then be oriented "above" other elements or features, and thus the exemplary terms "under.

As used herein, the terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and it is to be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof, and that the term "and/or" as used herein includes any and all combinations of the associated listed items.

The above description is only for the purpose of illustrating the technical solutions of the present invention and not for the purpose of limiting the same, and other modifications or equivalent substitutions made by those skilled in the art to the technical solutions of the present invention should be covered within the scope of the claims of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims (10)

1. A wafer level chip package structure, comprising: the chip packaging structure comprises a first chip (1), a conductive column (11), a substrate (12), a second chip (2), a plastic package body (21), a connecting column (3), an outer package body (4), a conductive bump (5), a second bonding pad (51), a dielectric layer (52), a passivation layer (521), a second opening (522), a bonding pad (53), a first bonding pad (61), a metal bump (62), a glue layer (63), a first opening (64) and a mold (7); the first chip (1) is arranged on a mold (7), the surface of the first chip (1) is upwards exposed out of the second bonding pad (51), a substrate (12) is arranged on the mold (7), and a conductive column (11) is arranged on the substrate (12).

2. The wafer-level chip packaging structure according to claim 1, wherein the conductive pillar (11) is electrically connected to the first bonding pad (61) and the second bonding pad (51);

the conductive column (11) extends to the back surface of the substrate (12) and is buried in the substrate (12);

the substrate (12) is provided with a connecting column (3), and the connecting column (3) penetrates through the first chip (1) and points to the second chip (2).

3. The wafer level chip package structure according to claim 1, wherein the mold (7) is provided with a molding compound (21), and the molding compound (21) is provided with an outer package (4).

4. The wafer level chip packaging structure according to claim 1, wherein a first bonding pad (61) is disposed on the first chip (1); a passivation layer is arranged on the first chip (1) and covers the first bonding pad (61); a first opening (64) is formed above the first bonding pad (61) to expose at least part of the surface of the first bonding pad (61); a metal bump (62) is provided on an exposed surface of the first pad (61).

5. The wafer-level chip package structure according to claim 1, wherein the shape structure of the conductive bump (5) is configured as a metal bump adapted to the shape structure of the conductive bump.

6. The wafer level chip packaging structure according to claim 1, wherein a passivation layer (521) is disposed on the second bonding pad (51), the passivation layer (521) is provided with a second opening (522), and a conductive bump (5) is disposed on the second opening (522);

the second chip (2) is placed on the conductive bump (5) and is electrically connected with the first chip (1) through the conductive bump (5).

7. The wafer level chip packaging structure according to claim 1, wherein the side of the plastic package body (21) is surrounded by an outer package body (4), and the outer package body (4) packages the semiconductor device therein.

8. The wafer-level chip package structure according to claim 1, wherein the substrate (12) is provided with a front side and a back side, and the encapsulation material of the substrate (12) covers the front side and the back side of the substrate (12).

9. The wafer level chip package structure according to claim 1, wherein the mold (7) is provided with a device for eliminating tail warping during the chip manufacturing process.

10. The wafer-level chip package structure according to claim 1, wherein a conductive metal is disposed inside the conductive pillar (11), and a side surface of the conductive pillar (11) contains polysilicon.

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