CN215731718U - Array substrate, display panel and display device - Google Patents

Abstract

The utility model discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate and a driving circuit layer positioned on the substrate, wherein the driving circuit layer comprises a pixel driving circuit, a first scanning signal line and an initialization signal line; the pixel driving circuit comprises an initialization transistor, a first scanning signal line is connected with the grid electrode of the initialization transistor, and the initialization signal line is connected with the first pole of the initialization transistor; the vertical projection of the initialization signal line on the substrate is not overlapped with the vertical projection of the first scanning signal line on the substrate, so that a bridge spanning structure spanning the first scanning signal line is avoided when the initialization signal line is connected with the first electrode of the initialization transistor, the production cost is reduced, in addition, in the detection process, the probability of short circuit between the bridge spanning structure and the signal line in the array substrate is reduced, and the detection yield of the array substrate is improved.

Description

Array substrate, display panel and display device

Technical Field

The embodiment of the utility model relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

An Organic Light Emitting Diode (OLED) display panel includes a plurality of pixel units, each corresponding to a pixel driving circuit. The OLED display panel is also provided with an initialization signal line for providing an initialization signal for an initialization transistor in the pixel driving circuit. When the initialization signal line is connected to the initialization transistor, the bridge structure is formed on the scanning signal line by the connecting structure, so that the cost is increased, line defects are easily caused when the OLED display panel is detected, and the yield of the OLED display panel is reduced.

SUMMERY OF THE UTILITY MODEL

The utility model provides an array substrate, a display panel and a display device, which are used for reducing the cost of the array substrate and improving the yield of the array substrate.

In a first aspect, an embodiment of the present invention provides an array substrate, including:

the pixel driving circuit comprises a substrate and a driving circuit layer positioned on the substrate, wherein the driving circuit layer comprises a pixel driving circuit, a first scanning signal line and an initialization signal line; the pixel driving circuit comprises an initialization transistor, the first scanning signal line is connected with the grid electrode of the initialization transistor, and the initialization signal line is connected with the first pole of the initialization transistor; the vertical projection of the initialization signal line on the substrate is not overlapped with the vertical projection of the first scanning signal line on the substrate.

Optionally, the driving line layer further includes a second scanning signal line, and the pixel driving circuit further includes a data writing transistor; the grid electrode of the data writing transistor is connected with the second scanning signal line; the initialization signal line is disposed between the first scanning signal line and the second scanning signal line.

Optionally, the driving line layer further includes a via hole, the via hole is filled with a conductive material, and the first pole of the initialization transistor is connected to the initialization signal line through the via hole.

Optionally, the initialization transistor includes a gate initialization transistor and an anode initialization transistor, a gate of the gate initialization transistor and a gate of the anode initialization transistor are connected to the first scan signal line, and a first pole of the gate initialization transistor and a first pole of the anode initialization transistor are connected to the initialization signal line.

Optionally, the driving line layer further includes a third scanning signal line, the initialization transistor is a gate initialization transistor, and the pixel driving circuit further includes an anode initialization transistor; the grid electrode of the anode initialization transistor is connected with the third scanning signal line, the first electrode of the reset transistor is connected with the initialization signal line, and the vertical projection of the initialization signal line on the substrate is not overlapped with the vertical projection of the third scanning signal line on the substrate.

Optionally, the pixel driving circuit further includes a storage capacitor, where the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the first scan signal line are disposed in the same layer, and the second electrode plate and the initialization signal line are disposed in the same layer.

Optionally, the driving line layer further includes a data signal line, an extending direction of the data signal line intersects an extending direction of the initialization signal line, and a first electrode of the data writing transistor is connected to the data signal line; the initialization signal line is arranged on one side of the data signal line, which is far away from the substrate.

Optionally, the driving circuit layer further includes a light emission control signal line, the pixel driving circuit further includes a light emission control transistor, a gate of the light emission control transistor is connected to the light emission control signal line, and the light emission control signal line is disposed on a side of the second scanning signal line away from the first scanning signal line.

In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate provided in any embodiment of the first aspect.

In a third aspect, an embodiment of the present invention further provides a display device, including the display panel provided in any embodiment of the second aspect.

According to the technical scheme of the embodiment of the utility model, the vertical projection of the initialization signal line on the substrate is not overlapped with the vertical projection of the first scanning signal line on the substrate, so that a bridge-crossing structure crossing the first scanning signal line can be avoided when the initialization signal line is connected with the first electrode of the initialization transistor, the material cost is reduced, the probability of short circuit between the bridge-crossing structure and the signal line in the array substrate is reduced in the subsequent detection process of the array substrate, and the detection yield of the array substrate is improved.

Drawings

Fig. 1 is a schematic structural diagram of a pixel driving circuit provided in the prior art;

FIG. 2 is a schematic diagram of a pixel driving circuit corresponding to FIG. 1;

fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 5 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the utility model;

fig. 6 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the utility model;

fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a pixel driving circuit provided in the prior art, and fig. 2 is a structural diagram of a pixel driving circuit corresponding to fig. 1. As shown in fig. 1 and 2, the gates of the gate initialization transistor T1 and the anode initialization transistor T2 in the pixel driving circuit are connected to the first scan signal line S1, the first pole is connected to the initialization signal line vref, the second pole of the gate initialization transistor T1 is connected to the gate of the driving transistor T3, and the second pole of the anode initialization transistor T2 is connected to the anode of the light emitting device D1. In the initialization stage, the first scan signal line S1 controls the gate initialization transistor T1 and the anode initialization transistor T2 to be turned on, so that the initialization signal supplied from the initialization signal line vref is transmitted to the gate of the driving transistor T3 and the anode of the light emitting device D1 through the gate initialization transistor T1 and the anode initialization transistor T2, respectively, to initialize the gate of the driving transistor T3 and the anode of the light emitting device D1. With continued reference to fig. 1 and 2, when the initialization signal line vref is connected to the first poles of the gate initialization transistor T1 and the anode initialization transistor T2, the initialization signal line vref extends through the signal transmission structure 101 to above the first poles of the gate initialization transistor T1 and the anode initialization transistor T2, and then the connection of the initialization signal line vref to the first poles of the gate initialization transistor T1 and the anode initialization transistor T2 is achieved through vias. Since the transmission structure 101 crosses the first scanning signal line S1 to form a bridge, the material cost is increased, and when the array substrate where the pixel driving circuit is located is detected, a short circuit is easily generated at the bridge, which causes a bad circuit, and reduces the yield of the array substrate.

In view of the above technical problems, an embodiment of the present invention provides an array substrate. Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. As shown in fig. 3, the array substrate includes a substrate 110 and a driving line layer on the substrate 110, the driving line layer including a pixel driving circuit 120, a first scanning signal line 131 and an initialization signal line 141; the pixel driving circuit 120 includes an initialization transistor M1, the first scanning signal line 131 is connected to the gate of the initialization transistor M1, and the initialization signal line 141 is connected to the first pole of the initialization transistor M1; the vertical projection of the initialization signal line 141 on the substrate 110 does not overlap the vertical projection of the first scanning signal line 131 on the substrate 110.

Specifically, the substrate 110 may be a flexible substrate, and the substrate 110 may be Polyimide (PI) by way of example. The driving circuit layer includes pixel driving circuits 120, and each pixel driving circuit 120 corresponds to a light emitting device in the display panel, and is configured to provide a driving signal to the corresponding light emitting device to drive the light emitting device to emit light. The driving line layer further includes signal lines for providing control signals to the pixel driving circuits 120, and controlling the pixel driving circuits 120 to form driving signals. The driving line layer includes an active layer and a plurality of conductive layers, and the pixel driving circuit 120 may include a plurality of transistors. The active layer is used to form active regions of transistors within the pixel driving circuit 120 and connection lines between different transistors, and the multi-layered conductive layer may be used to form the first scanning signal line 131 and the initialization signal line 141. Illustratively, the conductive layer where the initialization signal line 141 is located on a side of the conductive layer where the first scanning signal line 131 is located, which is far from the substrate 110. The first scan signal line 131 is connected to the gate of the initialization transistor M1 for providing a gate signal to the initialization transistor M1 to control the initialization transistor M1 to be turned on or off. The initialization signal line 141 is connected to a first pole of the initialization transistor M1 for providing an initialization signal to the initialization transistor M1. When the initialization signal line 141 is connected to the first pole of the initialization transistor M1, it may be configured that a vertical projection of the initialization signal line 141 and the extension line when the initialization signal line 141 is connected to the first pole of the initialization transistor M1 on the substrate 110 is not overlapped with a vertical projection of the first scan signal line 131 on the substrate 110, that is, the initialization signal line 141 is directly connected to the first pole of the initialization transistor M1, so that a bridge structure spanning the first scan signal line 131 may be avoided when the initialization signal line 141 is connected to the first pole of the initialization transistor M1, which not only reduces material cost, but also reduces the probability of short circuit between the bridge structure and the signal line in the array substrate in the subsequent array substrate detection process, and improves the detection yield of the array substrate.

With continued reference to fig. 3, the driving line layer further includes a second scanning signal line 132, and the pixel driving circuit 120 further includes a data writing transistor M2; the gate of the data writing transistor M2 is connected to the second scanning signal line 132; the initialization signal line 141 is disposed between the first and second scanning signal lines 131 and 132.

Specifically, as shown in fig. 3, the pixel driving circuit 120 further includes a data writing transistor M2, the gate of the data writing transistor M2 is connected to the second scanning signal line 132, and the first pole of the data writing transistor M2 is connected to the data signal line. After the initialization transistor M1 is controlled to be turned on by the first scan signal provided by the first scan signal line 131 to initialize the pixel driving circuit 120, the data writing transistor M2 is controlled to be turned on by the second scan signal provided by the second scan signal line 132, so that the data writing transistor M2 writes the data voltage provided by the data signal line, and the data writing of the pixel driving circuit 120 is realized. With reference to fig. 3, the initialization signal line 141 is disposed between the first scanning signal line 131 and the second scanning signal line 132, and the first pole of the initialization transistor M1 is disposed on a side of the initialization signal line 141 away from the first scanning signal line 131, so that when the initialization signal line 141 is connected to the first pole of the initialization transistor M1, the initialization signal line 141 can be directly connected to the first pole of the initialization transistor M1 along the vertical direction of the substrate 110, and a bridge structure spanning the first scanning signal line 131 is prevented from being generated by the initialization signal line 141 extending along the intersecting direction X in which the first scanning line extends, which not only reduces the material cost, but also reduces the probability of short circuit between the bridge structure and the signal lines in the array substrate in the subsequent array substrate detection process, and improves the detection yield of the array substrate.

With continued reference to fig. 3, the pixel driving circuit 120 further includes a driving transistor M3 and a threshold compensation transistor M4, a second pole of the data writing transistor M2 is connected to the first pole of the driving transistor M3, a first pole of the threshold compensation transistor M4 is connected to the gate of the driving transistor M3, a second pole of the threshold compensation transistor M4 is connected to the second pole of the driving transistor M3, and the gate of the threshold compensation transistor M4 is connected to the second scan signal line 132. When the data writing transistor M2 is controlled to be turned on by the second scan signal provided by the second scan signal line 132, the threshold compensation transistor M4 is controlled to be turned on by the second scan signal provided by the second scan signal line 132, and the data signal is transmitted to the gate of the driving transistor M3 through the driving transistor M3 and the threshold compensation transistor M4, so that the data writing is realized and the threshold compensation of the driving transistor M3 is realized.

With continued reference to fig. 3, the driving line layer further includes a via 151, the via 151 is filled with a conductive material, and the first pole of the initialization transistor M1 is connected to the initialization signal line 141 through the via 151.

In particular, an insulating layer may be further disposed between the active layer and the conductive layer for insulating the active layer and the conductive layer or for insulating adjacent conductive layers. The first pole of the initialization transistor M1 may be formed by an active layer, and the initialization signal line 141 may be formed by a conductive layer. When the first pole of the initialization transistor M1 is connected to the initialization signal line 141, a via 151 may be provided on the insulating layer between the active layer and the conductive layer, and a vertical projection of the via 151 on the substrate 110 overlaps a vertical projection of the initialization signal line 141 on the substrate 110 and a vertical projection of the first pole of the initialization transistor M1 on the substrate 110, and the via 151 is filled with a conductive material, achieving connection of the first pole of the initialization transistor M1 to the initialization signal line 141. In addition, the initialization signal line 141 is directly and vertically connected to the first electrode of the initialization transistor M1 through the via 151, which can reduce the patterning structure of the initialization signal line 141 and is beneficial to reducing the cost in the patterning process.

It should be noted that, fig. 3 exemplarily shows that the initialization transistor M1 includes a gate initialization transistor M11 and an anode initialization transistor M12, the gate of the gate initialization transistor M11 and the gate of the anode initialization transistor M12 are connected to the first scanning signal line 131, and the first pole of the gate initialization transistor M11 and the first pole of the anode initialization transistor M12 are connected to the initialization signal line 141.

Specifically, the pixel driving circuit 120 further includes a driving transistor M3 and a light emitting device (not shown in fig. 3), the second pole of the gate initialization transistor M11 is connected to the gate of the driving transistor M3, and the second pole of the anode initialization transistor M12 is connected to the anode of the light emitting device. In the initialization stage of the pixel driving circuit, the first scan signal line 131 controls the gate initialization transistor M11 and the anode initialization transistor M12 to be turned on simultaneously, and the initialization signal provided from the initialization signal line 141 is transmitted to the gate of the driving transistor M3 through the gate initialization transistor M11 to initialize the gate of the driving transistor M3 and transmitted to the anode of the light emitting device through the anode initialization transistor M12 to initialize the anode of the light emitting device.

It should be noted that, in other embodiments, the initialization transistor may be a gate initialization transistor or an anode initialization transistor. Fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 4, the driving line layer further includes a third scan signal line 133, the initialization transistor M1 is a gate initialization transistor M11, and the pixel driving circuit 120 further includes an anode initialization transistor M12; the gate of the anode initialization transistor M12 is connected to the third scanning signal line 133, the first pole of the anode initialization transistor M12 is connected to the initialization signal line 141, and the vertical projection of the initialization signal line 141 on the substrate 110 does not overlap the vertical projection of the third scanning signal line M12 on the substrate 110.

Specifically, in the array substrate, the pixel driving circuits 120 may be arranged in an array. The third scanning signal line 133 corresponding to the pixel driving circuit 120 in the previous row may multiplex the first scanning signal line 131 corresponding to the pixel driving circuit 120 in the next row, and the gate of the anode initialization transistor M12 in the pixel driving circuit 120 in the previous row and the gate of the gate initialization transistor M11 in the pixel driving circuit 120 in the next row are connected to the same scanning signal line, while the first pole of the anode initialization transistor M12 in the pixel driving circuit 120 in the previous row and the first pole of the gate initialization transistor M11 in the pixel driving circuit 120 in the next row are connected to the same initialization signal line 141. When the gate of the anode initialization transistor M12 is connected to the third scanning signal line 133, the third scanning signal line 133 controls the anode initialization transistor M12 to be turned on after the data writing period in the pixel driving circuit 120, thereby initializing the anode of the light emitting device. At the same time, the gate initialization transistor M11 in the pixel driving circuit 120 in the next row is turned on, and the gate of the driving transistor M3 in the pixel driving circuit 120 in the next row is initialized. At this time, the initialization signal line 141 is located between the second scanning signal line 132 of the pixel driving circuit 120 in the current row and the first scanning signal line 131 of the pixel driving circuit 120 in the next row, that is, located between the second scanning signal line 132 and the third scanning signal line 133 of the pixel driving circuit 120 in the same row, and the vertical projection of the initialization signal line 141 on the substrate 110 is set to be non-overlapped with the vertical projection of the third scanning signal line M12 on the substrate 110, so that a bridge spanning structure spanning the third scanning signal line 133 when the initialization signal line 141 is connected with the first electrode of the gate initialization transistor M11 in the pixel driving circuit 120 in the next row can be avoided, and not only is the material cost reduced, but also in the subsequent array substrate detection process, the probability of short circuit between the bridge spanning structure and the signal lines in the array substrate is reduced, and the detection yield of the array substrate is improved.

With continued reference to fig. 4, the driving circuit layer further includes a light-emitting control signal line 134, the pixel driving circuit 120 further includes a light-emitting control transistor M5, a gate of the light-emitting control transistor M5 is connected to the light-emitting control signal line 134, and the light-emitting control signal line 134 is disposed on a side of the second scanning signal line 132 away from the first scanning signal line 131.

Specifically, the pixel driving circuit 120 may include two emission control transistors M5, a first emission control transistor M51 and a second emission control transistor M52, respectively. The gates of the first and second light emission control transistors M51 and M52 are connected to a light emission control signal line 134, the first pole of the first light emission control transistor M51 is connected to a power signal line, the second pole of the first light emission control transistor M51 is connected to the first pole of the driving transistor M3, the first pole of the second light emission control transistor M52 is connected to the second pole of the driving transistor M3, and the second pole of the second light emission control transistor M52 is connected to the anode of the light emitting device. In a light emitting stage of the pixel driving circuit 120, the light emitting control signal line 134 controls the first and second light emitting control transistors M51 and M52 to be turned on, and the first light emitting control transistor M51, the driving transistor M3, and the second light emitting control transistor M52 form a current path to supply a driving current to the light emitting device, which emits light according to the driving current. Because the light-emitting control signal line 134 is disposed on the side of the second scan signal line 132 away from the first scan signal line 131, a bridge-crossing structure crossing the light-emitting control signal line 134 generated by the connection of the initialization signal line 141 and the initialization transistor M1 extending along the intersecting direction X along which the first scan line extends can be avoided, so that not only is the material cost reduced, but also the probability of short circuit between the bridge-crossing structure and the signal line in the array substrate is reduced in the subsequent detection process of the array substrate, and the detection yield of the array substrate is improved.

Fig. 5 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the utility model, and with continued reference to fig. 4 to 5, the pixel driving circuit further includes a storage capacitor C1, the storage capacitor C1 includes a first electrode C11 and a second electrode C12, the first electrode C11 and the first scanning signal line 131 are disposed in the same layer, and the second electrode C12 and the initialization signal line 141 are disposed in the same layer.

Specifically, the storage capacitor C1 is connected to the gate of the driving transistor M3 in the pixel driving circuit 120, and is used for storing and maintaining the potential of the gate of the driving transistor M3 after the data voltage is written into the gate of the driving transistor M3 in the data writing phase. The first plate C11 of the storage capacitor C1 may be disposed at the same layer as the first scan signal line 131, and for example, the first plate C11 may multiplex the gate of the driving transistor M3, and the second plate C12 may be disposed at the same layer as the initialization signal line 141, which may reduce the arrangement of conductive layers in the array substrate.

Fig. 6 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the utility model. Referring to fig. 3 and 6, the driving line layer further includes a data signal line 161, an extending direction of the data signal line 161 intersects an extending direction of the initialization signal line 141, and a first pole of the data write transistor M2 is connected to the data signal line 161; the initialization signal line 141 is disposed on a side of the data signal line 161 away from the substrate 110.

Specifically, the driving line layer may include four conductive layers, and the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are sequentially disposed along a direction in which the substrate 110 is directed to the conductive layers. The first conductive layer may be used to form the first scanning signal line 131, the second conductive layer may be used to form the storage capacitor C, the third conductive layer may be used to form the data signal line 161 and the power signal line 162, and the fourth conductive layer may be used to form the initialization signal line 141, such that the initialization signal line 141 is disposed at a side of the data signal line 161 away from the substrate 110, and when the initialization signal line 141 and the data signal line 161 and the power signal line 162 extend in different directions, not only a short circuit caused by the intersection of the data signal line 161 and the power signal line 162 with the initialization signal line 141 may be avoided, but also the difficulty in arranging different signal lines may be reduced.

The embodiment of the utility model also provides a display panel. Fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 7, the display panel 10 includes an array substrate 11 according to any embodiment of the present invention.

Specifically, the display panel 10 includes the array substrate 11 provided in any embodiment of the present invention, and therefore has the same beneficial effects as the array substrate provided in any embodiment of the present invention, and the details are not repeated herein. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame and the like.

The embodiment of the utility model also provides a display device. Fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 8, the display device 20 includes a display panel 21 provided in any embodiment of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. An array substrate, comprising:

the pixel driving circuit comprises a substrate and a driving circuit layer positioned on the substrate, wherein the driving circuit layer comprises a pixel driving circuit, a first scanning signal line and an initialization signal line; the pixel driving circuit comprises an initialization transistor, the first scanning signal line is connected with the grid electrode of the initialization transistor, and the initialization signal line is connected with the first pole of the initialization transistor;

the vertical projection of the initialization signal line on the substrate is not overlapped with the vertical projection of the first scanning signal line on the substrate.

2. The array substrate of claim 1, wherein the driving line layer further comprises a second scanning signal line, and the pixel driving circuit further comprises a data writing transistor; the grid electrode of the data writing transistor is connected with the second scanning signal line; the initialization signal line is disposed between the first scanning signal line and the second scanning signal line.

3. The array substrate of claim 1, wherein the driving line layer further comprises a via hole filled with a conductive material, and the first pole of the initialization transistor is connected to the initialization signal line through the via hole.

4. The array substrate of claim 2, wherein the initialization transistor comprises a gate initialization transistor and an anode initialization transistor, a gate of the gate initialization transistor and a gate of the anode initialization transistor are connected to the first scan signal line, and a first pole of the gate initialization transistor and a first pole of the anode initialization transistor are connected to the initialization signal line.

5. The array substrate of claim 1, wherein the driving circuit layer further comprises a third scanning signal line, the initialization transistor is a gate initialization transistor, and the pixel driving circuit further comprises an anode initialization transistor; the grid electrode of the anode initialization transistor is connected with the third scanning signal line, the first electrode of the anode initialization transistor is connected with the initialization signal line, and the vertical projection of the initialization signal line on the substrate is not overlapped with the vertical projection of the third scanning signal line on the substrate.

6. The array substrate of claim 1, wherein the pixel driving circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate, the first plate is disposed on a same layer as the first scanning signal line, and the second plate is disposed on a same layer as the initialization signal line.

7. The array substrate of claim 2, wherein the driving line layer further comprises a data signal line, an extending direction of the data signal line intersects an extending direction of the initialization signal line, and a first pole of the data writing transistor is connected to the data signal line; the initialization signal line is arranged on one side of the data signal line, which is far away from the substrate.

8. The array substrate of claim 2, wherein the driving circuit layer further comprises a light emission control signal line, the pixel driving circuit further comprises a light emission control transistor, a gate of the light emission control transistor is connected to the light emission control signal line, and the light emission control signal line is disposed on a side of the second scanning signal line away from the first scanning signal line.

9. A display panel comprising the array substrate according to any one of claims 1 to 8.

10. A display device characterized by comprising the display panel according to claim 9.

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