CN215581226U

CN215581226U - Exchanger capable of customizing protocol line sequence

Info

Publication number: CN215581226U
Application number: CN202122329903.2U
Authority: CN
Inventors: 蒋忠伟; 刘志
Original assignee: Shenzhen Daren High Tech Electronic Co ltd
Current assignee: Shenzhen Daren High Tech Electronic Co ltd
Priority date: 2021-09-24
Filing date: 2021-09-24
Publication date: 2022-01-18
Anticipated expiration: 2031-09-24

Abstract

The utility model discloses an exchanger capable of customizing a protocol line sequence, which comprises a first interface and a second interface, wherein the first interface and the second interface are respectively arranged at two ends of a protocol line; the relay group is connected with the first interface and the second interface respectively, and the first interface and the second interface are connected through the relay group according to a user-defined line sequence; the control unit is connected with the relay set and controls the relay set to work; and the upper computer is connected with and communicates with the control unit, and the line sequence between the first interface and the second interface is set by the upper computer in a user-defined mode. The exchanger capable of customizing the protocol line sequence has high safety and stable communication, and is not easy to generate short circuit phenomenon caused by wrong wiring. When the line sequence needs to be replaced, the line sequence only needs to be set by an upper computer in a user-defined mode, the reliability and the efficiency of wiring are high, the compatibility is good, and the method is applicable to different non-standardized application scenes.

Description

Exchanger capable of customizing protocol line sequence

[ technical field ] A method for producing a semiconductor device

The utility model relates to a junction device, in particular to a switch capable of customizing a protocol line sequence.

[ background of the utility model ]

The protocol line usually uses the network interface hardware to communicate with the standard interface, wherein, when the industrial bus such as RS485, 232, CAN, etc. uses the network interface hardware to communicate with the standard interface, the corresponding line sequence between the network interface and the standard interface needs to be selected to connect, so as to realize the transmission and reception of information. The existing wiring method between the network port and the standard interface is to convert the standard interface into a wiring terminal, then to perform wiring in a manual mode, and after the wiring is completed, to fix the wiring terminal by a screw. When the network port or the interface needs to be replaced, the connection needs to be reconnected, so that the efficiency is low, and the phenomenon of short circuit or open circuit caused by wrong connection is easy to occur. On the other hand, the conventional manual connection method is also easy to cause poor contact and communication interruption. In addition, in the existing wiring method, redundant miscellaneous wires exist, and the appearance of the product is influenced.

[ Utility model ] content

The present invention is directed to solve the above problems, and provides a switch capable of customizing protocol line sequence, which has good compatibility, high security, stable communication and convenient use.

The utility model relates to a switch capable of customizing protocol line sequence, comprising:

the first interface and the second interface are respectively arranged at two ends of the protocol line; the first interface and the second interface are respectively connected with interfaces of different devices; the first interface is at least provided with one pin, and the second interface is at least provided with two pins;

at least two relay groups, which are respectively connected with the first interface and the second interface, and the first interface and the second interface are connected through the relay groups according to a user-defined line sequence;

the control unit is connected with the relay set and controls the relay set to work;

and the upper computer is connected with and communicates with the control unit, and the line sequence between the first interface and the second interface is set by the upper computer in a user-defined mode.

The quantity of relay group with the stitch quantity of first interface is the same, every the relay group includes a plurality of relays, every in the relay group the quantity of relay with the stitch quantity of second interface is the same, and every behind a plurality of relay contact public end short circuits in the relay group, again in proper order with a stitch of first interface is connected, every the normally open contact of a plurality of relays in the relay group respectively in proper order with a stitch of second interface is connected.

The control unit comprises a USB interface, a USB-to-serial port circuit, a processing module, at least two relay group driving circuits and a power module, wherein the USB interface is respectively connected with an upper computer and the USB-to-serial port circuit, the processing module is respectively connected with the USB-to-serial port circuit and the relay group driving circuits, each relay group is respectively connected with one of the relay group driving circuits, and the power module is respectively connected with the USB interface, the USB-to-serial port circuit, the processing module and the relay group driving circuits.

Further, the processing module comprises a fourth chip U4 and a peripheral circuit, the fourth chip U4 is respectively connected with the relay group driving circuit and the peripheral circuit, and the peripheral circuit comprises a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a second resistor R2 and a first crystal oscillator X1.

Furthermore, the peripheral circuit comprises a reset circuit, a power supply filter circuit and a crystal oscillator circuit; the reset circuit comprises a second resistor R2 and a seventh capacitor C7, one end of the second resistor R2 is connected with the ninth pin of the fourth chip U4 and the 3.3V power supply, the other end of the second resistor R2 is connected with the fourth pin of the fourth chip U4 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded; the power supply filter circuit comprises an eighth capacitor C8, one end of the eighth capacitor C8 is connected with the eighth pin of the fourth chip U4, and the other end of the eighth capacitor C8 is connected with the seventh pin of the fourth chip U4 and grounded; the crystal oscillator circuit provides a clock signal for the fourth chip U4, and includes a ninth capacitor C9, a tenth capacitor C10 and a first crystal oscillator X1, wherein one end of the first crystal oscillator X1 is connected to the eleventh pin of the fourth chip U4 and one end of the ninth capacitor C9, the other end of the first crystal oscillator X1 is connected to the twelfth pin of the fourth chip U4 and one end of the tenth capacitor C10, and the other end of the ninth capacitor C9 is connected to the other end of the tenth capacitor C10 and grounded. The first pin, the second pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the sixteenth pin, the nineteenth pin and the twentieth pin of the fourth chip U4 are respectively connected with the relay group driving circuit.

Further, the number of the relay group driving circuits is the same as that of the relay groups, each relay group driving circuit is correspondingly connected with each relay group, each relay group driving circuit comprises a plurality of push-pull circuits, each push-pull circuit comprises a base driving resistor, a current-limiting resistor, an NPN type triode and a PNP type triode, one end of each base driving resistor is connected with the processing module, the other end of each base driving resistor is connected with the base of each NPN type triode and the base of each PNP type triode respectively, the emitting electrode of each NPN type triode and the emitting electrode of each PNP type triode are connected with the relay groups respectively, the collecting electrode of each NPN type triode is connected with one end of each current-limiting resistor, the collecting electrode of each PNP type triode is grounded, and the other end of each current-limiting resistor is connected with the power supply.

In each relay group driving circuit, the number N of the push-pull circuits meets the condition that N is not less than (N-1) the number of the relays in the corresponding relay group.

In a relay group driving circuit, the output ends of any two push-pull circuits control the pull-in or the disconnection of two relays.

The power supply module comprises a rechargeable battery, a charging management circuit and a power supply conversion circuit, the charging management circuit is respectively connected with the USB interface, the rechargeable battery and the power supply conversion circuit, and the power supply conversion circuit is respectively connected with the USB-to-serial port circuit, the processing module and the relay group driving circuit.

Furthermore, the rechargeable battery is a lithium ion battery, and the power conversion circuit outputs a 3.3V power supply.

The utility model has the beneficial effects that: the exchanger capable of customizing the protocol line sequence connects the first interface and the second interface through the relay group according to the customized line sequence, so that the safety is high, the communication is stable, and the short circuit phenomenon caused by wiring errors is not easy to occur. When the line sequence needs to be replaced, the upper computer is only needed to set the line sequence in a user-defined mode, the disassembly or the re-wiring is not needed, the reliability and the efficiency of the wiring are high, the compatibility is good, and meanwhile the method is also suitable for different non-standardized application scenes. In addition, the utility model has no miscellaneous line, and the product is beautiful and easy to maintain.

[ description of the drawings ]

Fig. 1 is a schematic block diagram of the present invention.

Fig. 2 is a wiring schematic of the present invention.

Fig. 3 is a functional block diagram of the control unit of the present invention.

Fig. 4 is a circuit diagram of the control unit of the present invention.

Fig. 5 is a control flow diagram of the present invention.

FIG. 6 is a software flow diagram of a serial port receive interrupt of a fourth chip in the processing module of the present invention.

FIG. 7 is a software process flow diagram of a fourth chip in the processing module of the present invention.

[ detailed description ] embodiments

The following examples are further illustrative and supplementary to the present invention and do not limit the present invention in any way.

As shown in fig. 1, the switch capable of customizing the protocol line sequence of the present invention includes a first interface 11, a second interface 12, a relay group 20, a control unit 30, and an upper computer 40. The first interface 11 and the second interface 12 are respectively disposed at two ends of the protocol line, the relay group 20 is respectively connected with the first interface 11 and the second interface 12, and the control unit 30 is respectively connected with the relay group 20 and the upper computer 40. The device CAN be used in industrial buses such as RS485, 232 and CAN, and CAN be used in non-standardized application scenes generated by communication between network port hardware and standard interfaces, and CAN also be used in other scenes requiring line sequence change.

As shown in fig. 1, the first interface 11 and the second interface 12 are respectively connected with interfaces of different devices to enable connection and/or communication from one device to another. The first interface 11 has at least one pin, and the second interface 12 has at least two pins. The first interface 11 and the second interface 12 may be one of various interfaces, such as a USB interface, a DB9 interface, an RJ45 network interface, and the like. The first interface 11 and the second interface 12 may be the same or different, and may be determined according to actual usage scenarios. In the embodiment shown in fig. 4, the first interface 11 is a DB9 standard interface with nine pins, and the second interface 12 is an RJ45 network interface with eight pins.

As shown in fig. 1, the relay group 20 is connected to the first interface 11 and the second interface 12, respectively, and is used for customizing a line sequence between the first interface 11 and the second interface 12. The relay set 20 is provided with at least one, and the number of the at least one is the same as the number of the pins of the first interface 11, for example, when the number of the pins of the first interface 11 is two, the number of the relay set 20 is also two. It should be noted that, in practical applications, only some pins in the first interface 11 need to be wired, and at this time, the number of the relay groups 20 is the same as the number of the pins that need to be wired in the first interface 11. In the embodiment shown in fig. 4, only the second pin and the third pin are connected in the first interface, and the number of the relay sets 20 is two. Each relay group 20 includes a plurality of relays 21, and the number of the relays 21 in each relay group 20 is the same as the number of pins of the second interface 12, for example, when the number of the pins of the second interface 12 is three, the number of the relays 21 in each relay group 20 is three. The relay 21 is a miniature solid-state signal relay. After the contact common ends of the relays 21 in each relay group 20 are short-circuited, the contacts are sequentially connected with one pin of the first interface 11, the normally open contacts of the relays 21 in each relay group 20 are sequentially connected with one pin of the second interface 12, and by means of attraction or disconnection of the relays 21, any pin of the second interface can be controlled to be connected to a pin of the first interface, so that the first interface 11 and the second interface 12 can be connected randomly. Specifically, in the embodiment shown in fig. 2, the number of the relay groups 20 is nine, and the number of the relays 21 in each relay group 20 is eight. The contact common ends of the eight relays 21 in each relay group 20 are connected to the nine pins of the first interface 11 in sequence after being short-circuited, the normally open contacts of the eight relays 21 in the nine relay groups 20 are connected to the eight pins of the second interface in sequence, and any pin of the second interface 12 can be controlled to be connected to any pin of the first interface 11 by attracting or disconnecting each relay 21, so that the first interface 11 and the second interface 12 can be connected at will.

As shown in fig. 1, the control unit 30 is connected to the relay set 20 and the upper computer 40, and is configured to control the relay 21 in the relay set 20 to be switched on or off. As shown in fig. 3, the control unit 30 includes a USB interface 31, a USB to serial interface circuit 32, a processing module 33, a relay group driving circuit 34, and a power module 35. The USB interface 31 is connected to the upper computer 40 and the USB to serial port circuit 32, and is configured to transmit data of the upper computer 40 to the USB to serial port circuit 32. The processing module 33 is connected to the USB-to-serial port circuit 32 and the relay group driving circuit 34, respectively, and receives data from the USB-to-serial port circuit 32, processes the data, and outputs a control signal to the relay group driving circuit 34. The relay group driving circuits 34 are connected to the relay groups 20, wherein the number of the relay group driving circuits 34 is the same as the number of the relay groups 20, that is, each relay group driving circuit 34 corresponds to one relay group 20, and the relay group driving circuit 34 is used for controlling the actuation or the disconnection of the relays 21 in the relay group 20. The power module 35 is connected to the USB interface 31, the USB to serial port circuit 32, the processing module 33, and the relay group driving circuit 34, and is used to supply power to the USB interface 31, the USB to serial port circuit 32, the processing module 33, and the relay group driving circuit 34.

Specifically, as shown in fig. 4, the USB-to-serial port circuit 32 includes a third chip U3, a sixth capacitor C6, a first diode D1 and a second diode D2, wherein a first pin of the third chip U3 is connected to a third pin of the USB interface 31, a second pin thereof is connected to a second pin of the USB interface 31, a third pin thereof is grounded, a fifth pin thereof is connected to the 5V power supply, a sixth pin thereof is connected to a cathode of the second diode D2, a seventh pin thereof is connected to an anode of the first diode D1, an eighth pin thereof is connected to one end of the sixth capacitor C6, an anode of the second diode D2 and a cathode of the first diode D1 are respectively connected to the processing module 33, and the other end of the sixth capacitor C6 is grounded. In this embodiment, the specific model of the third chip U3 is CH 340N.

As shown in fig. 4, the processing module 33 includes a fourth chip U4 and a peripheral circuit, wherein the fourth chip U4 is connected to the relay group driving circuit 34 and the peripheral circuit, respectively, and the peripheral circuit includes a reset circuit, a power filter circuit, and a crystal oscillator circuit. The reset circuit comprises a second resistor R2 and a seventh capacitor C7, one end of the second resistor R2 is connected with the ninth pin of the fourth chip U4 and the 3.3V power supply, the other end of the second resistor R2 is connected with the fourth pin of the fourth chip U4 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded. The power filter circuit comprises an eighth capacitor C8, one end of the eighth capacitor C8 is connected to the eighth pin of the fourth chip U4, and the other end of the eighth capacitor C8 is connected to the seventh pin of the fourth chip U4 and grounded. The crystal oscillator circuit provides a clock signal for the fourth chip U4, and includes a ninth capacitor C9, a tenth capacitor C10 and a first crystal oscillator X1, wherein one end of the first crystal oscillator X1 is connected to the eleventh pin of the fourth chip U4 and one end of the ninth capacitor C9, the other end of the first crystal oscillator X1 is connected to the twelfth pin of the fourth chip U4 and one end of the tenth capacitor C10, and the other end of the ninth capacitor C9 is connected to the other end of the tenth capacitor C10 and grounded. The first, second, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth and twentieth pins of the fourth chip U4 are connected to the relay group driving circuit 34, respectively. In this embodiment, the specific model of the fourth chip U4 is HC32L110C6 PA.

As shown in fig. 4, the relay group driving circuit 34 includes a plurality of push-pull circuits 341, and in each relay group driving circuit 34, the number N of the push-pull circuits 341 satisfies N × (N-1) ≧ the number of the relays 21 in the corresponding relay group 20, and in the embodiment shown in fig. 4, the number of the push-pull circuits 341 is four, so as to simplify the circuit structure. Each push-pull circuit 341 has the same structure and is connected to the relay 21 in the corresponding relay group 20, the push-pull circuit 341 includes a base driving resistor, a current limiting resistor, an NPN type triode and a PNP type triode, wherein one end of the base driving resistor is connected to the processing module 33, the other end of the base driving resistor is connected to the base of the NPN type triode and the base of the PNP type triode, the emitter of the NPN type triode and the emitter of the PNP type triode are connected to the relay group 20, the collector of the NPN type triode is connected to one end of the current limiting resistor, the collector of the PNP type triode is grounded, and the other end of the current limiting resistor is connected to the power supply. In one relay group driving circuit 34, the output ends of any two push-pull circuits 341 control the pull-in or the disconnection of two relays 21. In the present embodiment, the structure of one of the push-pull circuits 341 is taken as an example for explanation, and the structure of the other push-pull circuits 341 is different only in the relay 21 connected thereto. The push-pull circuit 341 includes a third resistor R3, a fourth resistor R4, a first triode Q1 and a second triode Q2, wherein the third resistor R3 is a base driving resistor, the fourth resistor R4 is a current limiting resistor, the first triode Q1 is an NPN type triode, and the second triode Q2 is a PNP type triode. The push-pull circuit 341 is used to increase the driving capability of the IO port of the fourth chip U4. Specifically, as shown in fig. 4, in the embodiment, one end of the third resistor R3 is connected to the processing module 33, and the other end of the third resistor R3 is connected to bases of the first transistor Q1 and the second transistor Q2, respectively, an emitter of the first transistor Q1 and an emitter of the second transistor Q2 are connected to an anode of an input terminal of the first relay RL11, a cathode of an input terminal of the second relay RL12, an anode of an input terminal of the third relay RL13, a cathode of an input terminal of the fourth relay RL14, an anode of an input terminal of the fifth relay RL15, and a cathode of an input terminal of the sixth relay RL16 in the relay group 20, respectively, a collector of the first transistor Q1 is connected to one end of the fourth resistor R4, a collector of the second transistor Q2 is grounded, and the other end of the fourth resistor R4 is connected to a power supply, where the power supply is 3.3V. The push-pull circuit 341 is configured to improve the driving capability of the IO port of the fourth chip U4, the IO port output current of the fourth chip U4 is generally several milliamperes, and the current of several tens of milliamperes is usually required for the pull-in of the relay 21, taking a JK16 type solid state relay as an example, when the eleventh relay RL11 is pulled in, the output signal AOUT1 of the first pin of the fourth chip U4 is at a high level, the first triode Q1 is turned on, the second triode Q2 is turned off, the output signal AOUT2 of the second pin of the fourth chip U4 is at a low level, the third triode Q3 is turned off, the fourth triode Q4 is turned on, and at this time, the current flows from the 3.3V power supply through the fourth resistor R4 to the first triode Q1, then flows from the input anode of the eleventh relay RL11 to the cathode of the input terminal thereof, and flows to the ground through the fourth triode Q4, at this time, the current of the relay RL11 at this time flows through the following formula:

I＝(VCC–Vce(Q1)–Vce(Q4)–Vf(RL11))/R4；

the VCC is 3.3V, Vce (Q1) is a saturation voltage drop of the first triode Q1 is 0.3V, Vce (Q4) is a saturation voltage drop of the fourth triode Q4 is 0.3V, Vf (RL11) is an on voltage drop of an input diode of the eleventh relay RL11, and is generally between 1.2V and 1.5V, and R4 is a resistance value of the fourth resistor R4 and is 36 ohms. When the conduction voltage drop of the input diode of the eleventh relay RL11 is 1.2V, I ═ (3.3-0.3-0.3-1.2)/36 ═ 0.0417A, that is, 41.7mA, and when the conduction voltage drop of the input diode of the eleventh relay RL11 is 1.5V, I ═ 0.033A, that is, 33 mA.

As shown in fig. 4, when the AOUT1 of the fourth chip U4 outputs a high level, the first transistor Q1 of the push-pull circuit 341 is turned on, the second transistor Q2 is turned off, and the AO1 is at a high level; when the AOUT1 of the fourth chip U4 outputs a low level, the second transistor Q2 of the push-pull circuit 341 is turned on, the first diode Q1 is turned off, and the AO1 is at a low level; when the AOUT1 of the fourth chip U4 outputs a high impedance state, both the first transistor Q1 and the second transistor Q2 of the push-pull circuit 341 are turned off, and the AO1 outputs a high impedance state. Similarly, the third triode Q3, the fourth triode Q4, the fifth triode Q5, the sixth triode Q6, the seventh triode Q7 and the eighth triode Q8 all form a push-pull output circuit, the push-pull circuit can output three states of a high level, a low level and a high resistance state, the four groups of push-pull circuits can control twelve relays at most, when a relay needs to be attracted, the push-pull circuit corresponding to the anode of the input end of the relay is output to the high level, the push-pull circuit corresponding to the cathode of the input end of the relay is output to the low level, and the other push-pull circuits are output to the high resistance state. For example, when the first relay RL1 needs to be engaged, the output AO1 of the first push-pull circuit group may be set to a high level, the output AO2 of the second push-pull circuit group may be set to a low level, and the output AO3 of the third push-pull circuit group and the output AO4 of the fourth push-pull circuit group may be set to a high impedance state.

As shown in fig. 3 and 4, the power module 35 is used for supplying power, and includes a rechargeable battery 351, a charging management circuit 352 and a power conversion circuit 353, wherein the charging management circuit 352 is respectively connected to the USB interface 31, the rechargeable battery 351 and the power conversion circuit 353, and the power conversion circuit 353 is respectively connected to the USB to serial interface circuit 32, the processing module 33 and the relay group driving circuit 34. Specifically, as shown in fig. 4, the rechargeable battery 351 is a lithium ion battery, but may be other types of rechargeable batteries, and the embodiment is not limited thereto. The charging management circuit 352 includes an input end filter circuit, a first resistor R1, and a first chip U1, where the input end filter circuit filters an input power of the first chip U1, the input end filter circuit includes a third capacitor C3 and a fourth capacitor C4, the fourth capacitor C4 is an electrolytic capacitor, one end of the third capacitor C3 is connected to the positive electrode of the fourth capacitor C4, the fourth pin of the first chip U1, and the 5V power supply, the other end of the third capacitor C3 is connected to the negative electrode of the fourth capacitor C4, one end of the first resistor R1 is grounded, the other end of the first resistor R1 is connected to the fifth pin of the first chip U1, the first pin and the second pin of the first chip U1 are grounded, and the third pin of the first chip U1 is connected to the positive electrode of the rechargeable battery 351. In this embodiment, the specific model of the first chip U1 is TP 4055. The power conversion circuit 353 comprises an input end filter circuit, an output end filter circuit and a second chip U2, wherein the input end filter circuit comprises a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is respectively connected with the anode of the second capacitor C2, the first pin and the third pin of the second chip U2 and the anode of the rechargeable battery 351, and the other end of the first capacitor C1, the cathode of the second capacitor C2 and the second pin of the second chip U2 are respectively grounded. The output end filter circuit comprises a fifth capacitor C5, one end of the fifth capacitor C5 and a fifth pin of the second chip U2 are respectively connected with a 3.3V power supply, and the other end of the fifth capacitor C5 and a fourth pin of the second chip U2 are respectively grounded. In this embodiment, the specific model of the second chip U2 is TPS 78233.

As shown in fig. 1, the upper computer 40 is connected to and communicates with the control unit 30, and is configured to custom set a line sequence between the first interface 11 and the second interface 12, and send set data to the control unit 30. For example, when the first interface 11 and the second interface 12 need to be connected, the line sequence of the first interface 11 and the second interface 12 can be set through the upper computer; when the line sequence of the first interface 11 and the second interface 12 needs to be replaced, the line sequence between the first interface 11 and the second interface 12 is reset on the upper computer 40, so that the user-defined wiring requirement is met. The upper computer 40 may be an industrial personal computer or a computer, and is connected to and communicates with the control unit 30 through a USB interface.

As shown in fig. 3 and 4, the working principle of the present invention is: when the upper computer 40 is connected with the control unit 30 through the USB, the 5V power supply of the USB interface charges the rechargeable battery 351 through the charging management circuit 352, and generates a 3.3V power supply through the power conversion circuit 353 to supply power to the USB to serial port circuit 32, the processing module 33, and the relay group driving circuit 34, and at the same time, the upper computer 40 converts the set line sequence data between the first interface 11 and the second interface 12 into serial port data through the USB to serial port circuit 32 to communicate with the processing module 33, and the processing module 33 controls the relay group driving circuit 34 according to the received data. When the upper computer 40 is disconnected from the control unit 30, the rechargeable battery 351 generates a 3.3V power supply through the power conversion circuit 353, and supplies power to the USB to serial port circuit 32, the processing module 33, and the relay group driving circuit 34, so as to maintain the control of the control unit 30 on the relay group 20. That is, when the control unit 30 is disconnected from the upper computer 40, the rechargeable battery 351 can generate 3.3V power through the power conversion circuit 353, so as to meet the power supply requirement.

As shown in fig. 5, the control flow of the present invention is: the upper computer 40 sends a control frame, the control unit 30 receives a control frame command sent by the upper computer 40 and then responds to the control frame, then the upper computer 40 sends a parameter frame, the parameter frame data comprises a parameter for connecting a certain pin of the first jack 11 with a certain pin of the second jack 12, the control unit 30 receives the parameter frame command sent by the upper computer 40 and then responds to the parameter frame, finally, the upper computer 40 sends an end frame, the control unit 30 returns to the end frame after receiving the end frame command sent by the upper computer 40, and meanwhile, the relay group is controlled to act, so that a certain pin of the first jack 11 is connected with a certain pin of the second jack 12. The command table of the control frame, the response control frame, the parameter frame, the response parameter frame, the end frame and the response end frame is shown in table 1.

TABLE 1 Command Table

As shown in fig. 6, the fourth chip U4 enters a serial port to receive an interrupt after receiving data sent by the upper computer 40, first determines whether a received frame header is correct after entering the interrupt, if the frame header is incorrect, it indicates that an interference signal is received, and exits the interrupt, if the received frame header is correct, it receives data, and then determines whether a frame tail is correct, if the frame tail is incorrect, it indicates that the received data is incomplete or erroneous, and exits the interrupt, and if the received frame tail is correct, it indicates that a set of complete data is received, it exits the interrupt routine after setting a flag bit.

As shown in fig. 7, the software processing flow of the fourth chip U4 is as follows: the fourth chip U4 detects whether a flag bit exists in serial port interruption in a circulating way, if the flag bit exists, the fourth chip U4 receives data sent by the upper computer 40, after the data are received, if the current state is a state waiting for receiving a control frame, whether the data are control frame data is judged, if the data are the control frame data, the control frame is sent to respond to the upper computer 40, and the current state is switched to a state waiting for receiving a parameter frame; if the current state is the state waiting for receiving the parameter frame, judging whether the data is parameter frame data, if the data is the parameter frame data, sending a parameter frame response to the upper computer 40, and switching the current state to the state waiting for receiving the finishing frame; if the current state is the state of waiting for receiving the end frame, whether the data is the end frame data or not is judged, if the data is the end frame data, the end frame response is sent to the upper computer 40, the current state is switched to the state of waiting for receiving the control frame, meanwhile, the action of the relay group 20 is controlled, the line sequence between the first interface 11 and the second interface 12 is adjusted, and therefore the connection between the first interface 11 and the second interface 12 is achieved.

Although the present invention has been described with reference to the above embodiments, the scope of the present invention is not limited thereto, and modifications, substitutions and the like of the above members are intended to fall within the scope of the claims of the present invention without departing from the spirit of the present invention.

Claims

1. A switch capable of customizing protocol wire order, the switch comprising:

the device comprises a first interface (11) and a second interface (12), wherein the first interface (11) and the second interface (12) are respectively arranged at two ends of a protocol line; wherein the first interface (11) and the second interface (12) are respectively connected with interfaces of different devices; the first interface (11) is at least provided with one pin, and the second interface (12) is at least provided with two pins;

at least two relay groups (20) respectively connected with the first interface (11) and the second interface (12), wherein the first interface (11) and the second interface (12) are connected through the relay groups (20) according to a user-defined line sequence;

the control unit (30) is connected with the relay set (20), and the control unit (30) controls the relay set (20) to work;

and the upper computer (40) is connected with and communicates with the control unit (30), and the line sequence between the first interface (11) and the second interface (12) is set by the user through the upper computer (40).

2. The switch of the customizable protocol line sequence of claim 1, characterized in that the number of the relay groups (20) is the same as the number of pins of the first interface (11), each relay group (20) comprises a plurality of relays (21), the number of the relays (21) in each relay group (20) is the same as the number of pins of the second interface (12), and after the contact common end of the relays (21) in each relay group (20) is short-circuited, the relay groups are sequentially connected with one pin of the first interface (11), and the normally open contacts of the relays (21) in each relay group (20) are sequentially connected with one pin of the second interface (12).

3. The switch of the self-defined protocol line sequence of claim 1, wherein the control unit (30) comprises a USB interface (31), a USB to serial port circuit (32), a processing module (33), at least two relay group driving circuits (34) and a power module (35), the USB interface (31) is connected to the upper computer (40) and the USB to serial port circuit (32), the processing module (33) is connected to the USB to serial port circuit (32) and the relay group driving circuits (34), each relay group driving circuit (34) is connected to one relay group (20), and the power module (35) is connected to the USB interface (31), the USB to serial port circuit (32), the processing module (33) and the relay group driving circuits (34).

4. The switch of claim 3, wherein the processing module (33) comprises a fourth chip U4 and peripheral circuits, the fourth chip U4 is connected to the relay group driving circuit (34) and the peripheral circuits, respectively, and the peripheral circuits comprise a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a second resistor R2 and a first crystal oscillator X1.

5. The switch of the customizable protocol line sequence of claim 4, wherein the peripheral circuit comprises a reset circuit, a power filter circuit and a crystal oscillator circuit;

the reset circuit comprises a second resistor R2 and a seventh capacitor C7, one end of the second resistor R2 is connected with the ninth pin of the fourth chip U4 and the 3.3V power supply, the other end of the second resistor R2 is connected with the fourth pin of the fourth chip U4 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded; the power supply filter circuit comprises an eighth capacitor C8, one end of the eighth capacitor C8 is connected with the eighth pin of the fourth chip U4, and the other end of the eighth capacitor C8 is connected with the seventh pin of the fourth chip U4 and grounded; the crystal oscillator circuit provides a clock signal for the fourth chip U4, and comprises a ninth capacitor C9, a tenth capacitor C10 and a first crystal oscillator X1, wherein one end of the first crystal oscillator X1 is respectively connected with an eleventh pin of the fourth chip U4 and one end of a ninth capacitor C9, the other end of the first crystal oscillator X1 is respectively connected with a twelfth pin of the fourth chip U4 and one end of the tenth capacitor C10, and the other end of the ninth capacitor C9 is connected with the other end of the tenth capacitor C10 and grounded; the first, second, thirteenth, fourteenth, fifteenth, sixteenth, nineteenth and twentieth pins of the fourth chip U4 are respectively connected with the relay set driving circuit (34).

6. The switch of claim 3, wherein the number of the relay group driving circuits (34) is the same as the number of the relay groups (20), each relay group driving circuit (34) is respectively connected to each relay group (20) in turn, each relay group driving circuit (34) comprises a plurality of push-pull circuits (341), each push-pull circuit (341) comprises a base driving resistor, a current limiting resistor, an NPN type triode and a PNP type triode, one end of the base driving resistor is connected to the processing module (33), the other end of the base driving resistor is connected to the bases of the NPN type triode and the PNP type triode, the emitter of the NPN type triode and the emitter of the PNP type triode are respectively connected to the relay groups (20), and the collector of the NPN type triode is connected to one end of the current limiting resistor, the collector of the PNP type triode is grounded, and the other end of the current-limiting resistor is connected with a power supply.

7. The switch of customizable protocol line sequences according to claim 6, characterized in that in each relay group driving circuit (34), the number N of the push-pull circuits (341) satisfies N x (N-1) ≧ the number of relays (21) in the corresponding relay group.

8. The switch of customizable protocol line sequence according to claim 6, characterized in that, in one relay group driving circuit (34), the output ends of any two push-pull circuits (341) control the connection or disconnection of two relays (21).

9. The switch of the customizable protocol line sequence of claim 3, wherein the power module (35) comprises a rechargeable battery (351), a charging management circuit (352) and a power conversion circuit (353), the charging management circuit (352) is respectively connected with the USB interface (31), the rechargeable battery (351) and the power conversion circuit (353), and the power conversion circuit (353) is respectively connected with the USB to serial port circuit (32), the processing module (33) and the relay group driving circuit (34).

10. The customizable protocol line-sequential exchanger of claim 9, wherein the rechargeable battery (351) is a lithium ion battery and the power conversion circuit (353) outputs 3.3V power.