CN215526410U - Multisource data acquisition system based on analog signal conditioning circuit - Google Patents
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Abstract
The utility model discloses a multisource data acquisition system based on an analog signal conditioning circuit, which belongs to the technical field of multisource data acquisition and comprises a GPS (global positioning system) adapter board, an FPGA (field programmable gate array) core board, an interface board and a power board, wherein the interface board comprises an inertial navigation unit, an inclination angle sensor, a coder, an AD (analog-to-digital) acquisition module, a displacement sensor, a temperature sensor and a laser displacement sensor, the AD acquisition module comprises the analog signal conditioning circuit and an AD conversion chip, the FPGA is used as a main control chip, and the high-precision real-time synchronous acquisition of data of the displacement sensor, the temperature sensor, the laser displacement sensor and other sensors is realized by controlling the AD sampling frequency. The amplitude of the output analog signal which can be accepted by inputting the signal to the AD through the signal conditioning and amplifying circuit is 0V to 4V after the amplitude of the analog signal input by the displacement sensor is increased from 0V to 10V, the cut-off bandwidth frequency is about 6kHZ within the range of the acceptable amplitude of the AD, and the noise can be effectively filtered.
Description
Technical Field
The utility model belongs to the technical field of multi-source data acquisition, and particularly relates to a multi-source data acquisition system based on an analog signal conditioning circuit.
Background
High-precision synchronous acquisition of multi-source heterogeneous data is one of key technologies in a track dynamic-static combination detection system. The track dynamic and static combination detection system takes an inertia measurement system as a core measurement unit, and is assisted by various high-precision sensors such as a total station, a GPS, a track gauge, an inclination angle, a speedometer, a sleeper identification and the like, so that the rapid detection of the geometric dimension of a railway track is realized. Due to the dynamic measurement mode of the track dynamic and static combined rapid detection system, the measurement speed is high, the sampling frequency is high, a large amount of multi-source data needs to be synchronously acquired, processed and stored, and is uploaded to the control center in real time for subsequent comprehensive calculation, and therefore higher performance requirements are provided for the multi-source data acquisition module.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem of providing a multisource data acquisition system based on an analog signal conditioning circuit, which takes an FPGA as a main control chip, takes an Invitta TX2 as a core data processing unit, establishes a high-precision time reference by utilizing a high-stability crystal oscillator, PPS pulses output by a GPS and NEMA data, and realizes high-precision real-time synchronous acquisition of data of a plurality of sensors such as a displacement sensor, a temperature sensor, a laser displacement sensor and the like by controlling an AD sampling frequency.
The utility model adopts the following technical scheme for solving the technical problems:
a multisource data acquisition system based on an analog signal conditioning circuit comprises a GPS (global positioning system) adapter plate, an FPGA (field programmable gate array) core plate, an interface board and a power board, wherein the GPS adapter plate and the interface board are respectively connected with the FPGA core plate, and the power board is respectively connected with the GPS adapter plate, the FPGA core plate and the interface board;
the FPGA core board comprises a high-stability crystal oscillator module, an FPGA main control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface, wherein the high-stability crystal oscillator module is connected with the FPGA main control module, the FPGA main control module is connected with the data processing center through the USB transmission module and the serial port module respectively, and the USB interface, the gigabit network interface and the HDMI interface are connected with the data processing center respectively;
the interface board comprises an inertial navigation unit, an inclination angle sensor, an encoder, an AD acquisition module, a displacement sensor, a temperature sensor and a laser displacement sensor, wherein the displacement sensor, the temperature sensor and the laser displacement sensor are respectively connected with the AD acquisition module, and the inertial navigation unit, the inclination angle sensor, the encoder and the AD acquisition module are respectively connected with the FPGA main control module;
the AD acquisition module comprises an analog signal conditioning circuit and an AD conversion chip, and the displacement sensor, the temperature sensor and the laser displacement sensor are respectively connected with the FPGA main control module through the analog signal conditioning circuit and the AD conversion chip in sequence;
the analog signal conditioning circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a voltage input VIN end and a voltage output VOUT end, wherein the voltage input VIN end is connected with one end of the first resistor R1, the other end of the first resistor R1 is respectively connected with the negative input end of the first operational amplifier U1, one end of the second resistor R2 and one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected with the other end of the second resistor R2, the output end of the first operational amplifier U1 and one end of the fifth resistor R5, the other end of the fifth resistor R5 is respectively connected with one end of the second capacitor C2, one end of the sixth resistor R6 and the negative input end of the second operational amplifier U2, the other end of the second capacitor C2 is connected to the other end of the sixth resistor R6, the output end of the second operational amplifier U2 and the voltage output VOUT end, the positive input end of the second operational amplifier U2 is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, the other end of the seventh resistor R7 and the other end of the eighth resistor R8 are connected to ground, the positive input end of the first operational amplifier U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, the other end of the third resistor R3 and the other end of the fourth resistor R4 are connected to ground
As a further preferable scheme of the multisource data acquisition system based on the analog signal conditioning circuit, the FPGA main control module adopts Artix-7 series FPGA of Xilinx company as a main control chip.
As a further preferable solution of the multi-source data acquisition system based on the analog signal conditioning circuit of the present invention, the data processing center employs JetsonTX2 from NVIDIA corporation.
As a further preferable scheme of the multisource data acquisition system based on the analog signal conditioning circuit, the AD acquisition module comprises the analog signal conditioning circuit and an AD conversion chip, and the displacement sensor, the temperature sensor and the laser displacement sensor are respectively connected with the FPGA main control module through the analog signal conditioning circuit and the AD conversion chip in sequence.
As a further preferable scheme of the multisource data acquisition system based on the analog signal conditioning circuit, the model of the AD conversion chip is AD 7689.
As a further preferable scheme of the multi-source data acquisition system based on the analog signal conditioning circuit, the chip type of the USB transmission module is XY7C 68013.
As a further preferable scheme of the multisource data acquisition system based on the analog signal conditioning circuit, the chip model of the high-stability crystal oscillator module is 7 N710.000MBP.
As a further preferable scheme of the multi-source data acquisition system based on the analog signal conditioning circuit, the high-stability crystal oscillator module includes a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69, and a voltage VCC terminal, an 8 interface of the control chip 7N10.000MBP is connected to one end of the resistor R22, the other end of the resistor R22 is connected to one end of a capacitor C45, an 9 interface of the control chip 7N10.000MBP, one end of the resistor R23, and the voltage VCC terminal, the other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected to one end of the resistor R24, the other end of the resistor R24 is grounded, a 10 interface of the control chip 7N10.000MBP is connected to one end of the capacitor C69, and the other end of the capacitor C69 is grounded.
As a further preferable scheme of the multi-source data acquisition system based on the analog signal conditioning circuit, the GPS patch panel includes a chip OEM-719, a voltage VCC terminal, a resistor R79, a capacitor C12, a capacitor C67, and a capacitor C68, the voltage VCC terminal is connected to one end of the resistor R79, the other end of the resistor R79 is connected to the 5 port of the chip OEM-719 and one end of the capacitor C12, the other end of the capacitor C12 is grounded, the 2 port of the chip OEM-719 is connected to one end of the capacitor C67, one end of the capacitor C68, and the voltage VCC terminal, and the other end of the capacitor C67 is connected to the other end of the capacitor C68 and grounded.
Compared with the prior art, the utility model adopting the technical scheme has the following technical effects:
1. the utility model takes FPGA as a main control chip, takes Invitta TX2 as a core data processing unit, establishes a high-precision time reference by utilizing a high-stability crystal oscillator, and combining PPS (pulse per second) pulse and NEMA (network asynchronous receiver and amplifier) data output by a GPS (global positioning system), and realizes high-precision real-time synchronous acquisition of data of multiple sensors such as a displacement sensor, a temperature sensor and a laser displacement sensor by controlling AD (analog-to-digital) sampling frequency;
2. the interface board control module is used as an intermediate component for connecting the FPGA core board and the sensors, mainly completes the functions of conditioning data signals of each sensor, level conversion, AD conversion and the like, and connects the converted signals to an FPGA chip of the FPGA core board through two rows of socket pins, and the FPGA chip completes the synchronous acquisition of data of each sensor according to a set time interval;
3. the amplitude of the signals which can be accepted by inputting the analog signals output by the displacement sensor and the laser displacement sensor into the AD through the signal conditioning and amplifying circuit is 0V to 4V after the amplitude of the analog signals input by the displacement sensor is increased from 0V to 10V, and the cut-off bandwidth frequency of the analog signals is about 6kHZ within the range of the acceptable amplitude of the AD, so that the noise can be effectively filtered;
4. because the amplitudes of analog signals output by the displacement sensor and the laser displacement sensor are possibly different, and the acceptable input voltage range of the AD7689 is 0-4.096V, the analog signals output by the sensors cannot be directly input to an AD conversion chip, the analog signals need to be conditioned into the acceptable analog signals input by the AD through a signal conditioning circuit, and the amplitudes of the analog signals are ensured to be uniform;
5. the FPGA main control module adopts Artix-7 series FPGA of Xilinx company as a main control chip, the chip provides the lowest system cost and power consumption of the industry, the device provides the highest performance power consumption ratio structure, the line speed of a transceiver, the DSP processing capacity and the AMS integration in a single FPGA with optimized cost, and the lowest cost and power consumption are optimized and realized in various general logics and DSP application;
6. the high-stability crystal oscillator module has good short-term stability and high long-term precision of PPS (pulse per second) output by the GPS, and adopts the PPS output by the GPS to domesticate a high-temperature crystal oscillator so as to establish a high-precision time reference;
7. the GPS adapter board of the utility model installs the GPS module on the circuit board and completes the level conversion of the PPS signal and the NEMA signal output by the GPS module, the FPGA is connected with the PPS and the UART port through the interface board, reads the NEMA data of the GPS, and establishes a high-precision time reference in the FPGA by combining the PPS signal and the high-stability quartz crystal oscillator.
Drawings
FIG. 1 is a schematic diagram of the structure of a multi-source data acquisition system based on an analog signal conditioning circuit according to the present invention;
FIG. 2 is a schematic diagram of the structure of the FPGA core board of the present invention;
FIG. 3 is a schematic diagram of the structure of the interface board of the present invention;
FIG. 4 is a circuit diagram of an analog signal conditioning circuit of the present invention;
FIG. 5 is a circuit diagram of the high stability crystal oscillator module of the present invention;
fig. 6 is a circuit diagram of a GPS patch panel of the present invention.
Detailed Description
The technical scheme of the utility model is further explained in detail by combining the attached drawings:
example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A multi-source data acquisition system based on an analog signal conditioning circuit is shown in figure 1 and comprises a GPS adapter plate, an FPGA core plate, an interface plate and a power supply plate, wherein the GPS adapter plate and the interface plate are respectively connected with the FPGA core plate; the utility model takes FPGA as a main control chip, takes Invitta TX2 as a core data processing unit, utilizes a high-stability crystal oscillator, combines PPS (pulse per second) pulse output by a GPS (global positioning system) and NEMA (network asynchronous receiver and amplifier) data to establish a high-precision time reference, and realizes high-precision real-time synchronous acquisition of data of a plurality of sensors such as a displacement sensor, a temperature sensor, a laser displacement sensor and the like by controlling AD (analog-to-digital) sampling frequency.
As shown in fig. 2, the FPGA core board includes a high-stability crystal oscillator module, an FPGA main control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface, and an HDMI interface, the high-stability crystal oscillator module is connected to the FPGA main control module, the FPGA main control module is connected to the data processing center through the USB transmission module and the serial port module, and the USB interface, the gigabit network interface, and the HDMI interface are connected to the data processing center;
as shown in fig. 3, the interface board includes an inertial navigation unit, a tilt angle sensor, an encoder, an AD acquisition module, a displacement sensor, a temperature sensor, and a laser displacement sensor, the temperature sensor, and the laser displacement sensor are respectively connected to the AD acquisition module, and the inertial navigation unit, the tilt angle sensor, the encoder, and the AD acquisition module are respectively connected to the FPGA main control module.
The AD acquisition module comprises an analog signal conditioning circuit and an AD conversion chip, and the displacement sensor, the temperature sensor and the laser displacement sensor are respectively connected with the FPGA main control module through the analog signal conditioning circuit and the AD conversion chip in sequence;
as shown in fig. 4, the analog signal conditioning circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a voltage input VIN end and a voltage output VOUT end, the voltage input VIN end is connected to one end of a first resistor R1, the other end of the first resistor R1 is connected to the negative input end of the first operational amplifier U1, one end of the second resistor R2 and one end of a first capacitor C1, the other end of the first capacitor C1 is connected to the other end of the second resistor R2, the output end of the first operational amplifier U1 and one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the second capacitor C2, one end of the sixth resistor R87458 and the negative input end of the operational amplifier U2, the other end of the second capacitor C2 is connected to the other end of the sixth resistor R6, the output end of the second operational amplifier U2 and the voltage output VOUT end, the positive input end of the second operational amplifier U2 is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, the other end of the seventh resistor R7 and the other end of the eighth resistor R8 are connected to ground, the positive input end of the first operational amplifier U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, and the other end of the third resistor R3 and the other end of the fourth resistor R4 are connected to ground.
The interface board control module is used as an intermediate component for connecting the FPGA core board and the sensors, mainly completes the functions of conditioning data signals of each sensor, level conversion, AD conversion and the like, and connects the converted signals to an FPGA chip of the FPGA core board through two rows of socket plugs, and the FPGA chip completes the synchronous acquisition of data of each sensor according to a set time interval.
The amplitude of the signals which can be accepted by the displacement sensor and the laser displacement sensor and are input to the AD through the signal conditioning and amplifying circuit is 0V to 4V after the amplitude of the analog signals input by the displacement sensor is increased from 0V to 10V, the cut-off bandwidth frequency of the analog signals is about 6kHZ within the range of the acceptable amplitude of the AD, and the noise can be effectively filtered.
According to the utility model, because the amplitudes of analog signals output by the displacement sensor and the laser displacement sensor are possibly different, and the acceptable input voltage range of the AD7689 is 0-4.096V, the analog signals output by the sensors cannot be directly input to the AD conversion chip, and the analog signals need to be conditioned into the acceptable analog signals input by the AD through the signal conditioning circuit, and the amplitudes of the analog signals are ensured to be uniform.
The FPGA main control module adopts Artix-7 series FPGA of Xilinx company as a main control chip, an FPGA core board is used as a core component of the whole track dynamic and static combination rapid detection multi-source data acquisition system, the sub-module mainly completes processing of high-speed signal interfaces such as a gigabit network, a USB3.0 and an HDMI, core tasks such as AD conversion control and data transmission, high-precision time reference establishment data synchronous acquisition and encoder data synchronous acquisition and the like, and is connected with an interface board in a buckling mode through a connector.
The data processing center employs JetsonTX2 from NVIDIA corporation. According to the utility model, a high-precision time reference is established through the high-stability crystal oscillator and the PPS pulse and NEMA data output by the GPS adapter plate, the advantage of high-speed parallel of the FPGA is fully exerted, and synchronous acquisition control of data of multiple sensors such as an inertial navigation sensor, an encoder, a displacement sensor, a temperature sensor and a laser displacement sensor on an interface plate is realized; the Jetson TX2 of NVIDIA company is used as a data processing and fusing center, TX2 can be communicated with an upper computer through a gigabit network interface, receives a control instruction sent by the upper computer, is communicated with an FPGA chip on an FPGA core board through a serial port, and uploads sensor data synchronously acquired by the FPGA to TX2 through a USB transmission module to perform data processing, fusing and storing; the high-efficiency DC/DC conversion module and the power conversion chip are integrated on the power panel, so that high-efficiency power conversion is realized, a power supply can be provided for each module, and the stable operation of the whole system is guaranteed.
AD acquisition module contains analog signal conditioning circuit and AD conversion chip, displacement sensor, temperature sensor, laser displacement sensor are connected FPGA host system through analog signal conditioning circuit and AD conversion chip respectively in proper order. The model of the AD conversion chip is AD 7689.
The chip model of the USB transmission module is XY7C 68013.
As shown in fig. 5, the chip model of the high-stability crystal oscillator module is 7 N710.000MBP. The high-stability crystal oscillator module comprises a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC end, wherein an 8 interface of the control chip 7N10.000MBP is connected with one end of a resistor R22, the other end of the resistor R22 is respectively connected with one end of a capacitor C45, an 9 interface of the control chip 7N10.000MBP, one end of a resistor R23 and the voltage VCC end, the other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected with one end of a resistor R24, the other end of the resistor R24 is grounded, a 10 interface of the control chip 7N10.000MBP is connected with one end of the capacitor C69, and the other end of the capacitor C69 is grounded. The high-stability crystal oscillator module has good short-term stability and high long-term precision of the PPS pulse output by the GPS, and the PPS pulse output by the GPS is adopted to domesticate the high-temperature crystal oscillator so as to establish a high-precision time reference.
As shown in fig. 6, the GPS patch panel includes a chip OEM-719, a voltage VCC terminal, a resistor R79, a capacitor C12, a capacitor C67, and a capacitor C68, the voltage VCC terminal is connected to one end of the resistor R79, the other end of the resistor R79 is respectively connected to the 5 port of the chip OEM-719 and one end of the capacitor C12, the other end of the capacitor C12 is grounded, the 2 port of the chip OEM-719 is respectively connected to one end of the capacitor C67, one end of the capacitor C68, and the voltage VCC terminal, and the other end of the capacitor C67 is connected to the other end of the capacitor C68 and grounded. The GPS adapter board of the utility model installs the GPS module on the circuit board and completes the level conversion of the PPS signal and the NEMA signal output by the GPS module, the FPGA is connected with the PPS and the UART port through the interface board, reads the NEMA data of the GPS, and establishes a high-precision time reference in the FPGA by combining the PPS signal and the high-stability quartz crystal oscillator.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the utility model. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the utility model.
Claims (8)
1. The utility model provides a multisource data acquisition system based on analog signal conditioning circuit which characterized in that: the GPS adapter plate and the interface board are respectively connected with the FPGA core board, and the power board is respectively connected with the GPS adapter plate, the FPGA core board and the interface board;
the FPGA core board comprises a high-stability crystal oscillator module, an FPGA main control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface, wherein the high-stability crystal oscillator module is connected with the FPGA main control module, the FPGA main control module is connected with the data processing center through the USB transmission module and the serial port module respectively, and the USB interface, the gigabit network interface and the HDMI interface are connected with the data processing center respectively;
the interface board comprises an inertial navigation unit, an inclination angle sensor, an encoder, an AD acquisition module, a displacement sensor, a temperature sensor and a laser displacement sensor, wherein the displacement sensor, the temperature sensor and the laser displacement sensor are respectively connected with the AD acquisition module, and the inertial navigation unit, the inclination angle sensor, the encoder and the AD acquisition module are respectively connected with the FPGA main control module;
the AD acquisition module comprises an analog signal conditioning circuit and an AD conversion chip, and the displacement sensor, the temperature sensor and the laser displacement sensor are respectively connected with the FPGA main control module through the analog signal conditioning circuit and the AD conversion chip in sequence;
the analog signal conditioning circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a voltage input VIN end and a voltage output VOUT end, wherein the voltage input VIN end is connected with one end of the first resistor R1, the other end of the first resistor R1 is respectively connected with the negative input end of the first operational amplifier U1, one end of the second resistor R2 and one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected with the other end of the second resistor R2, the output end of the first operational amplifier U1 and one end of the fifth resistor R5, the other end of the fifth resistor R5 is respectively connected with one end of the second capacitor C2, one end of the sixth resistor R6 and the negative input end of the second operational amplifier U2, the other end of the second capacitor C2 is connected to the other end of the sixth resistor R6, the output end of the second operational amplifier U2 and the voltage output VOUT end, the positive input end of the second operational amplifier U2 is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, the other end of the seventh resistor R7 and the other end of the eighth resistor R8 are connected to ground, the positive input end of the first operational amplifier U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, and the other end of the third resistor R3 and the other end of the fourth resistor R4 are connected to ground.
2. The analog signal conditioning circuit-based multi-source data acquisition system of claim 1, wherein: the FPGA main control module adopts Artix-7 series FPGA of Xilinx company as a main control chip.
3. The analog signal conditioning circuit-based multi-source data acquisition system of claim 1, wherein: the data processing center employs JetsonTX2 from NVIDIA corporation.
4. The analog signal conditioning circuit-based multi-source data acquisition system of claim 1, wherein: the model of the AD conversion chip is AD 7689.
5. The analog signal conditioning circuit-based multi-source data acquisition system of claim 1, wherein: the chip model of the USB transmission module is XY7C 68013.
6. The analog signal conditioning circuit-based multi-source data acquisition system of claim 1, wherein: the chip model of the high-stability crystal oscillator module is 7 N710.000MBP.
7. The analog signal conditioning circuit-based multi-source data acquisition system of claim 1, wherein: the high-stability crystal oscillator module comprises a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC end, wherein an 8 interface of the control chip 7N10.000MBP is connected with one end of a resistor R22, the other end of the resistor R22 is respectively connected with one end of a capacitor C45, an 9 interface of the control chip 7N10.000MBP, one end of a resistor R23 and the voltage VCC end, the other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected with one end of a resistor R24, the other end of the resistor R24 is grounded, a 10 interface of the control chip 7N10.000MBP is connected with one end of the capacitor C69, and the other end of the capacitor C69 is grounded.
8. The analog signal conditioning circuit-based multi-source data acquisition system of claim 1, wherein: the GPS adapter plate comprises a chip OEM-719, a voltage VCC end, a resistor R79, a capacitor C12, a capacitor C67 and a capacitor C68, wherein the voltage VCC end is connected with one end of the resistor R79, the other end of the resistor R79 is respectively connected with a 5 port of the chip OEM-719 and one end of the capacitor C12, the other end of the capacitor C12 is grounded, a 2 port of the chip OEM-719 is respectively connected with one end of the capacitor C67, one end of the capacitor C68 and the voltage VCC end, and the other end of the capacitor C67 is connected with the other end of the capacitor C68 and grounded.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114915352A (en) * | 2022-04-11 | 2022-08-16 | 南京理工大学 | PWM modulation-demodulation control system based on FPGA |
| CN116112386A (en) * | 2022-11-25 | 2023-05-12 | 浙江华章科技有限公司 | State diagnosis management system of high-value equipment of paper making line |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114915352A (en) * | 2022-04-11 | 2022-08-16 | 南京理工大学 | PWM modulation-demodulation control system based on FPGA |
| CN116112386A (en) * | 2022-11-25 | 2023-05-12 | 浙江华章科技有限公司 | State diagnosis management system of high-value equipment of paper making line |
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