CN215378886U - Energy efficiency relaxation oscillator - Google Patents

Energy efficiency relaxation oscillator Download PDF

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CN215378886U
CN215378886U CN202120742067.8U CN202120742067U CN215378886U CN 215378886 U CN215378886 U CN 215378886U CN 202120742067 U CN202120742067 U CN 202120742067U CN 215378886 U CN215378886 U CN 215378886U
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interface
transistor
transmission gate
capacitor
gate
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陈世军
王欣
李梧萤
施永明
解宁
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Shanghai Institute of Technical Physics of CAS
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Shanghai Institute of Technical Physics of CAS
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Abstract

The patent relates to an energy efficiency relaxation oscillator, which adjusts high and low threshold voltages (VA and VB) so as to adjust the threshold voltage of a comparator I1 and realize the programmability of the frequency of the oscillator. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are respectively charged by the reference voltages VREFP and VREFN to regulate the overdrive voltages of M2 and M3 due to the power consumption of the circuit and gm/IdInversely, the higher the value, the lower the power consumption, so the overall power consumption of the oscillator circuit is reduced by adjusting the values of the reference voltages VREFP and VREFN, and the energy efficiency of the oscillator circuit is improved. This patent further improves efficiency rate of utilization, reduction consumption.

Description

Energy efficiency relaxation oscillator
Technical Field
The patent relates to the technical field of electronic equipment, in particular to an energy efficiency relaxation oscillator for further improving the energy efficiency utilization rate and reducing the power consumption.
Background
The 21 st century is a brand new information age, and the development of the information technology industry changes the world to a great extent and changes the lives of people. Low power consumption systems such as wireless sensor nodes have been widely used in the fields of portable wearable devices, bio-medicine, and the like. And in these fields of application, the hardware system is required to maintain a long operation time, i.e. the hardware system needs to have low power consumption. The wireless sensor typically enters an idle mode after operating for a period of time, and the clock source is the only circuit operating in the idle mode to perform the "wake-up" function. In low power consumption applications, a relaxation oscillator is usually used as a clock source to wake up other circuit modules in a sleep state. Therefore, the design of a relaxation oscillator with high precision and low power consumption is always the research focus of scholars at home and abroad.
There is a need for an energy efficient relaxation oscillator that further improves energy efficient usage and reduces power consumption.
Disclosure of Invention
The patent aims to provide an energy efficiency relaxation oscillator which further improves the energy efficiency utilization rate and reduces the power consumption.
An energy efficient relaxation oscillator, comprising:
the oscillator is provided with a high threshold voltage interface VA, a low threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN and an output signal interface VO respectively;
the first reference voltage interface VREFP is connected to a source of a transistor M1, a gate of the transistor M1 is connected to a V2 interface, one way of a drain of the transistor M1 is connected to a capacitor C1, one way is connected to a source of a transistor M2, one way of a gate of the transistor M2 is connected to a V1 interface, one way is connected to a gate of the transistor M3, one way of a source of the transistor M3 is connected to a capacitor C2, one way is connected to a drain of a transistor M4, the capacitor C2 is grounded, a gate of the transistor M4 is connected to a V2 interface, a source of the transistor M4 is connected to a second reference voltage interface VREFN, after the drain of the transistor M2 and the drain of the transistor M3 are connected, one way is connected to a capacitor C3, one way is connected to an INP interface of a comparator I1, the capacitor C3 is grounded, an INN interface of the comparator I1 is connected to an OUT interface of a transmission gate I4, one way is connected to an OUT interface of a transmission gate I5, and an interface V1 of the comparator I1 is connected to an inverter 2, one path is connected with a V1 interface, the other path of the phase inverter I2 is connected with a phase inverter I3, the other path is connected with a V2 interface, and the phase inverter I3 is connected with an output signal interface VO;
an IN interface of the transmission gate I4 is connected with a high threshold voltage interface VA, a VP interface of the transmission gate I4 is connected with an output signal interface VO, a VN interface of the transmission gate I4 is connected with a V2 interface, an IN interface of the transmission gate I5 is connected with a low threshold voltage interface VB, a VN interface of the transmission gate I5 is connected with the output signal interface VO, and a VP interface of the transmission gate I5 is connected with a V2 interface.
The transmission gate I5 and the transmission gate I4 have the same structure and are transmission gates TG respectively.
The VN interface of the transmission gate TG is connected with the gate of a transistor M5, the source of the transistor M5 is connected with the source of a transistor M6 and then connected with the OUT interface, the drain of the transistor M5 is connected with the drain of a transistor M6 and then connected with the IN interface, and the gate of the transistor M6 is connected with the VP interface.
One end of the capacitor C1 is wired.
The direction of the comparator I1, the inverter I2 and the inverter I3 is towards the output signal interface VO.
The transistor M5 is a PMOS transistor and the transistor M6 is an NMOS transistor.
The voltages of the first reference voltage interface VREFP and the second reference voltage interface VREFN are adjustable.
The oscillator is provided with a high-threshold voltage interface VA, a low-threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN and an output signal interface VO respectively; a first reference voltage interface VREFP is connected to a source of the transistor M1, a gate of the transistor M1 is connected to the V2 interface, one way of a drain of the transistor M1 is connected to the capacitor C1, one way of the transistor is connected to a source of the transistor M2, one way of a gate of the transistor M2 is connected to the V2 interface, one way of the transistor is connected to a gate of the M2, one way of the source of the transistor M2 is connected to the capacitor C2, one way of the transistor is connected to a drain of the transistor M2, the capacitor C2 is grounded, a gate of the transistor M2 is connected to the V2 interface, a source of the transistor M2 is connected to the second reference voltage interface VREFN, a drain of the M2 is connected to a drain of the M2, one way of the capacitor C2 is connected to the INP interface of the comparator I2, the capacitor C2 is grounded, an INN interface of the comparator I2 is connected to the OUT interface of the transmission gate I2, one way of the comparator I2 is connected to the inverter I2, and one way of the inverter I2 is connected to the inverter 2. The inverter I3 is connected with an output signal interface VO; an IN interface of the transmission gate I4 is connected with a high threshold voltage interface VA, a VP interface of the transmission gate I4 is connected with an output signal interface VO, a VN interface of the transmission gate I4 is connected with a V2 interface, an IN interface of the transmission gate I5 is connected with a low threshold voltage interface VB, a VN interface of the transmission gate I5 is connected with the output signal interface VO, and a VP interface of the transmission gate I5 is connected with a V2 interface. This patent further improves efficiency rate of utilization, reduction consumption.
The programmable oscillator frequency is realized by adjusting the high and low threshold voltages (VA and VB) so as to adjust the threshold voltage of the comparator I1. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are respectively charged by the reference voltages VREFP and VREFN to regulate the overdrive voltages of M2 and M3 due to the power consumption of the circuit and gm/IdInversely, the higher the value, the lower the power consumption, so the overall power consumption of the oscillator circuit is reduced by adjusting the values of the reference voltages VREFP and VREFN, and the energy efficiency of the oscillator circuit is improved.
Drawings
FIG. 1 is an overall block diagram of the present patent;
FIG. 2 is a first internal circuit diagram of the present patent;
FIG. 3 is a second internal circuit diagram of the present patent;
FIG. 4 is a circuit diagram of a transmission gate TG of the present patent;
in the figure: 1. an oscillator.
Detailed Description
The patent is further described with reference to the following drawings and specific examples.
An energy efficient relaxation oscillator, comprising: the device comprises an oscillator 1, wherein the oscillator 1 is respectively provided with a high threshold voltage interface VA, a low threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN and an output signal interface VO; a first reference voltage interface VREFP is connected to a source of the transistor M1, a gate of the transistor M1 is connected to the V2 interface, one way of a drain of the transistor M1 is connected to the capacitor C1, one way of the transistor is connected to a source of the transistor M2, one way of a gate of the transistor M2 is connected to the V2 interface, one way of the transistor is connected to a gate of the M2, one way of the source of the transistor M2 is connected to the capacitor C2, one way of the transistor is connected to a drain of the transistor M2, the capacitor C2 is grounded, a gate of the transistor M2 is connected to the V2 interface, a source of the transistor M2 is connected to the second reference voltage interface VREFN, a drain of the M2 is connected to a drain of the M2, one way of the capacitor C2 is connected to the INP interface of the comparator I2, the capacitor C2 is grounded, an INN interface of the comparator I2 is connected to the OUT interface of the transmission gate I2, one way of the comparator I2 is connected to the inverter I2, and one way of the inverter I2 is connected to the inverter 2. The inverter I3 is connected with an output signal interface VO; an IN interface of the transmission gate I4 is connected with a high threshold voltage interface VA, a VP interface of the transmission gate I4 is connected with an output signal interface VO, a VN interface of the transmission gate I4 is connected with a V2 interface, an IN interface of the transmission gate I5 is connected with a low threshold voltage interface VB, a VN interface of the transmission gate I5 is connected with the output signal interface VO, and a VP interface of the transmission gate I5 is connected with a V2 interface.
The transmission gate I5 and the transmission gate I4 have the same structure, and are transmission gates TG, respectively. The VN interface of the transmission gate TG is connected to the gate of the transistor M5, the source of the transistor M5 is connected to the source of the transistor M6 and then to the OUT interface, the drain of the transistor M5 is connected to the drain of the transistor M6 and then to the IN interface, and the gate of the transistor M6 is connected to the VP interface. One terminal of the capacitor C1 is wired. The direction of the comparator I1, the inverter I2 and the inverter I3 is towards the output signal interface VO. The transistor M5 is a PMOS transistor, and the transistor M6 is an NMOS transistor. The voltages of the first reference voltage interface VREFP and the second reference voltage interface VREFN are adjustable.
An energy efficient relaxation oscillator, oscillator 1(Comparator) comprises two voltage references (VREFP, VREFN), two high and low threshold voltage inputs (VA, VB), and an output signal (VO). The circuit comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4, a capacitor C1, a capacitor C2, a capacitor C3, a comparator I1, an inverter I2, an inverter I3, a transmission gate I4 and a transmission gate I5. The specific structure of the transmission gate TG is composed of a PMOS transistor M5 and an NMOS transistor M6.
The working process is concretely as follows. If the output voltage V1 of the comparator I1 is at a high level, the output of the inverter I2 is at a low level, the output of the inverter I3 is at a high level, the transmission gate I4 is turned off, the transmission gate I5 is turned on, and the low threshold voltage VB is input to the input terminal INN of the comparator I1. Meanwhile, the transistor M1, the transistor M3 are turned on, the transistor M2, the transistor M4 are turned off, the lower plate of the capacitor C1 is charged to the first reference voltage VREFP, and the capacitor C3 starts to discharge, so that the potential of the comparator input terminal INP starts to decrease. When the voltage at the input terminal INP of the comparator falls below the voltage at the input terminal INN of the comparator I1 (i.e., the low threshold voltage VB), the output voltage V1 of the comparator I1 is low. When the output voltage V1 of the comparator I1 is at a low level, the output of the inverter I2 is at a high level, the output of the inverter I3 is at a low level, the transmission gate I5 is turned off, and the transmission gate I4 is turned on, so that the high threshold voltage VA is input to the input terminal INN of the comparator I1. Meanwhile, the transistor M2, the transistor M4 are turned on, the transistor M1, the transistor M3 are turned off, the upper plate of the capacitor C2 is charged to the second reference voltage VREFN, and the capacitor C3 starts to be charged, so that the potential of the input terminal INP of the comparator I1 starts to rise. When the voltage at the input terminal INP of the comparator I1 rises higher than the voltage at the input terminal INN of the comparator I1 (i.e., the high threshold voltage VA), the output voltage V1 of the comparator I1 is at a high level. By such repeated cycles, a stable oscillation waveform can be obtained at the output terminal of the comparator.
In this patent, the oscillator frequency can be programmable by adjusting the high and low threshold voltages (VA, VB) to adjust the threshold voltage of comparator I1. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are respectively charged by the reference voltages VREFP and VREFN to regulate the overdrive voltages of M2 and M3 due to the power consumption of the circuit and gm/IdInversely, the higher the value, the lower the power consumption, so the overall power consumption of the oscillator circuit is reduced by adjusting the values of the reference voltages VREFP and VREFN, and the energy efficiency of the oscillator circuit is improved.
The energy efficiency relaxation oscillator is designed, and comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4, a capacitor C1, a capacitor C2 and a capacitor C3, and comparison is carried outThe device I1, the inverter I2, the inverter I3, the transmission gate I4 and the transmission gate I5. The programmable oscillator frequency is realized by adjusting the high and low threshold voltages (VA, VB) so as to adjust the threshold voltage of the comparator I1. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are respectively charged by the reference voltages VREFP and VREFN to regulate the overdrive voltages of the transistor M2 and the transistor M3 due to the power consumption of the circuit and gm/IdInversely, the higher the value, the lower the power consumption, so the overall power consumption of the oscillator circuit is reduced by adjusting the values of the reference voltages VREFP and VREFN, and the energy efficiency of the oscillator circuit is improved.
The foregoing shows and describes the basic principles, principal features and advantages of this patent. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to explain the principles of the invention, and that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of protection sought is to be defined by the claims appended hereto and their equivalents.

Claims (7)

1. An energy efficient relaxation oscillator, comprising:
the oscillator (1) is provided with a high threshold voltage interface VA, a low threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN and an output signal interface VO respectively;
the first reference voltage interface VREFP is connected to a source of a transistor M1, a gate of the transistor M1 is connected to a V2 interface, one way of a drain of the transistor M1 is connected to a capacitor C1, one way is connected to a source of a transistor M2, one way of a gate of the transistor M2 is connected to a V1 interface, one way is connected to a gate of the transistor M3, one way of a source of the transistor M3 is connected to a capacitor C2, one way is connected to a drain of a transistor M4, the capacitor C2 is grounded, a gate of the transistor M4 is connected to a V2 interface, a source of the transistor M4 is connected to a second reference voltage interface VREFN, after the drain of the transistor M2 and the drain of the transistor M3 are connected, one way is connected to a capacitor C3, one way is connected to an INP interface of a comparator I1, the capacitor C3 is grounded, an INN interface of the comparator I1 is connected to an OUT interface of a transmission gate I4, one way is connected to an OUT interface of a transmission gate I5, and an interface V1 of the comparator I1 is connected to an inverter 2, one path is connected with a V1 interface, the other path of the phase inverter I2 is connected with a phase inverter I3, the other path is connected with a V2 interface, and the phase inverter I3 is connected with an output signal interface VO;
an IN interface of the transmission gate I4 is connected with a high threshold voltage interface VA, a VP interface of the transmission gate I4 is connected with an output signal interface VO, a VN interface of the transmission gate I4 is connected with a V2 interface, an IN interface of the transmission gate I5 is connected with a low threshold voltage interface VB, a VN interface of the transmission gate I5 is connected with the output signal interface VO, and a VP interface of the transmission gate I5 is connected with a V2 interface.
2. The energy efficient relaxation oscillator of claim 1, wherein the transmission gate I5 and the transmission gate I4 are identical in structure and are transmission gates TG respectively.
3. The energy efficiency relaxation oscillator of claim 1, wherein a VN interface of the transmission gate TG is connected with a gate of a transistor M5, a source of the transistor M5 is connected with a source of a transistor M6 and then connected with an OUT interface, a drain of the transistor M5 is connected with a drain of a transistor M6 and then connected with an IN interface, and a gate of the transistor M6 is connected with a VP interface.
4. The energy efficient relaxation oscillator of claim 1, wherein one end of said capacitor C1 is wired.
5. The energy efficient relaxation oscillator of claim 1, wherein the comparator I1, the inverter I2, and the inverter I3 are oriented towards the output signal interface VO.
6. The energy efficient relaxation oscillator of claim 1, wherein the transistor M5 is a PMOS transistor and the transistor M6 is an NMOS transistor.
7. The energy efficient relaxation oscillator of claim 1, wherein the voltage of the first reference voltage interface VREFP and the second reference voltage interface VREFN are adjustable.
CN202120742067.8U 2021-04-13 2021-04-13 Energy efficiency relaxation oscillator Active CN215378886U (en)

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Application Number Priority Date Filing Date Title
CN202120742067.8U CN215378886U (en) 2021-04-13 2021-04-13 Energy efficiency relaxation oscillator

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CN215378886U true CN215378886U (en) 2021-12-31

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