CN215343281U

CN215343281U - Cable connector for SSD and system for testing SSD

Info

Publication number: CN215343281U
Application number: CN202121079976.4U
Authority: CN
Inventors: 武恒文
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-05-19
Filing date: 2021-05-19
Publication date: 2021-12-28
Anticipated expiration: 2031-05-19

Abstract

The application provides a cable connector for an SSD and a system for testing the SSD, wherein the cable connector comprises a data line body, a first connecting end and two second connecting ends, wherein the first connecting end and the two second connecting ends are positioned at two opposite ends of the data line body. The first connecting end is provided with a first interface, and the first interface is used for being electrically connected with the NVMe SSD. The second link is equipped with the second interface, two second interface on the second link is used for being connected with two different host computer end one-to-one electricity, wherein, two the second interface is PCIe X2 interface. The first interface is electrically connected with the two second interfaces through the data line body respectively. Because the cable connector is simple in structure, the NVMe SSD is connected to two different host terminals by the cable connector to perform testing in a dual-port mode, the cable connector is convenient to use, and the cost can be reduced.

Description

Cable connector for SSD and system for testing SSD

Technical Field

The present application relates to the field of cables, and more particularly, to a cable connector for an SSD and a system for testing the SSD.

Background

NVMe (Non-Volatile Memory standard) is a bus transfer protocol specification based on a device logic interface similar to AHCI, and is mainly used for electrical connection with a host computer through a PCIe bus (peripheral component interconnect Express).

With the development of data centers and clouds, various hybrid application scenarios make NVMe SSD (Solid State Disk) more advantageous in data centers. In the development and trial-manufacturing stage of the NVMe SSD product, when a developer performs product test verification, various Adapter test fixtures need to be selected or the m.2/U.2 cable needs to be extended to improve the test efficiency, but these tools are only suitable for testing in the single-port mode. Since the two PCIe X2 channels of the NVMe SSD share a physical interface (e.g., U.2 interface), during the dual-port mode test, the two PCIe X2 channels need to be electrically connected to different hosts, so the existing single-port adapter and cable cannot meet the test requirement of the NVMe SSD in the dual-port mode.

At present, the NVMe SSD dual port mode is only applied to enterprises or data centers with higher requirements for reliability, corresponding test tools are mainly developed and used by relevant storage manufacturers, and in order to quickly perform batch tests on products, all manufacturers basically adopt a method Of installing an HBA (Host Bus Adapter) on a Server and performing a dual port test on an NVMe SSD through a JBOF (Just a Bunch Of NVMe Flash, NVMe SSD expansion cabinet) system, but the scheme has high development cost, a long period and is not flexible enough. Therefore, it is very necessary to design a new test aid tool for NVMe SSD dual port mode.

SUMMERY OF THE UTILITY MODEL

In view of the above, a first aspect of the present application provides a cable connector for an SSD, the cable connector including a data wire body, a first connection end and two second connection ends at two opposite ends of the data wire body. The first connecting end is provided with a first interface, and the first interface is used for being electrically connected with the NVMe SSD; the second connecting ends are provided with second interfaces, and the second interfaces on the two second connecting ends are used for being electrically connected with two different host ends one by one, wherein the two second interfaces are PCIe X2 interfaces; the first interface is electrically connected with the two second interfaces through the data line body respectively.

A second aspect of the present application provides a system for testing an SSD, the system including the cable connector of the first aspect and two hosts, wherein the second interfaces on the two second connection ends of the cable connector are electrically connected to the host ends of the two hosts one by one.

When the cable connector provided by the application connects the NVMe SSD to the host end, two PCIe X2 channels of the NVMe SSD can be distributed to two PCIe X2 interfaces, and the NVMe SSD is respectively electrically connected with two different host ends through two PCIe X2 interfaces, so that the test requirement of the NVMe SSD in a dual-port mode can be met. Because the cable connector is simple in structure, the cable connector is adopted to assist the NVMe SSD in carrying out the test in the dual-port mode, the use is convenient, and the cost can be reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a cable connector for an SSD according to an embodiment of the present application.

Fig. 2 is a pin configuration table of the cable connector for the SSD in fig. 1.

Description of the main elements

Cable connector 10

First connection end 11

Second connection end 12

First interface 111

Second interfaces 121, 122

Data line body 131

The main line body 1311

The sub-wire body 1312

Power line body 15

Power supply interface 16

The following detailed description will further illustrate the present application in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a cable connector for an SSD according to an embodiment of the present disclosure.

As shown in fig. 1, the cable connector 10 includes a data wire body 131, and a first connection end 11 and two second connection ends 12 located at two opposite ends of the data wire body 131, where the first connection end 11 is provided with a first interface 111, and the first interface 111 is used for electrically connecting with an NVMe SSD. The two second connection ends 12 are respectively provided with second interfaces 121 and 122, and the second interfaces 121 and 122 are respectively used for electrically connecting with two different host terminals (not shown).

In this embodiment, the second interfaces 121 and 122 are PCIe X2 interfaces, and the first interface 111 is electrically connected to the second interfaces 121 and 122 respectively through the data line body 131. Specifically, the second interfaces 121 and 122 are PCIe X2 gold fingers, and are both configured as dual-channel PCIe interfaces.

In this embodiment, the first interface 111 is an U.2 interface. Further, the first interface 111 adopts an SFF-8639 interface.

In this embodiment, the data line body 131 includes a main line body 1311 and two sub line bodies 1312, where one end of the main line body 1311 is connected to the first connection end 11, and the other end extends out of the two sub line bodies 1312. The free ends of the two sub-line bodies 1312 are connected with the two second connection ends 12 one by one, and the first interface 111 is electrically connected with the second interfaces 121 and 122 through the main line body 1311 and the two sub-line bodies 1312.

In other embodiments, the data line body 131 may include two sub-line bodies (not shown) independent from each other, one end of each of the two sub-line bodies is connected to the first connection end 11, and the other end of each of the two sub-line bodies is connected to the two second connection ends 12 one by one. The first interface 111 is electrically connected to the second interfaces 121 and 122 through the two sub-line bodies.

Further, the data wire body 131 is an FPC flat wire wrapped by an insulator.

In this embodiment, the cable connector 10 further includes a power line body 15, one end of the power line body 15 is connected to the first connection end 11, a power interface 16 for connecting an external power source is disposed at the other end of the power line body 15, and the power interface 16 is electrically connected to the first interface 111 through the power line body 15. Preferably, the power supply wire body is a wire with the specification of 24-18 AWG.

Further, the power interface 16 is a SATA interface.

Referring to fig. 2, fig. 2 is a pin configuration table of the cable connector 10 according to an embodiment of the present disclosure.

As shown in fig. 2, the first interface 111 includes at least 2 sets of RefClk differential signal pins (RefClk0+ and RefClk0-, RefClk1+ and RefClk1-), 4 sets of transmit differential signal pins (PETp0 and PETn0, PETp1 and PETn1, PETp2 and PETn2, PETp3 and PETn3), 4 sets of receive differential signal pins (PERp0 and PERn0, PERp1 and PERn1, PERp2 and PERn2, PERp3 and PERn3), 1 SMBUS clock signal pin (SMBClk), 1 SMBDat data signal pin (SMBDat), 2 ePERst signal pins (erest 0#, erest 1 me #), and one nvssd dual port enable signal pin (dual port en).

It should be noted that, in the dual port mode of the NVMe SSD, the second interfaces 121 and 122 each require 1 set of REFCLK differential signal pins and 1 PERST signal pin. Specifically, the second interface 121 includes at least 1 set of REFCLK differential signals (REFCLK + and REFCLK-), 2 sets of transmit differential signal pins (PETp0 and PETn0, PETp1 and PETn1), 2 sets of receive differential signal pins (PERp0 and PERn0, PERp1 and PERn1), and 1 set of PERST signal pins (PERST #). The second interface 122 has 1 more SMBUS clock signal pin (SMBCLK) and 1 more SMBUS data signal pin (SMBDAT) than the second interface 121.

Specifically, as shown in fig. 2, 2 sets of RefClk differential signal pins of the first interface 111 are electrically connected to RefClk differential signal sets of the second interfaces 121 and 122 in a one-to-one correspondence manner (pins RefClk0+, RefClk 0-of the first interface 111 are electrically connected to pins RefClk +, RefClk-of the second interface 121 in a one-to-one correspondence manner, and pins RefClk1+, RefClk 1-of the first interface 111 are electrically connected to pins RefClk +, RefClk-of the second interface 122 in a one-to-one correspondence manner). The 4 sets of transmission differential signal pins of the first interface 111 are electrically connected with the sets of transmission differential signal pins of the second interfaces 121 and 122 in a one-to-one correspondence manner (pins PETp0, PETn0, PETp1 and PETn1 of the first interface 111 are electrically connected with pins PETp0, PETn0, PETp1 and PETn1 of the second interface 121 in a one-to-one correspondence manner, and pins PETp2, PETn2, PETp3 and PETn3 of the first interface 111 are electrically connected with pins PETp0, PETn0, PETp1 and PETn1 of the second interface 122 in a one-to-one correspondence manner). The 4 sets of differential signal receiving pins of the first interface 111 are electrically connected with the sets of differential signal receiving pins of the second interfaces 121 and 122 in a one-to-one correspondence manner (the pins PERp0, PERn0, PERp1 and PERn1 of the first interface 111 are electrically connected with the pins PERp0, PERn0, PERp1 and PERn1 of the second interface 121 in a one-to-one correspondence manner, and the pins PERp2, PERn2, PERp3 and PERn3 of the first interface 111 are electrically connected with the pins PERp0, PERn0, PERp1 and PERn1 of the second interface 122 in a one-to-one correspondence manner). The 2 eprest signal pins of the first interface 111 are electrically connected to the PERST signal pins of the second interfaces 121 and 122 in a one-to-one correspondence manner (the pin eprest 0# of the first interface 111 is electrically connected to the pin PERST # of the second interface 121, and the pin eprest 1# of the first interface 111 is electrically connected to the pin PERST # of the second interface 122). The 1 SMBUS clock signal pin and the 1 SMBUS data signal pin of the first interface 111 are electrically connected to the 1 SMBUS clock signal pin and the 1 SMBUS data signal pin of the second interface 122 in a one-to-one correspondence manner (the pins SMBClk and SMBDat of the first interface 111 are electrically connected to the pins SMBClk and SMBDat of the second interface 122 in a one-to-one correspondence manner). It should be noted that, in this embodiment, the NVMe SSD dual-port enable signal pin (dual port en #) of the first interface 111 is electrically connected to the ground GND through a resistor R (as shown in fig. 2), so that the NVMe dual-port SSD enable signal of the NVMe SSD electrically connected to the first interface 111 is set to a low level, and the NVMe SSD can operate in the dual-port mode, and thus, when the dual-port mode test of the NVMe SSD is performed, the host does not need to send the NVMe dual-port SSD enable signal.

When the cable connector provided by the embodiment of the application connects the NVMe SSD to the host end, two PCIe X2 channels of the NVMe SSD can be distributed to two PCIe X2 interfaces, and the NVMe SSD is respectively and electrically connected with two different host ends through the two PCIe X2 interfaces, so that the test requirement of the NVMe SSD in a dual-port mode can be met. Because the cable connector is simple in structure, the cable connector is adopted to assist the NVMe SSD in carrying out the test in the dual-port mode, the use is convenient, and the cost can be reduced.

The present application further provides a system for testing an SSD, the system includes the cable connector 10 and two hosts, wherein the second interfaces 121 and 122 on the two second connection ends 12 of the cable connector 10 are electrically connected to the host ends of the two hosts one by one, and the system is used for testing the NVMe SSD in the dual port mode.

The foregoing is an implementation of the embodiments of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiments of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.

Claims

1. A cable connector for an SSD comprises a data line body, a first connecting end and two second connecting ends, wherein the first connecting end and the two second connecting ends are positioned at two opposite ends of the data line body; the second connecting ends are provided with second interfaces, and the second interfaces on the two second connecting ends are used for being electrically connected with two different host ends one by one, wherein the two second interfaces are PCIe X2 interfaces; the first interface is electrically connected with the two second interfaces through the data line body respectively.

2. The cable connector for an SSD of claim 1, wherein the first interface is an U.2 interface.

3. The cable connector for SSDs of claim 2, wherein the first interface and one of the second interfaces are each provided with an SMBUS clock signal pin, an SMBUS data signal pin.

4. The cable connector for the SSD according to claim 3, wherein the first interface is further provided with an NVMe SSD dual port enable signal pin, the NVMe SSD dual port enable signal pin being electrically connected to ground GND through a resistor, such that the NVMe SSD electrically connected to the first interface operates in a dual port mode.

5. The cable connector for an SSD of claim 4, wherein both of the second interfaces comprise a RefCLK signal pin and a PERST signal pin.

6. The cable connector for an SSD of claim 1, wherein the data wire body comprises a main wire body and two sub-wire bodies, the main wire body having one end connected with the first connection end and the other end extending out of the two sub-wire bodies; the free ends of the two sub-line bodies are connected with the two second connecting ends one by one, and the first interfaces are electrically connected with the two second interfaces through the main line body and the two sub-line bodies respectively.

7. The cable connector for the SSD according to claim 1, wherein the data wire body comprises two separate wire sub-bodies, one end of each of the two wire sub-bodies is connected to the first connecting end, and the other end of each of the two wire sub-bodies is connected to the two second connecting ends one by one; the first interface is electrically connected with the two second interfaces through the two sub-line bodies respectively.

8. The cable connector for the SSD according to claim 6 or 7, further comprising a power line body, wherein one end of the power line body is connected to the first connecting end, and the other end of the power line body is provided with a power interface for connecting an external power source, and the power interface is electrically connected to the first interface through the power line body.

9. The cable connector for an SSD of claim 8, wherein the power interface is a SATA interface.

10. A system for testing an SSD, comprising:

the cable connector of any one of claims 1 to 9; and

and the second interfaces on the two second connecting ends of the cable connector are electrically connected with the host ends of the two hosts one by one.