CN215300210U

CN215300210U - Negative terminal protection MCU and P negative common-ground BMS system

Info

Publication number: CN215300210U
Application number: CN202121237437.9U
Authority: CN
Inventors: 吴智声; 杨庆宏; 邓通杭
Original assignee: Fujian Scud Power Technology Co Ltd
Current assignee: Fujian Scud Power Technology Co Ltd
Priority date: 2021-06-03
Filing date: 2021-06-03
Publication date: 2021-12-24
Anticipated expiration: 2031-06-03

Abstract

The utility model discloses a negative terminal protection MCU and P burden BMS system altogether, including electric core module, AFE battery sampling chip U3, DCDC chip U2, keep apart chip U1, the undervoltage turn-off circuit of degree of depth, sampling circuit, singlechip MCU, electric capacity C103, load RL4, FUSE FUSE4, external charger, zener diode ZD36, diode D34, diode D1, diode D2, switch SW1, switch SW3, the utility model discloses measure P + P-external voltage very simple, and can the accurate measurement to P + P-external voltage to safe opening is charged; the utility model discloses if used the activation that charges, the singlechip itself can not be the low-power consumption, falls the electricity totally moreover and also can awaken up electric core.

Description

Negative terminal protection MCU and P negative common-ground BMS system

Technical Field

The utility model relates to a negative terminal protection MCU and P burden BMS system on ground altogether.

Background

With the progress and development of society, the intellectualization in the aspects of storage, family, trip and the like, the diversification of mobile consumer electronic products, and the adoption of batteries as clean energy providers, the batteries are more and more popular and favored by consumers and become an indispensable part of electronic products. In the application process, the battery is taken as an output end of energy, whether the performance of the battery core meets the use condition or not is considered through test items such as charging, discharging, high-temperature group storage, low-temperature group storage testing and the like under certain conditions, the safety and the operation coefficient in the application are improved, the battery is helped to reduce the failure rate in the use process in the long-term use process, more secure service is provided for a user in the use process, the user acceptance is improved, and the method becomes a significant research subject.

The conventional battery cell negative terminal scheme is as shown in fig. 1, and adopts the common ground of the MCU, the AFE and the DCDC, but because the negative terminal protection disconnects the B-and the P-voltages, when the external voltages of the external P + and the P-need to be judged, because the common ground does not cause the sampling difficulty, for example, it is very troublesome to judge whether the external voltage is available or not, and the conventional battery cell negative terminal scheme does not have the deep under-voltage protection function.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming not enough among the prior art, providing a negative terminal protection MCU and P burden BMS system altogether.

In order to achieve the purpose, the utility model is realized by the following technical scheme:

a negative end protection MCU and P negative common ground BMS system comprises a cell module, an AFE battery sampling chip U3, a DCDC chip U2, an isolation chip U1, a deep undervoltage shutdown circuit, a sampling circuit, a single chip microcomputer MCU, a capacitor C103, a load RL4, a FUSE FUSE4, an external charger, a zener diode ZD36, a diode D34, a diode D1, a diode D2, a switch SW1 and a switch SW3, wherein the external charger is provided with a positive electrode P + and a negative electrode P-, the cell module is provided with a positive electrode B + and a negative electrode B-, the cell module and the isolation chip U1 are both connected with an AFE battery sampling chip U3, the positive electrode B +, a negative electrode B-and a ground signal GND of a diode D1 are both connected with the deep undervoltage shutdown circuit, the isolation chip U1 is connected with the single chip microcomputer MCU, a GND end and a GND end of the DCDC chip U2 is connected with the ground signal MCU, a OUT end of the single chip MCU 2 is connected with the ground signal, the VIN end of the DCDC chip U2 is connected with an anode B +, one end of the FUSE FUSE4 is connected with B +, the other end of the FUSE FUSE4 is connected with an anode P +, the cathode of the diode D1 is connected with a cathode P-through a diode D2, the switch SW1 is connected with a diode D1 in parallel, the switch SW3 is connected with a diode D2 in parallel, the ADC end of the single-chip microcomputer MCU is connected with the cathode of the voltage stabilizing diode ZD36, the anode of the voltage stabilizing diode ZD36 is connected with a ground signal GND, the anode of the diode D34 is connected with the ground signal GND, the cathode of the diode D34 is connected with the cathode P-, the anode P +, the cathode P-, and the ADC end of the single-chip microcomputer are connected with a sampling circuit, one end of the capacitor C103 is connected with the anode P +, the other end of the capacitor C103 is connected with the cathode P-, and the load RL4 is connected with the capacitor C103 in parallel.

Preferably, the deep undervoltage shutdown circuit comprises a switch SW5, a resistor R210 and a transistor Q96, wherein one end of the switch SW5 is connected with a positive electrode B +, the other end of the switch SW5 is connected with a base electrode of a transistor Q96 through the resistor R210, an emitter electrode of the transistor Q96 is connected with a negative electrode B-, an emitter electrode of the transistor Q96 is further connected with a positive electrode of a diode D1, and a collector electrode of the transistor Q96 is connected with a ground signal GND.

Preferably, the transistor Q96 is an NPN transistor.

Preferably, the sampling circuit comprises a resistor R208 and a resistor R209, one end of the resistor R208 is connected with the positive pole P +, the other end of the resistor R208 is connected with the ADC end of the MCU, and the other end of the resistor R208 is also connected with the negative pole P-through the resistor R209.

Preferably, the cell module is formed by connecting a plurality of cells T in series.

The utility model has the advantages as follows: the utility model has the advantages that the measurement of the P + P-external voltage is very simple, and the P + P-external voltage can be accurately measured, thereby safely starting charging; the utility model discloses if used the activation that charges, the singlechip itself can not be the low-power consumption, falls the electricity totally moreover and also can awaken up electric core.

Drawings

FIG. 1 is a schematic diagram of a circuit in the background art;

fig. 2 is a schematic circuit diagram of the present invention.

Detailed Description

The technical scheme of the utility model is further explained by combining the attached drawings of the specification:

as shown in fig. 2, a negative terminal protection MCU and P negative common ground BMS system includes a cell module 3, an AFE battery sampling chip U3, a DCDC chip U2, an isolation chip U1, a deep undervoltage shutdown circuit 1, a sampling circuit 2, a single-chip MCU, a capacitor C103, a load RL4, a FUSE4, an external charger 4, a zener diode ZD36, a diode D34, a diode D1, a diode D2, a switch SW1, and a switch SW3, wherein the external charger 4 is provided with a positive electrode P + and a negative electrode P-, the cell module 3 is provided with a positive electrode B + and a negative electrode B-, the cell module 3 and the isolation chip U1 are all connected to the AFE battery sampling chip U3, the positive electrode B +, a negative electrode B-, a ground signal GND of the diode D1 are all connected to the deep undervoltage shutdown circuit 1, the isolation chip U1 is connected to the MCU, the DCDC chip U2 and the single-chip GND are all connected to ground signals GND, the OUT end of the DCDC chip U2 is connected with the MCU, the VIN end of the DCDC chip U2 is connected with the anode B +, one end of the FUSE FUSE4 is connected with B +, the other end of the FUSE FUSE4 is connected with the anode P +, the cathode of the diode D1 is connected to the cathode P-through a diode D2, the switch SW1 is connected in parallel with the diode D1, the switch SW3 is connected in parallel with a diode D2, the ADC end of the single chip microcomputer MCU is connected with the cathode of a voltage stabilizing diode ZD36, the anode of the zener diode ZD36 is connected to the ground signal GND, the anode of the diode D34 is connected to the ground signal GND, the cathode of the diode D34 is connected with the cathode P-, the anode P +, the cathode P-, the ADC end of the single chip MCU are connected with the sampling circuit 2, one end of the capacitor C103 is connected with the positive electrode P +, the other end of the capacitor C103 is connected with the negative electrode P-, and the load RL4 is connected with the capacitor C103 in parallel.

As shown in fig. 2, the deep undervoltage shutdown circuit 1 includes a switch SW5, a resistor R210, and a transistor Q96, wherein one end of the switch SW5 is connected to the positive electrode B +, the other end of the switch SW5 is connected to the base of the transistor Q96 through the resistor R210, the emitter of the transistor Q96 is connected to the negative electrode B-, the emitter of the transistor Q96 is further connected to the positive electrode of a diode D1, and the collector of the transistor Q96 is connected to the ground signal GND.

As shown in fig. 2, the triode Q96 is an NPN triode, the sampling circuit 2 includes a resistor R208 and a resistor R209, one end of the resistor R208 is connected to the positive electrode P +, the other end of the resistor R208 is connected to the ADC end of the MCU, the other end of the resistor R208 is also connected to the negative electrode P-through the resistor R209, and the electric core module 3 is formed by connecting a plurality of electric cores T in series.

The technical characteristics are as follows: 1. and the isolation chip U1 forms a signal isolation circuit. 2. The transistor Q96 forms a reverse diode which can be turned off, the transistor Q96 and the switch SW5 form a deep undervoltage turn-off circuit, and the SW5 is a normally closed circuit. 3. The diode D34 or the triode Q96 forms a power supply loop of hardware, and power is supplied to the DCDC chip by B + B-or P + P-, so that the MCU is supplied with power. 4. The resistor R208 and the resistor R209 form a voltage division circuit for sampling the voltage difference of P + P & lt- & gt by the MCU.

The working principle is as follows: the switch SW5 is normally closed, as shown in fig. 2, when power is first turned on, the switch SW3 is closed, the switch SW1 is open, no load RL4 exists outside, the DCDC chip is powered by B + B-, the ground of the MCU is not directly connected with B-and P-, and the semiconductor device transistor Q96 and the zener diode D34 are reversely connected. 2: the AFE battery sampling chip U3 adopts the battery cell module to directly supply power, the AFE battery sampling chip U3 and the MCU communication are isolated through the isolation chip U1, particularly, 20 or 30 or 40 battery cells need an isolation communication scheme, the scheme is only two battery cells, as the number of the battery cells is increased, the voltage B + of the battery cells is higher and higher, the capacity is higher and higher, and the judgment of external voltage is necessary for increasing the safety and reliability. 3: when an external power supply P + P-is connected, particularly when the external voltage P + is higher than the cell voltage B +, the switch SW3 is disconnected, the switch SW1 is closed, the diode D34 is connected, the system is powered by the external P + P-, and the P + P-voltage is reversely deduced through the voltage division of the sampling resistors R208 and R209, namely the sum of the voltages of the sampling resistors R208 and R209 is the voltage between the P + and the P-. 4: when the external voltages P + and P-are in the range of legal chargers, the system controls to open the charging tube. 5: when load RL4 is connected externally, no current is generated due to the reverse connection of diode D34, i.e., no current leaks from P-to GND to B-.

The model of the AFE battery sampling chip U3 is bq76920, the model of the DCDC chip U2 is lm5009, and the model of the isolation chip U1 is iso 1541.

As shown in fig. 1, there are two battery cells, and the full charge voltage of a single battery cell is 2.5-4.2V, when both battery cells are fully charged, B + is 5-8.4V, and the external charger P + is 5-8.4V, in an actual situation, the size of the external charger P + is determined according to the number n of the battery cells, that is, n times the full charge voltage of the battery cells.

The utility model has the advantages that the measurement of the P + P-external voltage is very simple, and the P + P-external voltage can be accurately measured, thereby safely starting charging; the utility model discloses if used the activation that charges, the singlechip itself can not be the low-power consumption, falls the electricity totally moreover and also can awaken up electric core.

It should be noted that the above list is only one specific embodiment of the present invention. Obviously, the present invention is not limited to the above embodiments, and many modifications can be made, and in short, all modifications that can be directly derived or suggested by the person skilled in the art from the disclosure of the present invention should be considered as the protection scope of the present invention.

Claims

1. The negative end protection MCU and P negative common ground BMS system is characterized by comprising a cell module (3), an AFE battery sampling chip U3, a DCDC chip U2, an isolation chip U1, a deep undervoltage shutdown circuit (1), a sampling circuit (2), a single chip microcomputer MCU, a capacitor C103, a load RL4, a FUSE FUSE4, an external charger (4), a voltage stabilizing diode ZD36, a diode D34, a diode D1, a diode D2, a switch SW1 and a switch SW3, wherein the external charger (4) is provided with a positive electrode P + and a negative electrode P-, the cell module (3) is provided with a positive electrode B + and a negative electrode B-, the cell module (3) and the isolation chip U1 are connected with the AFE battery sampling chip U3, positive electrodes GND, negative electrodes B-, ground signals of the positive electrode B +, the diode D1 are connected with the deep undervoltage shutdown circuit (1), and the isolation chip U1 is connected with the MCU, the GND end of the DCDC chip U2 and the MCU are both connected with a ground signal GND, the OUT end of the DCDC chip U2 is connected with the MCU, the VIN end of the DCDC chip U2 is connected with an anode B +, one end of the FUSE FUSE4 is connected with B +, the other end of the FUSE FUSE4 is connected with an anode P +, the cathode of the diode D1 is connected with a cathode P-through a diode D2, the switch SW1 is connected with a diode D1 in parallel, the switch SW3 is connected with a diode D2 in parallel, the ADC end of the MCU is connected with the cathode of a zener diode ZD36, the anode of the ZD diode 36 is connected with the ground signal GND, the anode of the diode D34 is connected with the ground signal GND, the cathode of the diode D34 is connected with the cathode P-, the anode P +, the cathode P-, and the ADC end of the MCU are both connected with a sampling circuit (2), one end of the capacitor C103 is connected with an anode P +, the other end of the capacitor C103 is connected with the negative pole P-, and the load RL4 is connected with the capacitor C103 in parallel.

2. The negative side protection MCU and P negative common ground BMS system according to claim 1, wherein said deep undervoltage shutdown circuit (1) comprises a switch SW5, a resistor R210, and a transistor Q96, wherein one end of said switch SW5 is connected to positive pole B +, the other end of said switch SW5 is connected to base of a transistor Q96 through a resistor R210, emitter of said transistor Q96 is connected to negative pole B-, emitter of said transistor Q96 is further connected to positive pole of a diode D1, and collector of said transistor Q96 is connected to ground signal GND.

3. The negative side protection MCU of claim 2, wherein the transistor Q96 is an NPN transistor.

4. The negative terminal protection MCU and P negative common ground BMS system according to claim 1, wherein the sampling circuit (2) comprises a resistor R208 and a resistor R209, one end of the resistor R208 is connected with the positive pole P +, the other end of the resistor R208 is connected with the ADC terminal of the MCU, and the other end of the resistor R208 is also connected with the negative pole P-through the resistor R209.

5. The negative terminal protection MCU and PBG common-ground BMS system according to claim 1, wherein the cell module (3) is formed by connecting a plurality of cells T in series.