CN215120093U - Equipment abnormity protection circuit and electronic equipment - Google Patents

Abstract

The utility model relates to an equipment abnormity protection circuit and electronic equipment, include: the power supply unit is connected with the equipment working power supply circuit and the switch unit of the equipment working circuit; a first level generating unit connected to the device start circuit and outputting a first level when the device start circuit is started; a WDI signal generation unit that periodically outputs a WDI signal when the device program is normal; a second level generating unit connected to the WDI signal generating unit and outputting a second level when the WDI signal is normal; a third level generating unit outputting a third level when the state configuration of the device is normal; the logic judgment unit is connected with the first, second and third level generation units, and outputs a fourth level when receiving the first, second and third levels at the same time, otherwise outputs a fifth level; the switch unit is connected with the logic judgment unit, is switched on when receiving the fourth level and is switched off when receiving the fifth level. Implement the utility model discloses can cut off heavy current input, improve equipment reliability when appearing unusually.

Description

Equipment abnormity protection circuit and electronic equipment

Technical Field

The utility model relates to an electronic circuit technical field, more specifically say, relate to an equipment abnormity protection circuit and electronic equipment.

Background

In the current electronic equipment such as cleaning equipment or electronic circuit products such as a floor washing machine, a manual trigger switch is usually adopted to restart the whole circuit in the processing process of abnormal operation of an internal program, and watchdog reset software is adopted in some products to electrify the whole circuit again, so that the process generates large current impact on the inside of the electronic equipment or products, and secondary damage is easy to occur.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in, to prior art's above-mentioned partial technical defect, provide an equipment abnormity protection circuit and electronic equipment.

The utility model provides a technical scheme that its technical problem adopted is: constructing an apparatus abnormality protection circuit comprising: a power supply unit, and

the switching unit is used for connecting the equipment working power supply circuit and the equipment working circuit;

a first level generation unit for connecting a device start-up circuit and configured to output a first level when the device start-up circuit is triggered to start up and to turn off the first level when the device start-up circuit is turned off;

a WDI signal generation unit configured to periodically output a WDI signal when a program of the device is operating normally;

the second level generating unit is connected with the WDI signal generating unit and used for receiving the WDI signal to output a second level and turning off the second level when the turn-off duration of the WDI signal exceeds the preset time;

a third level generation unit configured to output a third level when the state configuration of the device is operating normally, and to turn off the third level when the state configuration of the device is abnormal;

a logic judgment unit connected to the first level generation unit, the second level generation unit, and the third level generation unit, wherein the logic judgment unit is configured to output a fourth level when the first level, the second level, and the third level are received at the same time, and otherwise output a fifth level;

the switch unit is further connected with the logic judgment unit and is configured to be switched on when receiving the fourth level and switched off when receiving the fifth level.

Preferably, the second level generating unit includes: WDI chip U9 and D flip-flop U1;

a first pin of the WDI chip U9 is connected with a third pin of the D flip-flop U1, a second pin of the WDI chip U9 is grounded, a fourth pin of the WDI chip U9 is connected with the WDI signal generation unit, a fifth pin of the WDI chip U9 is connected with the power supply unit, a first pin of the D flip-flop U1 is connected with the WDI signal generation unit and the power supply unit, and a second pin and a fourth pin of the D flip-flop U1 are respectively connected with the power supply unit; and a sixth pin of the D trigger U1 is connected with the logic judgment unit.

Preferably, the logic judgment unit includes a first and gate circuit and a second and gate circuit;

the first input end of the first AND gate circuit is connected with the second level generation unit, the second input end of the first AND gate circuit is connected with the third level generation unit, the output end of the first AND gate circuit is connected with the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected with the first level generation unit, and the output end of the second AND gate circuit is connected with the switch unit.

Preferably, the first and second and gate circuits are integrated into a two-way and gate chip U10.

Preferably, the first level generating unit includes a first switching tube Q1, a first resistor R36, and a second resistor R37;

the first end of the first switch tube Q1 is used for receiving a starting signal of the equipment starting circuit, the first end of the first switch tube Q1 is further connected with the first end of the first resistor R36, the second end of the first resistor R36 is grounded, the second end of the first switch tube Q1 is connected with the power supply unit, the third end of the first switch tube Q1 is connected with the second input end of the second and gate circuit and the first end of the second resistor R37, and the second end of the second resistor R37 is grounded.

Preferably, the first level generating unit further comprises a TVS transistor TVS1, a cathode of the TVS transistor TVS1 is connected to the third terminal of the first switching transistor Q1, and an anode of the TVS transistor TVS1 is grounded; and/or

The first switch tube Q1 includes a first MOS transistor, a gate of the first MOS transistor is connected to the device start circuit, a source of the first MOS transistor is connected to the second input terminal of the second and circuit and the first end of the second resistor R37, and a drain of the first MOS transistor is connected to the power supply unit.

Preferably, the switching unit includes a first sub-switching unit, a second sub-switching unit, and a third sub-switching unit;

the first end of the first sub-switch unit is connected with the output end of the logic judgment unit, the second end of the first sub-switch unit is connected with the first end of the second sub-switch unit, the third end of the first sub-switch unit is grounded, the second end of the second sub-switch unit is connected with the power supply unit, the third end of the second sub-switch unit is connected with the first end of the third sub-switch unit, the second end of the third sub-switch unit is grounded, the third end of the third sub-switch unit is connected with the equipment working power supply circuit, and the fourth end of the third sub-switch unit is connected with the equipment working circuit.

Preferably, the first sub-switching unit includes a second switching tube Q12, a third resistor R60 and a fourth resistor R62;

the first end of the second switch tube Q12 is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, the second end of the third resistor R60 is connected to the output end of the logic judgment unit, the second end of the fourth resistor R62 is grounded, the second end of the second switch tube Q12 is connected to the first end of the second sub-switch unit, and the third end of the second switch tube Q12 is grounded.

Preferably, the second switch Q12 includes a transistor, a base set of the transistor is connected to the first terminal of the third resistor R60 and the first terminal of the fourth resistor R62, an emitter of the transistor is grounded, and a collector of the transistor is connected to the first terminal of the second sub-switch unit.

Preferably, the second sub-switching unit includes a third switching tube Q13, a fifth resistor R164, and a sixth resistor R65;

a first terminal of the third switching tube Q13 is connected to the first terminal of the fifth resistor R164 and the first terminal of the sixth resistor R65, a second terminal of the fifth resistor R164 is connected to the second terminal of the first sub-switching unit, a second terminal of the third switching tube Q13 is connected to the second terminal of the sixth resistor R65 and the power supply unit, and a third terminal of the third switching tube Q13 is connected to the first terminal of the third sub-switching unit.

Preferably, the third switching transistor Q13 includes a second MOS transistor, a gate of the second MOS transistor is connected to the first terminal of the fifth resistor R164 and the first terminal of the sixth resistor R65, a drain of the second MOS transistor is connected to the first terminal of the third sub-switching unit, and a source of the second MOS transistor is connected to the second terminal of the sixth resistor R65 and the power supply unit.

Preferably, the third sub-switching unit includes a contactor switch and a current sink circuit;

the first end of the coil of the contactor switch is connected with the third end of the second sub-switch unit and the first end of the current absorption circuit, the second end of the coil of the contactor switch is connected with the second end of the current absorption circuit and the ground, the first connecting end of the contact of the contactor switch is connected with the equipment working power supply circuit, and the second connecting end of the contact of the contactor switch is connected with the equipment working circuit.

Preferably, the first and second electrodes are formed of a metal,

the current absorption circuit comprises a diode VD9, wherein the cathode of the diode VD9 is connected with the first end of the coil of the contactor switch, and the anode of the diode VD9 is connected with the second end of the coil of the contactor switch.

Preferably, the WDI signal generating unit and the third level generating unit are integrated in a controller chip.

The present invention also provides an electronic device including the device abnormality protection circuit according to any one of the above embodiments.

Implement the utility model discloses an equipment abnormity protection circuit and electronic equipment has following beneficial effect: the high-current input can be cut off when abnormality occurs, and the reliability of the equipment is improved.

Drawings

The invention will be further explained with reference to the drawings and examples, wherein:

fig. 1 is a logic block diagram of an embodiment of an equipment anomaly protection circuit according to the present invention;

fig. 2 is a schematic circuit diagram of a first embodiment of an equipment abnormality protection circuit according to the present invention;

fig. 3 is a schematic circuit diagram of a first embodiment of an equipment abnormality protection circuit according to the present invention;

fig. 4 is a schematic circuit diagram of a first embodiment of the device abnormality protection circuit of the present invention.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, in a first embodiment of the device abnormality protection circuit 100 of the present invention, the device abnormality protection circuit includes: a power supply unit 110, and a switching unit 120 for connecting the device operation power supply circuit 210 and the device operation circuit 220, wherein the device operation power supply circuit 210 supplies power to the device operation circuit 220 when the switching unit 120 is turned on, and turns off the power supply when the switching unit 120 is turned off; a first level generation unit 140 for connecting the device start-up circuit 230 and configured to output a first level when the device start-up circuit 230 is triggered to start up and to turn off the first level when the device start-up circuit 230 is turned off; a WDI signal generation unit 150 configured to periodically output a WDI signal when a program of the apparatus operates normally; a second level generating unit 160 connected to the WDI signal generating unit 150, for receiving the WDI signal to output a second level, and turning off the second level when a turn-off duration of the WDI signal exceeds a preset time; a third level generation unit 170 configured to output a third level when the state configuration of the device is operating normally, and to turn off the third level when the state configuration of the device is abnormal; a logic judgment unit 180 connected to the first level generation unit 140, the second level generation unit 160, and the third level generation unit 170, and configured to output a fourth level when the first level, the second level, and the third level are received at the same time, and otherwise output a fifth level; the switching unit 120 is further connected to the logic judgment unit 180 and configured to be turned on when receiving the fourth level and turned off when receiving the fifth level. Specifically, the power supply unit 110 is used for supplying power to the inside of the protection circuit. The device operation power supply circuit 210 is used for supplying power to the operation circuit of the device, and the device operation circuit 220 is referred to as a control circuit inside the device, which generally refers to a high-current operation circuit of the device, and is mainly used for completing specific tasks that the device needs to perform, and its control circuit can be understood as controlling the device operation circuit to perform its corresponding specific task. The device operation power supply circuit 210 may be understood as a large-current power supply circuit, the switch unit 120 connects the device operation power supply circuit 210 and the device operation circuit 220, when the switch unit 120 is turned on, the device operation power supply circuit 210 supplies power to the device operation circuit 220, and the device may perform an operation. When the switching unit 120 is turned off, the device operation power supply circuit 210 turns off the power supply to the device operation circuit 220, at which time the device operation circuit 220 stops the operation. The device start circuit 230 is used for powering on the device, wherein the device operation power supply circuit 210 may be connected to a power input through the device start circuit 230, and when the device start circuit 230 is triggered, the power input is connected to the device operation power supply circuit 210 through the device start circuit 230 to power on the device. The first level generation unit 140 is connected to the device start-up circuit 230, outputs the first level when the device start-up circuit 230 is normally triggered to turn on, and turns off the output of the first level when the device start-up circuit 230 abnormally operates, that is, when it is turned off. The WDI signal generating unit 150 is used to monitor the program operation state of the device, which periodically outputs the WDI signal when the program operation of the device is to be performed, and the second level generating unit 160 outputs the second level when the WDI signal is normally periodically output. When the program of the device runs abnormally, the WDI signal generation unit 150 turns off the WDI signal output, at this time, the periodic WDI signal is turned off for a long time, and the second level generation unit 160 turns off the output of the second level when the WDI signal is turned off for too long time, that is, when the WDI signal exceeds the preset time. WDI signal anomalies typically occur in the event of an internal program running away. When the monitoring device operates by the third level generating unit 170, it performs an operation corresponding to a state configuration of the operation, and when the state configuration is normal, it outputs the third level, and when the state configuration is abnormal, it controls to turn off the output of the third level. The state configuration is obtained by reading out the state configuration sent by the control module in the operation control of the running equipment. The logic judgment unit 180 is connected to the first level generation unit 140, the second level generation unit 160, and the third level generation unit 170, makes a judgment according to the input of the first level, the second level, and the third level, and outputs the fourth level when the first level, the second level, and the third level are all normal, otherwise outputs the fifth level, that is, as long as one of the first level, the second level, and the third level is not output normally, the logic judgment unit 180 outputs the fifth level. The switching unit 120 is connected to the logic determination unit 180, and is turned off or turned on according to an output of the logic determination unit 180. When the logic determining unit 180 outputs the fourth level, the switching unit 120 is turned on, that is, when the device start state, the device operating state, and the device program operating state in the device are all normal, the device operating circuit 220 thereof may be powered by the device operating power supply circuit 210 to maintain a normal operating state, and when the logic determining unit 180 outputs the fifth level, the switching unit 120 is turned off, that is, when any one or more of the device start state, the device operating state, and the device program operating state in the device is abnormal, the power supply of the device operating circuit 220 is turned off, and the device operating circuit 220 stops operating.

Optionally, as shown in fig. 4, the second level generating unit 160 includes: WDI chip U9 and D flip-flop U1; a first pin of a WDI chip U9 is connected with a third pin of a D flip-flop U1, a second pin of a WDI chip U9 is grounded, a fourth pin of the WDI chip U9 is connected with a WDI signal generating unit 150, a fifth pin of the WDI chip U9 is connected with a power supply unit 110, a first pin of a D flip-flop U1 is connected with the WDI signal generating unit 150 and the power supply unit 110, and a second pin and a fourth pin of a D flip-flop U1 are respectively connected with the power supply unit 110; the sixth pin of the D flip-flop U1 is connected to the logic determination unit 180. Specifically, in the second level generating unit 160, the fourth pin of the WDI chip U9 is used to receive the WDI signal generated by the WDI signal generating unit 150, the first pin of the WDI chip U9 is connected to the D flip-flop U1, and the WDI chip U9 outputs a corresponding trigger signal according to the WDI signal input from the WDI signal generating unit 150 to trigger the D flip-flop U1 to operate. Specifically, when there is no periodic WDI signal input to the WDI chip U9, its internal will go back to high level again 200ms after a low level RESET signal is generated by RESET, and the third pin of the D flip-flop U1 keeps outputting low level at its sixth pin after receiving the rising edge, i.e., turns off the second level output. The first pin of the D flip-flop U1 is connected to the WDI signal generating unit 150, and when the WDI signal generating unit 150 is powered on, the WDI signal generating unit 150 sends a low level signal, and the output of the D flip-flop U1 is cleared by the low level signal, so as to prevent the D flip-flop U1 from being triggered and locked by the initial state of the WDI chip U1 during the power-on process. The second pin, i.e., the 1D pin, the third pin, i.e., the 1 CLK/pin, and the fourth pin, i.e., the 1 PRE/pin of the D flip-flop U1 may be supplied with a pull-up voltage by the power supply unit 110. In one embodiment, the WDI chip U9 is implemented with the TPS3828-33 and the D flip-flop U1 is implemented with the SN74HC74 DR.

Optionally, the logic determining unit 180 includes a first and gate circuit and a second and gate circuit; the first input end of the first and-gate circuit is connected to the second level generating unit 160, the second input end of the first and-gate circuit is connected to the third level generating unit 170, the output end of the first and-gate circuit is connected to the first input end of the second and-gate circuit, the second input end of the second and-gate circuit is connected to the first level generating unit 140, and the output end of the second and-gate circuit is connected to the switching unit 120. Specifically, in the logic determining unit 180, the input end of the first and circuit receives the second level and the third level, outputs a corresponding determination level according to the output or turn-off of the second level and the third level, and simultaneously receives the determination level and the first level through the input end of the second and circuit, and outputs a final determination result according to the determination level and the first level.

Alternatively, as shown in fig. 3, the first and gate circuit and the second and gate circuit are integrated into a two-channel and gate chip U10. Specifically, the first level generating unit 140, the second level generating unit 160, and the third level generating unit 170 are respectively connected through a two-way two-input and gate chip U10 to finally output the determination results based on the first level, the second level, and the third level. The first level generating unit 140 is connected to the sixth pin of the two-way two-input chip U10, the second level generating unit 160 is connected to the first pin of the two-way two-input chip U10, the third level generating unit 170 is connected to the second pin of the two-way two-input chip U10, the seventh pin of the two-way two-input chip U10 is connected to the fifth pin of the two-way two-input chip U10, and the third pin of the two-way two-input chip U10 is connected to the switching unit 120. In one embodiment, the two-way dual-input and gate chip U10 is 74HC2G08 DP.

Optionally, the first level generating unit 140 includes a first switch Q1, a first resistor R36, and a second resistor R37; the first end of the first switch tube Q1 is used for receiving a start signal of the device start circuit 230, the first end of the first switch tube Q1 is further connected to the first end of a first resistor R36, the second end of the first resistor R36 is grounded, the second end of the first switch tube Q1 is connected to the power supply unit 110, the third end of the first switch tube Q1 is connected to the second input end of the second and circuit and the first end of the second resistor R37, and the second end of the second resistor R37 is grounded. Specifically, in the first level generating circuit, a first end of the first switch Q1 is connected to the device start circuit 230, a start signal of the device start circuit 230 generates a driving level at a first end of the first switch Q1 through the first resistor R36, the driving level drives the first switch Q1 to be turned on, and after the first switch Q1 is turned on, the power supply unit 110 forms a voltage, i.e., a first level, at a first end of the second resistor R37 through the turned on first switch Q1. The first level is input to an input end of the second AND circuit.

Optionally, the first level generating unit 140 further includes a TVS transistor TVS1, a cathode of the TVS transistor TVS1 is connected to the third terminal of the first switching transistor Q1, and an anode of the TVS transistor TVS1 is grounded; specifically, since the first level generating unit 140 receives the start signal, which may be from a manual trigger signal, it prevents the first level generating unit 140 from generating the first level with electrostatic interference through the TVS transistor TVS 1.

Optionally, the first switch Q1 includes a first MOS transistor, a gate of the first MOS transistor is connected to the device start circuit 230, a source of the first MOS transistor is connected to the second input terminal of the second and circuit and the first end of the second resistor R37, and a drain of the first MOS transistor is connected to the power supply unit 110. The first switching transistor Q1 may be a MOS transistor, and its specific type may be NCE6003, and a gate of the MOS transistor is connected to the device start-up circuit 230 to be driven to turn on by a start signal of the device start-up circuit 230.

Alternatively, as shown in fig. 2, the switching unit 120 includes a first sub-switching unit 121, a second sub-switching unit 122, and a third sub-switching unit 123; the first end of the first sub-switch unit 121 is connected to the output end of the logic determining unit 180, the second end of the first sub-switch unit 121 is connected to the first end of the second sub-switch unit 122, the third end of the first sub-switch unit 121 is grounded, the second end of the second sub-switch unit 122 is connected to the power supply unit 110, the third end of the second sub-switch unit 122 is connected to the first end of the third sub-switch unit 123, the second end of the third sub-switch unit 123 is grounded, the third end of the third sub-switch unit 123 is connected to the device working power supply circuit 210, and the fourth end of the third sub-switch unit 123 is connected to the device working circuit 220. Specifically, in the switch unit 120, the device operation power supply circuit 210 and the device operation circuit 220 are controlled to be conducted through the three-stage sub-switch unit 120. The first sub-switch unit 121 is connected to the logic determination unit 180, and is turned on when receiving the fourth level output by the logic determination unit 180, the second sub-switch unit 122 is connected to the first sub-switch unit 121, and when the first sub-switch unit 121 is turned on, the second sub-switch unit 122 is turned on, at this time, the power supply unit 110 powers on the third sub-switch unit 123 through the second sub-switch unit 122, after the third sub-switch unit 123 is powered on, the third sub-switch unit 123 is turned on after being powered on, and the device operation power supply circuit 210 supplies power to the following device operation circuit 220 through the turned-on third sub-switch unit 123. When the logic determining unit 180 outputs the fifth level, the first sub-switching unit 121 is turned off, the second sub-switching unit 122 is turned off when the first sub-switching unit 121 is turned off, and the third sub-switching unit 123 is turned off when the second switching unit 120 is turned off, so that the device operation power supply circuit 210 cuts off power supply to the device operation circuit 220, and the device operation circuit 220 stops operating.

Optionally, the first sub-switching unit 121 includes a second switching tube Q12, a third resistor R60 and a fourth resistor R62; a first end of the second switch tube Q12 is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, a second end of the third resistor R60 is connected to the output end of the logic determination unit 180, a second end of the fourth resistor R62 is grounded, a second end of the second switch tube Q12 is connected to the first end of the second sub-switch unit 122, and a third end of the second switch tube Q12 is grounded. Specifically, in the first sub-switching unit 121, when the logic determining unit 180 outputs the fourth level, for example, when the logic determining unit is at a high level, the voltage dividing action of the third resistor R60 and the fourth resistor R62 generates a divided voltage at the first end of the second switching tube Q12, the divided voltage drives the second switching tube Q12 to be turned on, and when the second switching tube Q12 is turned on, the first end of the second sub-switching unit 122 is grounded. When the logic determining unit 180 outputs a fifth level, such as a low level, the first terminal of the second switch Q12 is at a low level, and the second switch Q12 is turned off.

Optionally, the second switch Q12 includes a transistor, a base set of the transistor is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, an emitter of the transistor is grounded, and a collector of the transistor is connected to the first end of the second sub-switch unit 122. The second switch Q12 may be a transistor, and the output of the logic determination unit 180 drives the base set of the transistor to turn on or off the transistor.

Optionally, the second sub-switching unit 122 includes a third switching tube Q13, a fifth resistor R164, and a sixth resistor R65; a first terminal of the third switching tube Q13 is connected to the first terminal of the fifth resistor R164 and the first terminal of the sixth resistor R65, a second terminal of the fifth resistor R164 is connected to the second terminal of the first sub-switching unit 121, a second terminal of the third switching tube Q13 is connected to the second terminal of the sixth resistor R65 and the power supply unit 110, and a third terminal of the third switching tube Q13 is connected to the first terminal of the third sub-switching unit 123. Specifically, in the second sub-switch unit 122, when the first sub-switch unit 121 is turned on, the power supply unit 110 generates a driving voltage at the first end of the third switch tube Q3 through the fifth resistor R164 and the sixth resistor R65 and the fifth resistor R164 and the sixth resistor R65 to drive the third switch tube Q13 to be turned on, and when the third switch tube Q13 is turned on, the power supply unit 110 electrically turns on the third sub-switch unit 123. When the first sub-switching unit 121 is turned off, no voltage division is generated between the fifth resistor R164 and the sixth resistor R65, the third switching tube Q13 is turned off, and the third sub-switching unit 123 is turned off.

Optionally, the third switching tube Q13 includes a second MOS tube, a gate of the second MOS tube is connected to the first end of the fifth resistor R164 and the first end of the sixth resistor R65, a drain of the second MOS tube is connected to the first end of the third sub-switching unit 123, and a source of the second MOS tube is connected to the second end of the sixth resistor R65 and the power supply unit 110. The third switching tube Q13 may be an MOS tube, for example, a PMOS tube, and a specific type may be AO4441, and a gate of the MOS tube is connected to the first sub-switching unit 121, and the MOS tube is driven to be turned on or off by the first sub-switching unit 121.

In one embodiment, the third sub-switching unit 123 includes a contactor switch and a current sink circuit; a first end of a coil of the contactor switch is connected with the third end of the second sub-switch unit 122 and a first end of the current absorption circuit, a second end of the coil of the contactor switch is connected with a second end of the current absorption circuit and the ground, a first connection end of a contact of the contactor switch is connected with the equipment working power supply circuit 210, and a second connection end of the contact of the contactor switch is connected with the equipment working circuit 220; specifically, the third sub-switch unit 123 is composed of a contactor switch 1231 and a current absorption circuit 1232, wherein the coil of the contactor switch 1231 controls power-on or power-off through the second sub-switch unit 122, and the contact of the contactor switch 1231 is respectively turned on or off when the coil of the contactor switch 1231 is powered on or powered off. The current absorption circuit is used for absorbing large current generated when the contactor coil is powered off.

In another embodiment, the current sinking circuit 1232 includes a diode VD9, a cathode of the diode VD9 is connected to a first end of the coil of the contactor switch, and an anode of the diode VD9 is connected to a second end of the coil of the contactor switch. Specifically, a large current generated when the contactor coil is de-energized can be absorbed by the diode VD 9. That is, when the contactor coil is de-energized, it forms a loop with the diode VD9 to discharge a large current generated when the contactor coil is de-energized.

Optionally, the WDI signal generating unit 150 and the third level generating unit 170 are integrated into a controller chip. Specifically, the WDI signal and the third electrical average may be generated by the controller chip U21. That is, the controller chip U21 periodically outputs WDI signals when its internal program is running normally, and turns off WDI signal output when its internal program is abnormal, and simultaneously monitors the configuration of its output port to the device state through the controller chip U21, and outputs the third level when the device state configuration is normal, otherwise turns off the third level. In one embodiment, the controller chip U21 may be of the type R5F52316 ADFP.

In addition, the present invention provides an electronic device, including the device abnormality protection circuit as described above. Namely, the working process of the electronic equipment is protected by the equipment abnormity protection circuit. So as to quickly cut off the injection of the main loop large circuit when the equipment is abnormal. The electronic equipment can be various electrical equipment including cleaning equipment such as a floor washing machine.

It is to be understood that the foregoing examples merely represent preferred embodiments of the present invention, and that the description thereof is more specific and detailed, but not intended to limit the scope of the invention; it should be noted that, for those skilled in the art, the above technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims (15)

1. An equipment anomaly protection circuit, comprising: a power supply unit, and

the switching unit is used for connecting the equipment working power supply circuit and the equipment working circuit;

a first level generation unit for connecting a device start-up circuit and configured to output a first level when the device start-up circuit is triggered to start up and to turn off the first level when the device start-up circuit is turned off;

a WDI signal generation unit configured to periodically output a WDI signal when a program of the device is operating normally;

the second level generating unit is connected with the WDI signal generating unit and used for receiving the WDI signal to output a second level and turning off the second level when the turn-off duration of the WDI signal exceeds the preset time;

a third level generation unit configured to output a third level when the state configuration of the device is normal, and to turn off the third level when the state configuration of the device is abnormal;

a logic judgment unit connected to the first level generation unit, the second level generation unit, and the third level generation unit, wherein the logic judgment unit is configured to output a fourth level when the first level, the second level, and the third level are received at the same time, and otherwise output a fifth level;

the switch unit is further connected with the logic judgment unit and is configured to be switched on when receiving the fourth level and switched off when receiving the fifth level.

2. The device abnormality protection circuit according to claim 1, wherein the second level generation unit includes: WDI chip U9 and D flip-flop U1;

a first pin of the WDI chip U9 is connected with a third pin of the D flip-flop U1, a second pin of the WDI chip U9 is grounded, a fourth pin of the WDI chip U9 is connected with the WDI signal generation unit, a fifth pin of the WDI chip U9 is connected with the power supply unit, a first pin of the D flip-flop U1 is connected with the WDI signal generation unit and the power supply unit, and a second pin and a fourth pin of the D flip-flop U1 are respectively connected with the power supply unit; and a sixth pin of the D trigger U1 is connected with the logic judgment unit.

3. The device abnormality protection circuit according to claim 1, wherein the logic judgment unit includes a first and gate circuit and a second and gate circuit;

the first input end of the first AND gate circuit is connected with the second level generation unit, the second input end of the first AND gate circuit is connected with the third level generation unit, the output end of the first AND gate circuit is connected with the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected with the first level generation unit, and the output end of the second AND gate circuit is connected with the switch unit.

4. The device abnormality protection circuit according to claim 3, wherein said first AND gate circuit and said second AND gate circuit are integrated into a two-way, two-input AND gate chip U10.

5. The device abnormality protection circuit according to claim 3, wherein the first level generating unit includes a first switching tube Q1, a first resistor R36, and a second resistor R37;

the first end of the first switch tube Q1 is used for receiving a starting signal of the equipment starting circuit, the first end of the first switch tube Q1 is further connected with the first end of the first resistor R36, the second end of the first resistor R36 is grounded, the second end of the first switch tube Q1 is connected with the power supply unit, the third end of the first switch tube Q1 is connected with the second input end of the second and gate circuit and the first end of the second resistor R37, and the second end of the second resistor R37 is grounded.

6. The device abnormality protection circuit according to claim 5,

the first level generating unit further comprises a TVS transistor TVS1, a cathode of the TVS transistor TVS1 is connected to the third terminal of the first switching transistor Q1, and an anode of the TVS transistor TVS1 is grounded; and/or

The first switch tube Q1 includes a first MOS transistor, a gate of the first MOS transistor is connected to the device start circuit, a source of the first MOS transistor is connected to the second input terminal of the second and circuit and the first end of the second resistor R37, and a drain of the first MOS transistor is connected to the power supply unit.

7. The device abnormality protection circuit according to claim 1, wherein the switching unit includes a first sub-switching unit, a second sub-switching unit, and a third sub-switching unit;

the first end of the first sub-switch unit is connected with the output end of the logic judgment unit, the second end of the first sub-switch unit is connected with the first end of the second sub-switch unit, the third end of the first sub-switch unit is grounded, the second end of the second sub-switch unit is connected with the power supply unit, the third end of the second sub-switch unit is connected with the first end of the third sub-switch unit, the second end of the third sub-switch unit is grounded, the third end of the third sub-switch unit is connected with the equipment working power supply circuit, and the fourth end of the third sub-switch unit is connected with the equipment working circuit.

8. The device abnormality protection circuit according to claim 7, wherein the first sub-switching unit includes a second switching tube Q12, a third resistor R60 and a fourth resistor R62;

the first end of the second switch tube Q12 is connected to the first end of the third resistor R60 and the first end of the fourth resistor R62, the second end of the third resistor R60 is connected to the output end of the logic judgment unit, the second end of the fourth resistor R62 is grounded, the second end of the second switch tube Q12 is connected to the first end of the second sub-switch unit, and the third end of the second switch tube Q12 is grounded.

9. The device abnormality protection circuit according to claim 8, wherein the second switching transistor Q12 includes a transistor, a base set of the transistor is connected to the first terminal of the third resistor R60 and the first terminal of the fourth resistor R62, an emitter of the transistor is grounded, and a collector of the transistor is connected to the first terminal of the second sub-switching unit.

10. The device abnormality protection circuit according to claim 7, wherein the second sub-switching unit includes a third switching tube Q13, a fifth resistor R164, and a sixth resistor R65;

a first terminal of the third switching tube Q13 is connected to the first terminal of the fifth resistor R164 and the first terminal of the sixth resistor R65, a second terminal of the fifth resistor R164 is connected to the second terminal of the first sub-switching unit, a second terminal of the third switching tube Q13 is connected to the second terminal of the sixth resistor R65 and the power supply unit, and a third terminal of the third switching tube Q13 is connected to the first terminal of the third sub-switching unit.

11. The device abnormality protection circuit according to claim 10,

the third switching tube Q13 includes a second MOS tube, a gate of the second MOS tube is connected to the first end of the fifth resistor R164 and the first end of the sixth resistor R65, a drain of the second MOS tube is connected to the first end of the third sub-switching unit, and a source of the second MOS tube is connected to the second end of the sixth resistor R65 and the power supply unit.

12. The device abnormality protection circuit according to claim 7, wherein the third sub-switching unit includes a contactor switch and a current sink circuit;

the first end of the coil of the contactor switch is connected with the third end of the second sub-switch unit and the first end of the current absorption circuit, the second end of the coil of the contactor switch is connected with the second end of the current absorption circuit and the ground, the first connecting end of the contact of the contactor switch is connected with the equipment working power supply circuit, and the second connecting end of the contact of the contactor switch is connected with the equipment working circuit.

13. The device abnormality protection circuit according to claim 12,

the current absorption circuit comprises a diode VD9, wherein the cathode of the diode VD9 is connected with the first end of the coil of the contactor switch, and the anode of the diode VD9 is connected with the second end of the coil of the contactor switch.

14. The device abnormality protection circuit according to claim 1, wherein said WDI signal generating unit and said third level generating unit are integrated in a controller chip.

15. An electronic device characterized by comprising the device abnormality protection circuit according to any one of claims 1 to 14.

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