CN215072368U - Signal acquisition circuit and signal acquisition device - Google Patents
Signal acquisition circuit and signal acquisition device Download PDFInfo
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- CN215072368U CN215072368U CN202121512755.1U CN202121512755U CN215072368U CN 215072368 U CN215072368 U CN 215072368U CN 202121512755 U CN202121512755 U CN 202121512755U CN 215072368 U CN215072368 U CN 215072368U
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Abstract
The application relates to a signal acquisition circuit and a signal acquisition device. The circuit includes: the device comprises an EMI filter, an operational amplifier, an anti-aliasing filter, an analog-to-digital converter, a positive power supply module and a negative power supply module; the positive input end and the negative input end of the EMI filter are used as input ends of signals, the positive output end of the EMI filter is connected with the positive input end of the operational amplifier, the negative output end of the EMI filter is connected with the negative input end of the operational amplifier, the positive power source end of the operational amplifier is connected with the output end of the positive power module, the negative power source end of the operational amplifier is connected with the output end of the negative power module, the output end of the operational amplifier is connected with the input end of the anti-aliasing filter, the output end of the anti-aliasing filter is connected with the positive input end of the analog-to-digital converter, the negative input end of the analog-to-digital converter is connected with the output end of the negative power module, and the output end of the analog-to-digital converter outputs signals. The signal amplification, filtering and sampling are realized, the sampling precision reaches 0.2uV, and the sampling precision is improved.
Description
Technical Field
The application relates to the technical field of signal acquisition, in particular to a signal acquisition circuit and a signal acquisition device.
Background
In the field of signal acquisition, one or more sets of very precise measuring instruments are generally required for acquiring weak signals (such as electric signals, optical signals, sound signals, force and the like), an internal circuit part of a general acquisition instrument on the market is mainly designed and completed by an analog-to-digital converter, and signals are directly connected to the analog-to-digital converter without being preprocessed, so that the sampling precision of the acquisition instrument is low.
SUMMERY OF THE UTILITY MODEL
In view of the above, it is necessary to provide a signal acquisition circuit and a signal acquisition device capable of improving sampling accuracy.
A signal acquisition circuit, the circuit comprising: the device comprises an EMI filter, an operational amplifier, an anti-aliasing filter, an analog-to-digital converter, a positive power supply module and a negative power supply module;
the positive input end and the negative input end of the EMI filter are used as input ends of signals, the positive output end of the EMI filter is connected with the positive input end of the operational amplifier, the negative output end of the EMI filter is connected with the negative input end of the operational amplifier, the positive power source end of the operational amplifier is connected with the output end of the positive power module, the negative power source end of the operational amplifier is connected with the output end of the negative power module, the output end of the operational amplifier is connected with the input end of the anti-aliasing filter, the output end of the anti-aliasing filter is connected with the positive input end of the analog-to-digital converter, the negative input end of the analog-to-digital converter is connected with the output end of the negative power module, and the output end of the analog-to-digital converter outputs signals.
In one embodiment, the EMI filter comprises: the circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor and a third capacitor;
one end of the first resistor is used as a positive input end of the EMI filter, the other end of the first resistor is respectively connected with one end of the first capacitor, one end of the third capacitor and the positive input end of the operational amplifier, one end of the second resistor is used as a negative input end of the EMI filter, the other end of the second resistor is respectively connected with one end of the second capacitor, the other end of the third capacitor and the negative input end of the operational amplifier, and the other end of the first capacitor and the other end of the second capacitor are grounded.
In one embodiment, the operational amplifier includes: the circuit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first amplifier and a second amplifier;
one end of the fourth resistor is used as a negative input end of the operational amplifier, the other end of the fourth resistor is connected with a non-inverting input end of the first amplifier, one end of the third resistor is used as a positive input end of the operational amplifier, the other end of the third resistor is respectively connected with an inverting input end of the first amplifier and one end of the fifth resistor, a VCC end of the first amplifier is used as a positive power source end of the operational amplifier and is connected with an output end of the positive power module, a VSS end of the first amplifier is used as a negative power source end of the operational amplifier and is connected with an output end of the negative power module, an output end of the first amplifier is respectively connected with the other end of the fifth resistor and one end of the sixth resistor, and the other end of the sixth resistor is respectively connected with an inverting input end of the second amplifier and one end of the eighth resistor, the VCC end of the second amplifier is used as the positive power supply end of the operational amplifier and connected with the output end of the positive power supply module, the VSS end of the second amplifier is used as the negative power supply end of the operational amplifier and connected with the output end of the negative power supply module, the non-inverting input end of the second amplifier is connected with one end of the seventh resistor, the other end of the seventh resistor is grounded, and the output end of the second amplifier is respectively connected with the other end of the eighth resistor and the input end of the anti-aliasing filter.
In one embodiment, the first amplifier is an amplifier of type OPA 2210.
In one embodiment, the second amplifier is an amplifier of type OPA 2210.
In one embodiment, the anti-aliasing filter comprises: a ninth resistor and a fourth capacitor;
one end of the ninth resistor is used as the input end of the anti-aliasing filter, the other end of the ninth resistor is respectively connected with one end of the fourth capacitor and the positive input end of the analog-to-digital converter, and the other end of the fourth capacitor is grounded.
In one embodiment, the analog-to-digital converter includes: the analog-to-digital conversion chip and the tenth resistor;
an AINP _ A pin of the analog-to-digital conversion chip is used as a positive input end of the analog-to-digital converter, an AINM _ A pin of the analog-to-digital conversion chip is connected with one end of a tenth resistor, the other end of the tenth resistor is connected with a negative input end of the analog-to-digital converter and is connected with an output end of the negative power module, a CS pin, an SCLK pin, an SDI pin and an SDO _ A pin of the analog-to-digital conversion chip are used as output end output signals of the analog-to-digital converter, an AVDD pin, a DVDD pin and an REFIO _ A pin of the analog-to-digital conversion chip are connected to a 5V direct-current power supply, and a REFGND _ A pin of the analog-to-digital conversion chip is grounded.
In one embodiment, the positive power module comprises: the linear voltage-stabilized power supply comprises a linear voltage-stabilized power supply, a fifth capacitor, a sixth capacitor and a seventh capacitor;
an IN pin of the linear stabilized voltage power supply, an SHDN pin of the linear stabilized voltage power supply and one end of a fifth capacitor are used as input ends of the positive power supply module, the other end of the fifth capacitor is grounded, a BYP pin of the linear stabilized voltage power supply is connected with one end of a sixth capacitor, the other end of the sixth capacitor, a SENSE pin of the linear stabilized voltage power supply, an OUT pin of the linear stabilized voltage power supply and one end of a seventh capacitor are used as output ends of the positive power supply module, the other end of the seventh capacitor is grounded, and a GND pin of the linear stabilized voltage power supply is grounded.
In one embodiment, the negative power module includes: the voltage stabilizer, the eighth capacitor, the ninth capacitor, the first electrolytic capacitor, the second electrolytic capacitor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the first inductor, the second inductor and the diode;
the positive electrode of the first electrolytic capacitor, one end of the first inductor, the SHDN pin of the voltage stabilizer and the IN pin of the voltage stabilizer are used as the input end of the negative power module, the negative electrode of the first electrolytic capacitor is grounded, the other end of the first inductor is respectively connected with the SW pin of the voltage stabilizer and one end of the eighth capacitor, the other end of the eighth capacitor is respectively connected with one end of the second inductor and the anode of the diode, the cathode of the diode is grounded, the Vc pin of the voltage stabilizer is connected with one end of the eleventh resistor, the other end of the eleventh resistor is connected with one end of the ninth capacitor, the other end of the ninth capacitor is grounded, the NFB pin of the voltage stabilizer is respectively connected with one end of the twelfth resistor and one end of the thirteenth resistor, and the other end of the thirteenth resistor is grounded, the other end of the twelfth resistor, the other end of the second inductor and one end of the second electrolytic capacitor are used as output ends of the negative power module, and the other end of the second electrolytic capacitor is grounded.
A signal collector, comprising: the signal acquisition circuit is provided.
The signal acquisition circuit and the signal acquisition device take the positive input end and the negative input end of the EMI filter as the input ends of signals, the positive output end of the EMI filter is connected with the positive input end of the operational amplifier, the negative output end of the EMI filter is connected with the negative input end of the operational amplifier, the positive power source end of the operational amplifier is connected with the output end of the positive power module, the negative power source end of the operational amplifier is connected with the output end of the negative power module, the output end of the operational amplifier is connected with the input end of the anti-aliasing filter, the output end of the anti-aliasing filter is connected with the positive input end of the analog-to-digital converter, the negative input end of the analog-to-digital converter is connected with the output end of the negative power module, and the output end of the analog-to-digital converter outputs signals. The signal amplification, filtering and sampling are realized, the sampling precision reaches 0.2uV, and the sampling precision is improved.
Drawings
FIG. 1 is a schematic diagram of a signal acquisition circuit according to an embodiment;
FIG. 2 is a schematic diagram of the EMI filter and operational amplifier of the signal acquisition circuit in one embodiment;
FIG. 3 is a schematic diagram of an anti-aliasing filter and an analog-to-digital converter in a signal acquisition circuit according to an embodiment;
FIG. 4 is a schematic diagram of a positive power module in the signal acquisition circuit in one embodiment;
FIG. 5 is a schematic diagram of a negative power module in the signal acquisition circuit in one embodiment;
FIG. 6 is a PCB layout of circuit acquisition circuitry.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, there is provided a signal acquisition circuit, characterized in that the circuit comprises: an EMI filter 110, an operational amplifier 120, an anti-aliasing filter 130, and an analog-to-digital converter 140; the positive input end and the negative input end of the EMI filter 110 are used as input ends of signals, the positive output end of the EMI filter 110 is connected with the positive input end of the operational amplifier 120, the negative output end of the EMI filter 110 is connected with the negative input end of the operational amplifier 120, the positive power end of the operational amplifier 120 is connected with the output end of the positive power module, the negative power end of the operational amplifier 120 is connected with the output end of the negative power module, the output end of the operational amplifier 120 is connected with the input end of the anti-aliasing filter 130, the output end of the anti-aliasing filter 130 is connected with the positive input end of the analog-to-digital converter 140, the negative input end of the analog-to-digital converter 140 is connected with the output end of the negative power module, and the output end of the analog-to-digital converter 140 outputs signals.
Wherein, the signal (the signal is an analog signal) is input from the positive input terminal and the negative input terminal of the EMI filter 110, and is output from the positive output terminal and the negative output terminal of the EMI filter 110 to the operational amplifier 120, and is amplified by the operational amplifier 120 and then output to the anti-aliasing filter 130, and then is output from the anti-aliasing filterThe stack filter 130 outputs to an analog-to-digital converter 140, and the analog-to-digital converter 140 performs analog-to-digital conversion on the signal and converts the signal into a digital signal output. The operational amplifier 120 has a magnification of 382 times. The signal acquisition circuit realizes the sampling precision of
The circuit realizes amplification, filtering and sampling of signals, and has the effects of high sampling rate and low noise aiming at micro signal processing.
As shown in fig. 2, in one embodiment, the EMI filter 110 includes: the circuit comprises a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2 and a third capacitor C3; one end of the first resistor R1 is used as the positive input end of the EMI filter 110, the other end of the first resistor R1 is connected to one end of the first capacitor C1, one end of the third capacitor C3 and the positive input end of the operational amplifier 120, one end of the second resistor R2 is used as the negative input end of the EMI filter 110, the other end of the second resistor R2 is connected to one end of the second capacitor C2, the other end of the third capacitor C3 and the negative input end of the operational amplifier 120, and the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded.
In terms of circuit implementation, the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2 of the EMI filter 110 form a low-pass filter, and then the high-frequency interference stabilizing circuit is further filtered by the third capacitor C3.
In one embodiment, the operational amplifier 120 includes: the circuit comprises a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first amplifier P1 and a second amplifier P2.
One end of a fourth resistor R4 is used as the negative input terminal of the operational amplifier 120, the other end of the fourth resistor R4 is connected to the non-inverting input terminal of the first amplifier P1, one end of a third resistor R3 is used as the positive input terminal of the operational amplifier 120, the other end of the third resistor R3 is connected to the inverting input terminal of the first amplifier P1 and one end of a fifth resistor R5, respectively, the VCC terminal of the first amplifier P1 is used as the positive power terminal of the operational amplifier 120 and connected to the output terminal of the positive power module, the VSS terminal of the first amplifier P1 is used as the negative power terminal of the operational amplifier 120 and connected to the output terminal of the negative power module, the output terminal of the first amplifier P1 is connected to the other end of the fifth resistor R5 and one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the inverting input terminal of the second amplifier P2 and one end of the eighth resistor R8, respectively, the VCC terminal of the second amplifier P2 is connected to the positive power terminal of the positive power module, the VSS terminal of the second amplifier P2 is connected to the output terminal of the negative power module as the negative power supply terminal of the operational amplifier 120, the non-inverting input terminal of the second amplifier P2 is connected to one terminal of the seventh resistor R7, the other terminal of the seventh resistor R7 is grounded, and the output terminal of the second amplifier P2 is connected to the other terminal of the eighth resistor R8 and the input terminal of the anti-aliasing filter 130, respectively.
In one embodiment, the first amplifier P1 is an amplifier model OPA 2210.
In one embodiment, the second amplifier P2 is an amplifier model OPA 2210.
Wherein the amplifier of OPA2210 is an ultra-low noise density
The amplifier has the advantages of ultra-low power consumption (2.5mA), high gain bandwidth product (18MHz), high common mode rejection ratio (140dB) and high precision, and the common mode rejection ratio can reach 130 dB. The amplification factor is adjusted by changing the resistance values of the input resistor and the feedback resistor. The operational amplifier 120 finally achieves signal amplification through two stages of amplifiers. The gain multiple G1 of the first amplifier P1, R5, R3, 19.1K Ω/100 Ω 191, the gain multiple G2 of the second amplifier P2, R8, R6, 2K Ω/1K Ω 2, the total gain of the operational amplifier 120, G1, G2, the signal bandwidth can reach 50KHz, and the body noise is controlled within 0.5 uVpp.
As shown in fig. 3, in one embodiment, the anti-aliasing filter 130 includes: a ninth resistor R9 and a fourth capacitor C4; one end of the ninth resistor R9 is used as the input end of the anti-aliasing filter 130, the other end of the ninth resistor R9 is connected to one end of the fourth capacitor C4 and the positive input end of the analog-to-digital converter 140, and the other end of the fourth capacitor C4 is grounded.
Where the anti-aliasing filter 130 suppresses signal interference outside the sampling band. In the aspect of circuit implementation, the ninth resistor R9 and the fourth capacitor C4 form a low-pass filter together to realize anti-aliasing, the cut-off frequency of the anti-aliasing filter is 66KHZ, and the required signal bandwidth can be met by 50KHz around 50 KHz.
In one embodiment, the analog-to-digital converter 140 includes: an analog-to-digital conversion chip P3 and a tenth resistor R10; an AINP _ a pin of the analog-to-digital conversion chip P3 is used as a positive input terminal of the analog-to-digital converter 140, an AINM _ a pin of the analog-to-digital conversion chip P3 is connected with one end of a tenth resistor R10, the other end of the tenth resistor R10 is connected with a negative input terminal of the analog-to-digital converter 140 and is connected with an output terminal of the negative power module, a CS pin, an SCLK pin, an SDI pin and an SDO _ a pin of the analog-to-digital conversion chip P3 are used as output signals of the analog-to-digital converter 140, an AVDD pin, a DVDD pin and a REFIO _ a pin of the analog-to-digital conversion chip P3 are connected with a 5V dc power supply AVDD, and a refga pin of the analog-to-digital conversion chip P3 is grounded.
The model of the analog-to-digital conversion chip P3 is ADS8355, and the conversion from an analog signal to a digital signal is completed through the analog-to-digital conversion chip P3. The ADS8355 is a double-channel analog-to-digital converter (ADC) with single power supply, and can realize double-channel 16-bit and 1MSps synchronous acquisition. In terms of circuit implementation, the signal output by the anti-aliasing filter 130 is input to the AINP _ a pin of the ADS8355, and the AINM _ a pin of the ADS8355 is connected to the output terminal VSS of the negative power supply module through the protection tenth resistor R10. The negative power supply module supplies the ADS8355 with half of the 5V direct current power supply. Each acquisition channel value is equal to the AINP _ a pin voltage minus the AINM _ a pin voltage. Therefore, when the AINM _ a pin inputs a negative voltage, the input signal is raised to satisfy the ADS8355 acquisition voltage range. The ADS8355 transmits the weak signal to the master control system through the serial bus SPI, and the SPI bus is connected with an SDI pin (SPI bus serial input port), a CS pin (SPI bus chip select port), an SCLK pin (SPI bus clock port) and an SDO _ A pin (SPI bus serial output port) of the ADS 8355. The other pins of the ADS8355 are suspended, and the suspended pins can be connected with circuits with other functions at the later stage according to actual use requirements.
As shown in fig. 4, in one embodiment, the positive power module includes: a linear regulated power supply P4, a fifth capacitor C5, a sixth capacitor C6 and a seventh capacitor C7; an IN pin of a linear stabilized power supply P4, an SHDN pin of a linear stabilized power supply P4 and one end of a fifth capacitor C5 are used as input ends of the positive power supply module, the other end of the fifth capacitor C5 is grounded, a BYP pin of the linear stabilized power supply P4 is connected with one end of a sixth capacitor C6, the other end of a sixth capacitor C6, a SENSE pin of the linear stabilized power supply P4, an OUT pin of the linear stabilized power supply P4 and one end of a seventh capacitor C7 are used as output ends of the positive power supply module, the other end of the seventh capacitor C7 is grounded, and a GND pin of the linear stabilized power supply P4 is grounded.
As shown in fig. 5, in one embodiment, the negative power module includes: the voltage stabilizer P5, the eighth capacitor C10, the ninth capacitor C9, the first electrolytic capacitor C8, the second electrolytic capacitor C11, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R12, the first inductor L1, the second inductor L2 and the diode D1; the anode of the first electrolytic capacitor C8, one end of the first inductor L1, the SHDN pin of the regulator P5 and the IN pin of the regulator P5 serve as input terminals of the negative power supply module, the cathode of the first electrolytic capacitor C8 is grounded, the other end of the first inductor L1 is connected to the SW pin of the regulator P5 and one end of the eighth capacitor C10, the other end of the eighth capacitor C10 is connected to one end of the second inductor L2 and the anode of the diode D1, the cathode of the diode D1 is grounded, the Vc pin of the regulator P5 is connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to one end of the ninth capacitor C9, the other end of the ninth capacitor C9 is grounded, the NFB pin of the regulator P5 is connected to one end of the twelfth resistor 12 and one end of the thirteenth resistor R12, the other end of the thirteenth resistor R12 is grounded, the other end of the twelfth resistor R12, the other end of the second inductor L53 and one end of the negative power supply module of the second capacitor P5 serve as output terminals of the negative power supply module, the other end of the second electrolytic capacitor C11 is grounded.
The positive power supply module provides a positive power supply for the signal acquisition circuit, and the negative power supply module provides a negative power supply for the signal acquisition circuit. Diode D1 is a schottky diode, linear regulator P4 is a chip model LT1763-2.5, and regulator P5 is a chip model LT 1614. The positive power supply module is powered by a 5V direct-current power supply and outputs a 2.5V direct-current power supply, and the negative power supply module is powered by the 5V direct-current power supply and outputs a-2.5V direct-current power supply. The first amplifier P1 and the second amplifier P2 need to be powered by +/-2.5V voltage, and the negative input end of the acquisition channel of the analog-to-digital conversion chip P3 needs to be powered by-AVDD/2 voltage (namely-2.5V), so that a linear stabilized voltage power supply P4 is used for converting an output positive 2.5V direct current power supply to provide a positive 2.5V direct current power supply for the first amplifier P1 and the second amplifier P2, and a voltage stabilizer P5 is used for converting an output-2.5V direct current power supply to provide a negative 2.5V direct current power supply for the first amplifier P1, the second amplifier P2 and the acquisition channel of the analog-to-digital conversion chip P3.
IN circuit implementation, a 5V direct-current power supply enters an IN pin and an SHDN pin of a linear stabilized power supply P4, and a BYP pin of a linear stabilized power supply P4 is connected with a SENSE pin through a bypass sixth capacitor C6, so that power supply ripples are reduced. The level is converted from the OUT pin of linear regulated power supply P4 to output 2.5V. The 5V dc power enters the SHDN pin and the IN pin of regulator P5. The Vc pin of the voltage regulator P5 is grounded through an eleventh resistor R11 and a ninth capacitor C9, so that error compensation is performed on the level conversion. The SW pin of the voltage stabilizer P5 is connected with a 5V direct current power supply through a first inductor L1, an EMI filter in the voltage stabilizer P5 is enabled, the EMI filter is grounded through an eighth capacitor C10 and a diode D1, and ripple interference after level conversion is reduced by connecting a second inductor L2 as the output end of the negative power supply module. The NFB pin of the voltage regulator P5 is a negative feedback pin, and the output voltage of the negative power module is calculated according to the resistance values of the twelfth resistor R12 and the thirteenth resistor R13, and the formula is as follows:
VSS is the output voltage of the negative power supply module, R12Is the resistance value of a twelfth resistor R1213Is the resistance value of the thirteenth resistor R13. The twelfth resistor R12 is set to 9.8K omega, and the power output is-2.5V when the thirteenth resistor R13 is 10K omega.
The PCB layout composed according to the circuit acquisition circuit is shown in FIG. 6.
The signal acquisition circuit realizes the acquisition precision of 0.2uV, the body noise of less than 0.5uVPP and the sampling frequency of up to 1MSps through the EMI filter 110, the precise operational amplifier 120, the anti-aliasing filter 130 and the analog-to-digital converter 140 with high precision and high sampling rate, and can acquire weak signals by combining a photoelectric conversion sensor, an acoustic-electric conversion sensor and a piezoelectric conversion sensor. The method is used for acquiring brain-like robot sensor signals, vehicle-mounted radar information and night light signals, acquiring more precise and weaker information and assisting in developing a more intelligent recognition algorithm.
In one embodiment, a signal collector comprises the signal collecting circuit of any one of the above embodiments.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A signal acquisition circuit, the circuit comprising: the device comprises an EMI filter, an operational amplifier, an anti-aliasing filter, an analog-to-digital converter, a positive power supply module and a negative power supply module;
the positive input end and the negative input end of the EMI filter are used as input ends of signals, the positive output end of the EMI filter is connected with the positive input end of the operational amplifier, the negative output end of the EMI filter is connected with the negative input end of the operational amplifier, the positive power source end of the operational amplifier is connected with the output end of the positive power module, the negative power source end of the operational amplifier is connected with the output end of the negative power module, the output end of the operational amplifier is connected with the input end of the anti-aliasing filter, the output end of the anti-aliasing filter is connected with the positive input end of the analog-to-digital converter, the negative input end of the analog-to-digital converter is connected with the output end of the negative power module, and the output end of the analog-to-digital converter outputs signals.
2. The circuit of claim 1, wherein the EMI filter comprises: the circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor and a third capacitor;
one end of the first resistor is used as a positive input end of the EMI filter, the other end of the first resistor is respectively connected with one end of the first capacitor, one end of the third capacitor and the positive input end of the operational amplifier, one end of the second resistor is used as a negative input end of the EMI filter, the other end of the second resistor is respectively connected with one end of the second capacitor, the other end of the third capacitor and the negative input end of the operational amplifier, and the other end of the first capacitor and the other end of the second capacitor are grounded.
3. The circuit of claim 1, wherein the operational amplifier comprises: the circuit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first amplifier and a second amplifier;
one end of the fourth resistor is used as a negative input end of the operational amplifier, the other end of the fourth resistor is connected with a non-inverting input end of the first amplifier, one end of the third resistor is used as a positive input end of the operational amplifier, the other end of the third resistor is respectively connected with an inverting input end of the first amplifier and one end of the fifth resistor, a VCC end of the first amplifier is used as a positive power source end of the operational amplifier and is connected with an output end of the positive power module, a VSS end of the first amplifier is used as a negative power source end of the operational amplifier and is connected with an output end of the negative power module, an output end of the first amplifier is respectively connected with the other end of the fifth resistor and one end of the sixth resistor, and the other end of the sixth resistor is respectively connected with an inverting input end of the second amplifier and one end of the eighth resistor, the VCC end of the second amplifier is used as the positive power supply end of the operational amplifier and connected with the output end of the positive power supply module, the VSS end of the second amplifier is used as the negative power supply end of the operational amplifier and connected with the output end of the negative power supply module, the non-inverting input end of the second amplifier is connected with one end of the seventh resistor, the other end of the seventh resistor is grounded, and the output end of the second amplifier is respectively connected with the other end of the eighth resistor and the input end of the anti-aliasing filter.
4. The circuit of claim 3, wherein the first amplifier is an amplifier of type OPA 2210.
5. The circuit of claim 3, wherein the second amplifier is an amplifier of type OPA 2210.
6. The circuit of claim 1, wherein the anti-aliasing filter comprises: a ninth resistor and a fourth capacitor;
one end of the ninth resistor is used as the input end of the anti-aliasing filter, the other end of the ninth resistor is respectively connected with one end of the fourth capacitor and the positive input end of the analog-to-digital converter, and the other end of the fourth capacitor is grounded.
7. The circuit of claim 1, wherein the analog-to-digital converter comprises: the analog-to-digital conversion chip and the tenth resistor;
an AINP _ A pin of the analog-to-digital conversion chip is used as a positive input end of the analog-to-digital converter, an AINM _ A pin of the analog-to-digital conversion chip is connected with one end of a tenth resistor, the other end of the tenth resistor is connected with a negative input end of the analog-to-digital converter and is connected with an output end of the negative power module, a CS pin, an SCLK pin, an SDI pin and an SDO _ A pin of the analog-to-digital conversion chip are used as output end output signals of the analog-to-digital converter, an AVDD pin, a DVDD pin and an REFIO _ A pin of the analog-to-digital conversion chip are connected to a 5V direct-current power supply, and a REFGND _ A pin of the analog-to-digital conversion chip is grounded.
8. The circuit of claim 1, wherein the positive power module comprises: the linear voltage-stabilized power supply comprises a linear voltage-stabilized power supply, a fifth capacitor, a sixth capacitor and a seventh capacitor;
an IN pin of the linear stabilized voltage power supply, an SHDN pin of the linear stabilized voltage power supply and one end of a fifth capacitor are used as input ends of the positive power supply module, the other end of the fifth capacitor is grounded, a BYP pin of the linear stabilized voltage power supply is connected with one end of a sixth capacitor, the other end of the sixth capacitor, a SENSE pin of the linear stabilized voltage power supply, an OUT pin of the linear stabilized voltage power supply and one end of a seventh capacitor are used as output ends of the positive power supply module, the other end of the seventh capacitor is grounded, and a GND pin of the linear stabilized voltage power supply is grounded.
9. The circuit of claim 1, wherein the negative power module comprises: the voltage stabilizer, the eighth capacitor, the ninth capacitor, the first electrolytic capacitor, the second electrolytic capacitor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the first inductor, the second inductor and the diode;
the positive electrode of the first electrolytic capacitor, one end of the first inductor, the SHDN pin of the voltage stabilizer and the IN pin of the voltage stabilizer are used as the input end of the negative power module, the negative electrode of the first electrolytic capacitor is grounded, the other end of the first inductor is respectively connected with the SW pin of the voltage stabilizer and one end of the eighth capacitor, the other end of the eighth capacitor is respectively connected with one end of the second inductor and the anode of the diode, the cathode of the diode is grounded, the Vc pin of the voltage stabilizer is connected with one end of the eleventh resistor, the other end of the eleventh resistor is connected with one end of the ninth capacitor, the other end of the ninth capacitor is grounded, the NFB pin of the voltage stabilizer is respectively connected with one end of the twelfth resistor and one end of the thirteenth resistor, and the other end of the thirteenth resistor is grounded, the other end of the twelfth resistor, the other end of the second inductor and one end of the second electrolytic capacitor are used as output ends of the negative power module, and the other end of the second electrolytic capacitor is grounded.
10. A signal collector, comprising: a signal acquisition circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121512755.1U CN215072368U (en) | 2021-07-05 | 2021-07-05 | Signal acquisition circuit and signal acquisition device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121512755.1U CN215072368U (en) | 2021-07-05 | 2021-07-05 | Signal acquisition circuit and signal acquisition device |
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| Publication Number | Publication Date |
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| CN215072368U true CN215072368U (en) | 2021-12-07 |
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| CN202121512755.1U Expired - Fee Related CN215072368U (en) | 2021-07-05 | 2021-07-05 | Signal acquisition circuit and signal acquisition device |
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| Country | Link |
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| CN (1) | CN215072368U (en) |
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- 2021-07-05 CN CN202121512755.1U patent/CN215072368U/en not_active Expired - Fee Related
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