CN214959478U - Low-power consumption FBAR oscillator circuit based on heap - Google Patents

Abstract

The utility model provides a low-power consumption FBAR oscillator circuit based on heap, a serial communication port, include: sequentially connected: the power supply port, the current generation circuit unit and the stacked core oscillation circuit unit are arranged in the circuit; the current generation circuit unit is used for generating current irrelevant to input power supply voltage; the stacked core-based oscillation unit is used for providing negative resistance for compensating energy loss of a resonant tank. The circuit is based on a stacked Pierce oscillator structure, can realize a large output swing amplitude, and has the characteristics of low power consumption, low phase noise, small area and the like.

Description

Low-power consumption FBAR oscillator circuit based on heap

Technical Field

The utility model belongs to the technical field of oscillating circuit, specifically be an oscillating circuit that low-power consumption, low phase noise, area are little, especially relate to a low-power consumption FBAR oscillator circuit based on heap.

Background

With the rapid development of the internet of things, high requirements of low power consumption, low phase noise and low cost are provided for wireless sensor nodes. Because the quartz crystal oscillator has large size and difficult processing, the requirements of a wireless communication system cannot be met due to poor impact resistance and vibration resistance. Therefore, an FBAR oscillator circuit with high accuracy, low power consumption and low phase noise is particularly important.

For a conventional Pierce oscillator, the power consumption of the oscillator is mainly determined by the negative resistance formed by the inverter circuit. Therefore, the optimization of the Pierce oscillator is limited to the technology of improving the inverter to reduce the power consumption, for example, making a transistor in the inverter work in a weak inversion region, but the optimization has the disadvantages of poor stability and unsuitability for a high-frequency band, and thus cannot be satisfied in wireless communication.

SUMMERY OF THE UTILITY MODEL

In view of this, in order to compensate the blank and not enough of prior art, the utility model aims at providing a low-power consumption FBAR oscillator circuit based on heap, overcome the shortcoming that the consumption is high in the Pierce oscillator, and phase noise performance is poor, and the integrable degree is high. The stack-based low-power consumption FBAR oscillator circuit comprises: the power supply port, the current generation circuit unit and the stacked core oscillation circuit unit are arranged in the circuit; the power supply port is used for providing a power supply voltage of 3.3V; a current generating circuit unit for generating a current independent of an input power voltage; based on stacked core oscillator circuit units including load capacitor C₁、C₂A bandpass (low pass) filter of a pi-network with FBAR resonators and an N-th order stacked inverter are used to provide negative resistance to compensate for the energy loss of the resonant tank. The circuit is based on a stacked Pierce oscillator structure, can realize a large output swing amplitude, and has the characteristics of low power consumption, low phase noise, small area and the like.

The utility model discloses specifically adopt following technical scheme:

a stacked-based low-power FBAR oscillator circuit, comprising: sequentially connected: the power supply port, the current generation circuit unit and the stacked core oscillation circuit unit are arranged in the circuit; the current generation circuit unit is used for generating current irrelevant to input power supply voltage; the stacked core-based oscillation unit is used for providing negative resistance for compensating energy loss of a resonant tank.

Further, the power port is used for providing a power voltage of 3.3V; the power supply voltage of the MOS tube in the circuit is 3.3V.

Furthermore, the current generation circuit unit adopts a Widlar current mirror structure.

Further, the current generation circuit unit comprises a MOS (metal oxide semiconductor) tube PM₁、PM₂、NM₁、NM₂、NM₃、NM₄、PM₃And a control resistor R_bWherein, MOS tube PM₁、PM₂And PM₃The grid electrodes are connected, and the drain electrodes are also connected; MOS pipe PM₁、PM₂、NM₁、NM₂The source electrode and the grid electrode are both connected with a power supply port; MOS pipe PM₃The drain of the transistor is a current-generating output terminal; MOS tube NM₁And NM₂Drain electrodes of the MOS transistors are respectively connected with the NM₃And NM₄A source electrode of (a); MOS tube NM₃And NM₄Are connected with the grid of the MOS transistor NM₃Via a controlled resistance R_bGrounded, NM₄Is directly grounded.

Further, the stacked core oscillation circuit unit comprises a bandpass filter in a pi-network form and an N-order inverter; the N-order inverters are N inverters connected in parallel.

Further, the N-order stacked inverter is used to provide a negative resistance that compensates for the energy loss of the resonant tank, and the pi-network type band pass filter is used to provide the voltage gain required for 180 ° phase shift and oscillation.

Furthermore, each order of the N-order inverters comprises a feedback resistor R_BFor equalizing input and output voltages of inverters of each stage, output terminals of inverters of each stageThe input ends are respectively connected with a coupling capacitor C_CGAnd C_CDUsed for blocking.

Further, the bandpass filter in the form of a pi network includes: load capacitance C₁C2, FBAR resonator;

feedback resistance R of each order_BBoth ends of the first-order inverter are respectively connected with the input end and the output end of the first-order inverter, and the input end and the output end of each-order inverter are respectively connected with the coupling capacitor C_DAnd a coupling capacitor C_GConnecting; two ends of the FBAR resonator are respectively connected with the coupling capacitors C_CGAnd C_CDAre connected and respectively pass through a load capacitor C₁And C₂Grounding;

and the current generation output end of the current generation circuit unit is connected with the source electrode of a PMOS tube in the Nth-order phase inverter.

Compared with the prior art, the utility model discloses and its preferred scheme adopts the FBAR oscillator of heap Pierce structure, and the structure complexity is not high, has characteristics such as the area is little, low-power consumption and low phase noise.

Drawings

The invention will be described in further detail with reference to the following drawings and detailed description:

fig. 1 is a schematic diagram of a bias current generating circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a core oscillation circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of the stacked low power consumption FBAR oscillator circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of the basic structure of the embodiment of the present invention.

Detailed Description

In order to make the features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail as follows:

as shown in fig. 1 to 4, the stacked FBAR oscillator circuit according to the present embodiment includes: sequentially connected: the power supply port, the current generation circuit unit and the stacked core oscillation circuit unit are arranged in the circuit; the current generation circuit unit is used for generating current irrelevant to the input power supply voltage; the stacked core based oscillation unit is used for providing negative resistance for compensating energy loss of the resonant circuit.

Which uses multi-stage parallel connection of inverters to make transconductance g of each stage_mTransconductance g relative to a conventional first-order Pierce structure_mThe smaller N times, the smaller transconductance means that the smaller current enables the stack structure to greatly reduce power consumption and phase noise, and the MOS tube used for each stage of inverter by using the improved body bias technology works in a saturation region, so that the circuit has high stability.

In this embodiment, the frequency of the oscillator is 1.93GHz, and the power port is used to provide a power voltage of 3.3V; the power supply voltage of the MOS tube in the circuit is 3.3V.

As shown in FIG. 1, the current generation circuit unit adopts a Widlar current mirror structure for providing a bias current I independent of the power supply voltage_bias。

The current generation circuit unit comprises a MOS (metal oxide semiconductor) transistor PM₁、PM₂、NM₁、NM₂、NM₃、NM₄、PM₃And a control resistor R_bWherein, MOS tube PM₁、PM₂And PM₃The grid electrodes are connected, and the drain electrodes are also connected; MOS pipe PM₁、PM₂、NM₁、NM₂The source electrode and the grid electrode are both connected with a power supply port; MOS pipe PM₃The drain of the transistor is a current-generating output terminal; MOS tube NM₁And NM₂Drain electrodes of the MOS transistors are respectively connected with the NM₃And NM₄A source electrode of (a); MOS tube NM₃And NM₄Are connected with the grid of the MOS transistor NM₃Via a controlled resistance R_bGrounded, NM₄Is directly grounded.

As shown in FIG. 2, the stacked core-based oscillation circuit unit comprises a load capacitor C₁、C₂A pi-type (or pi-type) network type band-pass filter formed by the FBAR resonator, and an N-order inverter; the N-order inverter is N inverters connected in parallel.

An N-order inverter is used to provide a negative resistance that compensates for the energy loss of the resonant tank, and a bandpass filter in the form of a pi network is used to provide the voltage gain required for 180 phase shift and oscillation.

Each of the N-stage inverters includes a feedback resistor R_BThe input and output voltages of each stage of inverter are equal, and the output end and the input end of each stage of inverter are respectively connected with a coupling capacitor C_CGAnd C_CDUsed for blocking.

Feedback resistance R of each order_BBoth ends of the first-order inverter are respectively connected with the input end and the output end of the first-order inverter, and the input end and the output end of each-order inverter are respectively connected with the coupling capacitor C_DAnd a coupling capacitor C_GConnecting; two ends of the FBAR resonator are respectively connected with the coupling capacitors C_CGAnd C_CDAre connected and respectively pass through a load capacitor C₁And C₂Grounding;

the current generating circuit unit has a current generating output end connected to the source of the PMOS tube in the Nth order inverter.

In the present embodiment, the bias current I generated by the current generation circuit unit_BiasThe size is as follows:

wherein μ is the carrier mobility of the NMOS transistor, Cox is the unit capacitance of the gate oxide, (W/L)₃And (W/L)₄Are MOS transistors NM respectively₃、NM₄The width to length ratio of the tube;

if the channel modulation effect is taken into account, the bias current I_BiasWriting into:

where λ is the channel length modulation factor, V_GS3For MOS transistor NM₃The gate-source voltage of the tube.

The core oscillation circuit is formed by cascading N inverters through two filter capacitors CG and CD, wherein each inverter comprises a feedback resistor R_bAnd for improvement ofThe resistance R of the body bias technology and the transconductance of the N-order inverter are shown as follows:

wherein g is_miIs the transconductance of each stage of inverter;

whether a conventional Pierce-structured oscillator or a stacked oscillator requires a negative resistance for energizing the FBAR resonator, the negative resistance provided by the present embodiment is as follows:

wherein, ω is_oscIs a resonant frequency, C₁And C₂Is the value of the load capacitance, C₃Is the value of the shunt parasitic capacitance of the FBAR.

Assuming that the channel lengths of the NMOS transistor and the PMOS transistor are the same, namely L_N＝L_PWhen the size of each stage of inverter is equal, g is easily obtained_mN，g_mP，G_MCurrent I of_DAnd the order N is:

the formula (2) is taken into the formula (4) and combined with the formula (3), and comprises the following components:

on the ideal premise that adverse factors such as temperature, MOS transistor size and process difference and the like and the same power supply voltage are not considered, compared with the traditional Pierce structure oscillating circuit, the stacked low-power consumption FBAR oscillator circuit reduces the power consumption by 1/N²And (4) doubling.

It should be noted that the number of orders N in the stacked FBAR oscillator circuit is not as large as possible, and is determined according to specific criteria and a predetermined power supply voltage.

The present invention is not limited to the above preferred embodiments, and other various types of stacked low power consumption FBAR oscillator circuits can be obtained by anyone who can use the present invention, and all equivalent changes and modifications made in the claims of the present invention shall fall within the scope of the present invention.

Claims (6)

1. A stacked-based low-power FBAR oscillator circuit, comprising: sequentially connected: the power supply port, the current generation circuit unit and the stacked core oscillation circuit unit are arranged in the circuit; the current generation circuit unit is used for generating current irrelevant to input power supply voltage; the stacked core-based oscillation unit is used for providing negative resistance for compensating energy loss of a resonant tank.

2. The stacked-based low-power FBAR oscillator circuit of claim 1, wherein: the power supply port is used for providing 3.3V power supply voltage; the power supply voltage of the MOS tube in the circuit is 3.3V.

3. The stacked-based low-power FBAR oscillator circuit of claim 1, wherein: the current generation circuit unit comprises an MOS tubePM ₁、PM ₂、NM ₁、NM ₂、NM ₃、NM ₄、PM ₃And a control resistorR _bWherein, the MOS tubePM ₁、PM ₂AndPM ₃the grid electrodes are connected, and the drain electrodes are also connected; MOS tubePM ₁、PM ₂、NM ₁、NM ₂The source electrode and the grid electrode are both connected with a power supply port; MOS tubePM ₃The drain of the transistor is a current-generating output terminal; MOS tubeNM ₁AndNM ₂the drain electrodes of the MOS transistors are respectively connected with the MOS transistorsNM ₃AndNM ₄a source electrode of (a); MOS tubeNM ₃AndNM ₄are connected with the grid of the MOS transistorNM ₃Drain controlled resistance ofR _bThe grounding is carried out on the ground,NM ₄is directly grounded.

4. The stacked-based low-power FBAR oscillator circuit of claim 1, wherein: the stacked core-based oscillation circuit unit comprises a pi-type network-form band-pass filter and an N-order inverter; the N-order inverters are N inverters connected in parallel.

5. The stacked-based low-power consumption FBAR oscillator circuit of claim 4, wherein: each order inverter in the N order inverters comprises a feedback resistorR _BThe input and output voltages of each stage of inverter are equal, and the output end and the input end of each stage of inverter are respectively connected with a coupling capacitorC _CGAndC _CDused for blocking.

6. The stacked-based low-power consumption FBAR oscillator circuit of claim 4, wherein: the bandpass filter in the form of a pi network comprises: load capacitance C₁C2, FBAR resonator;

feedback resistance of each orderR _BBoth ends of the first-order inverter are respectively connected with the input end and the output end of the first-order inverter, and the input end and the output end of each-order inverter are respectively connected with the coupling capacitorC _DAnd a coupling capacitorC _GConnecting; two ends of the FBAR resonator are respectively connected with the coupling capacitorsC _CGAndC _CDconnected and respectively passed through a load capacitorC ₁AndC ₂grounding;

and a generated current output end of the current generating circuit unit is connected with a source electrode of a PMOS tube used as an input end in the Nth-order phase inverter.

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