CN214705959U - Reversed polarity chip with grid line ohmic contact structure - Google Patents

Abstract

The utility model relates to a reverse polarity chip especially relates to a take reverse polarity chip of grid line ohmic contact structure. In the reversed polarity chip with the grid line ohmic contact structure, an N-GaAs layer is etched to form grid lines with intervals in a staggered mode and distributed on the whole N-AlGaInP layer. The GaAs layer is made into a grid line structure by the reverse polarity chip, so that the coverage area of the GaAs layer is effectively reduced, and the absorption of the GaAs layer to the emitted light of the active region is weakened; the thickness of the grid line directly connected with the N-face electrode is thicker, so that the contact area is increased, and the ohmic contact between the metal electrode and the epitaxial layer is realized; grid lines are distributed on the whole N-AlGaInP layer in a staggered mode, so that current can be effectively diffused to the whole chip, and the brightness of the chip is improved.

Description

Reversed polarity chip with grid line ohmic contact structure

Technical Field

The utility model relates to a reverse polarity chip especially relates to a take reverse polarity chip of grid line ohmic contact structure.

Background

The LED has the advantages of high luminous efficiency, low energy consumption, long service life, high environmental protection and the like, has become an indispensable photoelectric component in daily life, and is widely applied to the field of high-efficiency solid-state lighting, such as a digital tube, a display screen, a backlight source, an automobile lamp, a traffic signal lamp, landscape lighting and the like.

Currently, the LED has low external quantum efficiency due to low light extraction efficiency, so the main problem of LED is focused on how to extract light from the inside of the semiconductor material. GaAs is a light absorbing material by which light emitted from the active region can be absorbed, and is a major factor limiting the light extraction efficiency of LEDs. In order to eliminate the absorption of light by the GaAs substrate, the silicon substrate is used as a permanent supporting substrate for the chip by a substrate transfer technique instead of the GaAs substrate, and a reverse polarity chip is manufactured. When the epitaxial structure of the reverse polarity chip is grown, AlGaInP with high doping concentration is difficult to grow, and a layer of GaAs with high doping concentration needs to be grown on the AlGaInP in order to ensure that the epitaxial layer and the metal electrode realize ohmic contact. Although the high doping concentration GaAs realizes ohmic contact between the epitaxial layer and the metal electrode, the high doping concentration GaAs absorbs light emitted by the active region, and the light emitting efficiency of the chip is influenced. The common processing method is to remove all GaAs except the metal electrode region, and this processing method can concentrate the current in the region under the electrode, and the light emitted from the active region under the electrode region is blocked by the electrode and cannot be emitted, thereby reducing the light emitting efficiency of the chip.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defects of the prior art, the reversed polarity chip with the grid line ohmic contact structure is provided, the GaAs layer with high doping concentration is made into the grid line structure through wet etching, the GaAs layer of the grid line structure ensures that ohmic contact is realized, meanwhile, the absorption of light emitted by an active region is reduced, and in addition, the current in the region under the electrode can be effectively diffused to the whole chip.

The technical scheme of the utility model is that:

a reversed polarity chip with a grid line ohmic contact structure comprises a P-face electrode, a permanent silicon substrate, a first metal layer, a second metal layer, a dielectric film layer, a P-GaP layer, a P-AlInP layer, an MQW active region, an N-AlInP layer, an N-AlGaInP layer, an N-GaAs layer and an N-face electrode from bottom to top, wherein the N-GaAs layer is etched into grid lines with intervals, the grid lines are directly connected with each other or indirectly connected with each other through the grid lines positioned between the grid lines, the grid lines are distributed on the N-AlGaInP layer in a staggered mode, the N-GaAs layer is provided with the N-face electrode, and the thickness of the grid lines directly connected with the N-face electrode is larger than that of the grid lines not directly connected with the N-face electrode.

Further, the thickness of the grid line directly connected with the N-face electrode is 5-8 μm, and the thickness of the grid line not directly connected with the N-face electrode is 2-4 μm.

Further, the doping concentration of the N-AlGaInP layer is 2E18/cm3, and the part of the surface without GaAs coverage is coarsened.

Further, the dielectric film layer is SiO₂SiN or MgF₂In one, a circle of round holes with the diameter of 5-10 μm are uniformly distributed around the dielectric film layer, and the round holes are filled with the second metal layer.

Furthermore, the P-surface electrode and the N-surface electrode are composed of one or more of Au, Pt, Ti, Al, AuGe and AuBe.

Further, the first metal layer is composed of Ti, Pt and Au, and the second metal layer is composed of Au and AuZn.

The utility model has the advantages that: the GaAs layer is made into a grid line structure by the reverse polarity chip, so that the coverage area of the GaAs layer is effectively reduced, and the absorption of the GaAs layer to the emitted light of the active region is weakened; the thickness of the grid line directly connected with the N-face electrode is thicker, so that the contact area is increased, and the ohmic contact between the metal electrode and the epitaxial layer is realized; grid lines are distributed on the whole N-AlGaInP layer in a staggered mode, so that current can be effectively diffused to the whole chip, and the brightness of the chip is improved.

Drawings

Fig. 1 is a schematic structural diagram of a reverse polarity chip in this embodiment.

Fig. 2 is a schematic structural diagram of a gate line according to an embodiment.

Fig. 3 is a schematic structural diagram of a second gate line according to an embodiment.

Fig. 4 is a schematic structural diagram of a triple gate line in the embodiment.

Wherein the figures include the following reference numerals: 1. a P-side electrode; 2. a permanent silicon substrate; 3. a first metal layer; 4. a second metal layer; 5. a dielectric film layer; 6. a P-GaP layer; 7. a P-AlInP layer; 8. an MQW active region; 9. an N-AlInP layer; 10. an N-AlGaInP layer; 11. a N-GaAs layer; 12. and an N-face electrode.

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which currently preferred embodiments of the invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for completeness and fully convey the scope of the invention to the skilled person.

Example one

As shown in FIG. 2, the reversed polarity chip with the gate line ohmic contact structure comprises a P-face electrode 1, a permanent silicon substrate 2, a first metal layer 3, a second metal layer 4, a dielectric film layer 5, a P-GaP layer 6, a P-AlInP layer 7, a MQW active region 8, an N-AlInP layer 9, an N-AlGaInP layer 10, an N-GaAs layer 11 and an N-face electrode 12 from bottom to top, wherein the N-GaAs layer 11 is etched into gate lines with intervals, and the gate lines comprise four connected gate lines, three of which are vertical lines, the middle vertical line is 5-8 μm in width, the vertical lines on two sides are 2-4 μm in width, the other one is a transverse line, and the transverse line is 5-8 μm in width.

Further, the N-AlGaInP layer 10 has a doping concentration of 2E18/cm3, and the portion of the surface not covered with GaAs is roughened.

Further, the dielectric film layer 5 is SiO₂SiN or MgF₂In one of the above, a circle of circular holes with a diameter of 5-10 μm are uniformly distributed around the dielectric film layer 5, and the circular holes are filled with the second metal layer 4.

Further, the P-side electrode 1 and the N-side electrode 12 are composed of one or more of Au, Pt, Ti, Al, AuGe, and AuBe.

Further, the first metal layer 3 is composed of Ti, Pt, Au, and the second metal layer 4 is composed of Au, AuZn.

The GaAs layer is made into a grid line structure by the reverse polarity chip, so that the coverage area of the GaAs layer is effectively reduced, and the absorption of the GaAs layer to the emitted light of the active region is weakened; the two wider grid lines are connected with the metal electrode (the N-surface electrode 12), so that ohmic contact between the metal electrode and the epitaxial layer is realized; the four connected grid lines can effectively diffuse the current to the whole chip, and the brightness of the chip is improved.

The embodiment also provides a manufacturing method of a reverse polarity chip with the gate line ohmic contact structure, which comprises the following steps:

1. providing an epitaxial wafer on which an epitaxial layer grows on a GaAs substrate;

2. depositing a layer of SiO2 dielectric film on one surface of the epitaxial wafer, which is far away from the GaAs substrate, and manufacturing a circle of holes with the diameter of 6 mu m on the dielectric film by wet etching;

3. evaporating a second metal layer Au-AuZn-Au on the dielectric film, wherein the second metal layer can fill the holes in the dielectric film;

4. providing a permanent silicon substrate, and evaporating a first metal layer Ti-Pt-Au on the silicon substrate;

5. aligning the GaAs substrate with the silicon substrate, enabling the first metal layer to be in close contact with the second metal layer, and bonding the two metal layers under the conditions of high temperature and high pressure;

6. soaking the whole wafer into a corrosive liquid, removing the GaAs substrate and exposing the highly doped N-GaAs layer;

7. spin-coating a positive photoresist on the N-GaAs layer, manufacturing a mask protection pattern of the grid line, removing the N-GaAs of the mask protection pattern by using a mixed solution of phosphoric acid and hydrogen peroxide, and removing the mask protection pattern by using a degumming solution to obtain the N-GaAs layer of the grid line structure;

8. spin-coating negative photoresist, manufacturing an N-surface electrode mask pattern, evaporating an N-surface electrode material, and stripping a metal material outside an electrode area by using a lift-off process to obtain an N-surface electrode;

9. spin-coating a positive photoresist, manufacturing a mask protection pattern to cover the N-GaAs layer of the N-face electrode and the grid line structure, and roughening the N-AlInP layer by using roughening liquid to change the N-GaAs layer into grid line N-GaAs layers with intervals;

10. grinding one surface of the silicon substrate, which is far away from the epitaxial layer, to a required thickness, carrying out organic cleaning on the mask surface, and evaporating a P-surface electrode material;

11. the wafer is divided into individual core grains by means of laser cutting and splitting.

Example two

As shown in fig. 3, the difference from the first embodiment is that the gate lines include five connected gate lines, four of which are vertical lines, two middle vertical lines have a width of 5-8 μm, two vertical lines on two sides have a width of 2-4 μm, the other vertical line is a horizontal line, and the horizontal line has a width of 5-8 μm.

EXAMPLE III

As shown in fig. 4, the difference from the first embodiment is that the gate lines include four connected gate lines, two of which are broken lines, the width of the broken line is 5-8 μm, and the width of the vertical line on both sides is 2-4 μm.

The above-mentioned embodiments only represent the preferred embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several changes, modifications and substitutions can be made, which are all within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims (5)

1. The utility model provides a take grid line ohmic contact structure's reverse polarity chip, includes P face electrode, permanent silicon substrate, first metal level, second metal level, dielectric film layer, P-GaP layer, P-AlInP layer, MQW active area, N-AlInP layer, N-AlGaInP layer, N-GaAs layer and N face electrode from the bottom up, its characterized in that:

the N-GaAs layer is etched to form grid lines with intervals, the grid lines are directly connected with each other or indirectly connected with each other through the grid lines positioned between the grid lines, the grid lines are distributed on the whole N-AlGaInP layer in a staggered mode, the N-face electrode is arranged on the N-GaAs layer, and the thickness of the grid lines directly connected with the N-face electrode is larger than that of the grid lines not directly connected with the N-face electrode.

2. The reverse polarity chip with the gate line ohmic contact structure of claim 1, wherein:

the thickness of the grid line directly connected with the N-face electrode is 5-8 μm, and the thickness of the grid line not directly connected with the N-face electrode is 2-4 μm.

3. The reverse polarity chip with the gate line ohmic contact structure of claim 1, wherein:

the part of the surface of the N-AlGaInP layer, which is not covered by GaAs, is roughened.

4. The reverse polarity chip with the gate line ohmic contact structure of claim 1, wherein:

the dielectric film layer is SiO₂SiN or MgF₂In one, a circle of round holes with the diameter of 5-10 μm are uniformly distributed around the dielectric film layer, and the round holes are filled with the second metal layer.

5. The reverse polarity chip with the gate line ohmic contact structure of claim 1, wherein:

the first metal layer is composed of Ti, Pt and Au, and the second metal layer is composed of Au and AuZn.

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