CN214627465U - Component carrier element and component carrier comprising the component carrier element - Google Patents

Abstract

The utility model provides a part holds carrier component and holds carrier including this part holds carrier component's part. A component carrier element (100), characterized in that the component carrier element (100) comprises: i) a stack (110) comprising at least one electrically insulating layer structure (102) and/or at least one electrically conductive layer structure (104); and ii) an electrically insulating resin layer structure (106) on top of the stack (110). The surface of the electrical insulation resin layer structure (106) is plasma-treated so that the surface of the electrical insulation resin layer structure (106) has high wettability with water at a contact angle of 70 DEG or less.

Description

Component carrier element and component carrier comprising the component carrier element

Technical Field

The utility model relates to a part holds carrier element and holds carrier including this part holds carrier element's part.

Background

Against the background of the growing product functionality of component carriers equipped with one or more electronic components and the increasing miniaturization of such components and the increasing number of components to be mounted on component carriers such as printed circuit boards, increasingly powerful array-like components or packages with several components are used, which have a plurality of contact portions or connection portions, the spacing between which is increasingly smaller. The removal of heat generated by these components and the component carrier itself during operation becomes an increasing problem. At the same time, the component carrier should have mechanical robustness and electrical reliability in order to be operable even under severe conditions.

In particular, it remains a challenge to provide a layer stack with a resin layer surface allowing high quality adhesion to further layers, in particular solder resist layers or copper layers.

Fig. 2 shows an example of the manufacture of a component carrier. A plate 150 comprising a plurality of component carriers is cut into a plurality of component carriers 101 by a dicing tool 140. Indicated by black bars is the interface between the outermost resin layer and the solder resist layer. Providing effective adhesion between the resin layer and the solder resist layer is often a challenge. The dicing tool 140 is pushed through the board and mechanical forces may delaminate ("peel") the solder resist layer from the resin layer (due to poor adhesion and bonding between the layers).

Fig. 4 shows a prior art example of the interface between the resin layer 206 and the solder resist layer 208 after the manufacturing process shown in fig. 2. It can be clearly seen that the solder resist layer 208 has been delaminated from the resin layer 206.

It may be necessary to effectively attach/bond a further layer, such as a solder resist layer or an electrically conductive layer, to the outermost resin layer of the component carrier element to provide the component carrier.

SUMMERY OF THE UTILITY MODEL

According to an exemplary embodiment of the present invention, a component carrier element is provided, the component carrier element comprising: i) a stack comprising at least one electrically insulating layer structure and/or at least one electrically conductive layer structure; and ii) an electrically insulating resin layer structure arranged on (the top of) the stack (e.g. forming the outermost layer of the stack). The surface of the electrical insulation resin layer structure is plasma-treated so that the surface of the electrical insulation resin layer structure has a high wettability that water defines a contact angle (i.e., surface energy measurement) of 70 ° or less.

According to another exemplary embodiment of the present invention, there is provided a component carrier, comprising: i) the component carrier element as described above; and ii) a surface modification layer (in particular a solder resist) arranged on the electrically insulating resin layer structure.

According to another exemplary embodiment of the present invention, there is provided a component carrier, comprising: i) the component carrier element as described above; and ii) an electrically conductive layer disposed on the electrically insulating resin layer structure.

According to another exemplary embodiment of the invention, a method of manufacturing a component carrier element is provided, the method comprising: i) providing a stack comprising at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, wherein an electrically insulating resin layer structure is arranged on the stack; and ii) subjecting the surface of the electrically insulating resin layer structure to a plasma treatment (in particular O)₂Or N₂Plasma treatment) so that the surface of the electrically insulating resin layer structure particularly has high wettability with water at a contact angle of 70 ° or less.

In the context of this document, the term "component carrier" may particularly denote any support structure capable of accommodating one or more components thereon and/or therein to provide mechanical support and/or electrical connectivity. In other words, the component carrier may be configured as a mechanical and/or electronic carrier for the component. In particular, the component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate, and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board, which mixes different types of the above-mentioned types of component carriers.

In the context of this document, the term "component carrier element" may particularly denote a preform of a component carrier (or a semi-finished product) as described above. For example, the component carrier element may be a layer laminate having an outermost resin layer. In a further step, a solder resist layer or a copper layer may be attached to the resin layer to provide the final component carrier (product).

In the context of this document, the term "plasma treatment" may particularly refer to a surface treatment or cleaning that removes residues, impurities and/or contaminants from a surface (e.g. the surface of a resin layer) by applying a plasma (e.g. a high energy plasma or a Dielectric Barrier Discharge (DBD) plasma). The plasma may be generated from a gas such as argon, oxygen, hydrogen, nitrogen, or mixtures thereof (e.g., by using a high frequency voltage). Plasma treatment can destroy the organic bonds of surface contaminants, particularly high molecular weight contaminants (e.g., C-H, C-C, C ═ C, C-O and C-N). Alternatively or additionally, oxygen species (e.g., O) may be generated in the plasma²⁺、O^2-、O₃、O、O⁺、O^-Ionized ozone, metastable excited oxygen, and free electrons). These species may react with organic contaminants to form H₂O、CO、CO₂And lower molecular weight hydrocarbons.

According to an exemplary embodiment, the invention is based on the idea that when plasma treating the surface of an electrically insulating resin layer structure, a component carrier element can be provided having an outermost resin layer structure which can be effectively attached to a further layer, such as a surface finish (e.g. solder resist) layer or a copper layer (thus forming the final component carrier). In particular, the surface is plasma treated such that it has a high wettability (low surface tension) and is in particular hydrophilic. The high wettability may be further described by a contact angle determined by water of 70 ° or less (particularly 60 ° or less, more particularly 50 ° or less, more particularly 40 ° or less, more particularly 30 ° or less). The high wettability can significantly improve the adhesive bonding between the resin layer and the further layer. In the case where the further layer is a solder resist layer (e.g. epoxy), the plasma treated surface may improve the epoxy bonding. Plasma treatment may further provide high compatibility between materials.

In the following, further exemplary embodiments of the method and component carrier will be explained.

In one embodiment, the water defines a contact angle of 20 ° or less. This may provide the advantage that the wettability and thus the quality of the attachment and bonding is very high. In particular, the contact angle is 10 ° or less, more particularly 5 ° or less, more particularly 3 ° or less.

In one embodiment, the surface of the electrically insulating resin layer structure is treated by a non-reactive and/or polar plasma. This may provide the following advantages: substantially no undesired chemical reactions occur on the surface and/or the surface is rendered hydrophilic (due to the polar treatment).

In one embodiment, the surface of the electrically insulating resin layer structure is through O₂(or N)₂) Plasma treatment. The inventors have surprisingly found that O₂Plasma treatment may be particularly effective for current applications. In particular, O₂The plasma treatment provides a polar treatment (see above).

In one embodiment, the surface of the plasma treated electrically insulating resin layer structure includes chemical functional groups containing oxygen. In this way, the surface is rendered hydrophilic, thereby further improving the quality of the attachment. Additionally or alternatively, the surface of the plasma treated electrically insulating resin layer structure comprises chemical functional groups comprising nitrogen.

In one embodiment, the surface of the electrically insulating resin layer structure comprises a microstructured polarity. This may improve the chemical reaction with further layers, such as solder resist layers.

In one embodiment, the surface modification comprises a solder resist comprising at least one of an epoxy resin, an acrylic resin, a Hitachi resin.

In one embodiment, the electrically insulating resin layer structure includes at least one of a reinforced or non-reinforced resin, Ajinomoto Build-up Film (ABF) (e.g., GY16B), an epoxy resin, a bismaleimide-triazine resin, FR-4, FR-5, cyanate ester, polyphenylene (polyphenylene) derivative, prepreg material, polyimide, polyamide, liquid crystal polymer, and epoxy based laminate Film. In one example, the resin layer includes ABF and improves surface wettability to provide better surface conditions for epoxy (solder resist) chemical reaction and physical bonding, thereby improving material compatibility.

In one embodiment, the attachment at the interface between the surface modification layer (e.g., solder resist) and the electrically insulating resin layer structure meets an IPC (printed circuit society) cross-cut test criterion of 2 or better (specifically 1 or better, more specifically 0). The cross cut test criteria ranged from 0 to 5, provided by IPC as a test criteria for ink adhesion. This test is described in the standard ISO-2409(2013E) "paint and varnish cross-cut test" and defines the cross-cut test standard. Said documents are incorporated herein by reference. Levels 0, 1 and 2 are acceptable criteria, while levels 3,4 and 5 are unacceptable (rejected). The inventors have surprisingly found that this cross-cut test can be effectively used to assess the quality of the adhesion/bonding at the interface of the resin layer and the further layer with respect to the component carrier.

In one embodiment, the peel strength at the interface between the electrically conductive layer and the electrically insulating resin layer structure is 0.45N/mm or more, particularly 0.5N/mm or more, more particularly 0.525N/mm or more. The term "peel strength" may refer to the ability of a material to resist a force that pulls it apart by separating a flexible surface from a rigid surface or another flexible surface. Peel strength can be measured in N/mm and can be used as a quality criterion for adhesion between the resin layer and the electrically conductive layer (e.g., copper). The inventors have surprisingly found that the plasma treatment and thus the high wettability also increases the adhesion between the resin and the copper.

In this respect, it should be noted that high surface roughness is generally required to enable adhesion between the resin and the copper. However, according to the described invention, the resin surface may instead have a low surface roughness and a high wettability.

In one embodiment, a desmear treatment of the surface of the electrically insulating resin layer structure is performed prior to the plasma treatment. In one example, the surface roughness (Ra value) after the desmear process may be in the range of 140nm-240 nm.

In one embodiment, the component carrier is shaped as a plate-like piece. This contributes to a compact design, wherein the component carrier still provides a large basis for mounting components thereon. Further, in particular, a bare die is an example of an embedded electronic component, and can be easily embedded in a thin plate-like member such as a printed circuit board due to its small thickness.

In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate, in particular an IC substrate, and an interposer.

In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures (e.g. by applying pressure and/or by providing thermal energy). As a preferred material for PCB technology, the electrically conductive layer structure is made of copper, while the electrically insulating layer structure may comprise resin and/or glass fibres, so-called prepreg or FR4 material. The various electrically conductive layer structures may be connected to each other in a desired manner by forming holes through the laminate, for example by laser drilling or mechanical drilling, and by filling them partially or completely with an electrically conductive material, in particular copper, thereby forming vias or any other through-hole connections. Filled vias either connect the entire stack (via connections extending through multiple layers or the entire stack), filled vias or connect at least two electrically conductive layers (called vias). Similarly, optical interconnects may be formed through the layers of the stack to receive an electro-optical circuit board (EOCB). In addition to one or more components that may be embedded in a printed circuit board, printed circuit boards are typically configured for receiving one or more components on one or both of the opposing surfaces of a plate-like printed circuit board. They may be attached to the respective major surfaces by welding. The dielectric portion of the PCB may be composed of a resin with reinforcing fibers (e.g., glass fibers).

In the context of the present application, the term "substrate" may particularly denote a small component carrier. The substrate may be a relatively small component carrier with respect to the PCB, on which one or more components may be mounted, and may serve as a connection medium between the chip(s) and the further PCB. For example, the substrate may have substantially the same size as the components, in particular electronic components, to be mounted thereon (e.g. in the case of Chip Scale Packages (CSP)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks and a component carrier comparable to a Printed Circuit Board (PCB), but with a comparatively high density of laterally and/or vertically arranged connections. The transverse connections are, for example, conductive paths, while the vertical connections may be, for example, boreholes. These lateral and/or vertical connections are arranged within the substrate and may be used to provide electrical, thermal and/or mechanical connections of a packaged or unpackaged component (e.g., a bare die), particularly an IC chip, to a printed circuit board or an intermediate printed circuit board. Thus, the term "substrate" also includes "IC substrate". The dielectric part of the substrate may be composed of a resin with reinforcing particles, such as reinforcing spheres, in particular glass spheres.

The substrate or interposer may comprise or consist of at least one layer of: at least one layer of glass, silicon (Si) and/or a photoimageable or dryable organic material, such as an epoxy-based build-up material (e.g. an epoxy-based build-up film) or a polymer compound (which may or may not contain photosensitive and/or thermosensitive molecules), such as polyimide or polybenzoxazole.

In one embodiment, the at least one electrically insulating layer structure comprises a resin or polymer, such as at least one of epoxy, cyanate ester, benzocyclobutene, bismaleimide-triazine, polyphenylene derivatives (e.g. based on polyphenylene ether (PPE), Polyimide (PI), Polyamide (PA), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and/or combinations thereof, reinforced structures, such as made of glass (multiple layer glass), such as mesh, fiber, sphere or other types of filler particles, may also be used to form composites, combinations of semi-cured resins and reinforcing agents, such as fibers impregnated with the above resins, are referred to as prepregs, these prepregs are generally named for their properties, such as FR4 or FR5, which names describe their flame retardant properties, although prepregs are generally preferred for rigid PCBs, especially FR4, but other materials, especially epoxy based laminates (e.g. laminated films) or photoimageable dielectric materials may be used. For high frequency applications, high frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and/or cyanate ester resins may be preferred. In addition to these polymers, low temperature co-fired ceramics (LTCC) or other low, ultra-low, or ultra-low DK materials can also be applied as electrically insulating structures in component carriers.

In one embodiment, the at least one electrically conductive layer structure (e.g., additional layer) comprises at least one of copper, aluminum, nickel, silver, gold, palladium, tungsten, and magnesium. Although copper is generally preferred, other materials or coated versions thereof are possible, in particular coated with a superconducting material or a conductive polymer, such as graphene or poly (3, 4-ethylenedioxythiophene) (PEDOT), respectively.

The at least one component may be embedded in the component carrier and/or may be surface mounted on the component carrier. Such components may be selected from: a non-electrically conductive inlay, an electrically conductive inlay (e.g. a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (e.g. a heat pipe), a light guiding element (e.g. a light guide or light conductor connection), an electronic component or a combination thereof. The inlay may be, for example, a metal block with or without a coating of insulating material (IMS inlay), which may be embedded or surface mounted to facilitate heat dissipation. Suitable materials are defined in terms of their thermal conductivity, which should be at least 2W/mK. Such materials are generally based on, but not limited to, metals, metal oxides and/or ceramics, such as copper, alumina (Al)₂O₃) Or aluminum nitride (AlN). Other geometries with increased surface area are also often used in order to increase the heat exchange capacity. Furthermore, the component may be an active electronic component (implementing at least one pn junction), a passive electronic component (such as a resistor, inductor or capacitor), an electronic chip, a memoryDevices (e.g., DRAM or other data storage), filters, integrated circuits (e.g., Field Programmable Gate Arrays (FPGA), Programmable Array Logic (PAL), Generic Array Logic (GAL), and Complex Programmable Logic Device (CPLD)), signal processing components, power management components (e.g., Field Effect Transistors (FET), Metal Oxide Semiconductor Field Effect Transistors (MOSFET), Complementary Metal Oxide Semiconductor (CMOS), Junction Field Effect Transistors (JFET), or Insulated Gate Field Effect Transistors (IGFET)), all based on semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga)₂O₃) Indium gallium arsenide (InGaAs), and/or any other suitable inorganic compound), optoelectronic interface elements, light emitting diodes, opto-couplers, voltage converters (e.g., DC/DC converters or AC/DC converters), cryptographic components, transmitters and/or receivers, electromechanical converters, sensors, actuators, micro-electromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components may also be embedded in the component carrier. For example, a magnetic element may be used as the component. Such magnetic elements may be permanent magnetic elements (e.g. ferromagnetic elements, antiferromagnetic elements, multiferroic elements or ferrimagnetic elements, such as ferrite cores) or may be paramagnetic elements. However, the component may also be an IC substrate, interposer, or other component carrier, for example in a board-in-board (midplane) configuration. The component may be surface mounted on the component carrier and/or may be embedded within it. In addition, other components may also be used as components, particularly those that generate and emit electromagnetic radiation and/or are sensitive to electromagnetic radiation propagating from the environment.

In one embodiment, the component carrier is a laminate type component carrier. In such embodiments, the component carrier is a multi-layered structure of compounds that are stacked and joined together by the application of pressure and/or heat.

After processing the inner layer structure of the component carrier, one or both of the opposite major surfaces of the processed layer structure may be covered (in particular by lamination) symmetrically or asymmetrically with one or more further electrically insulating layer structures and/or electrically conductive layer structures. In other words, lamination may continue until the desired number of layers is obtained.

After completion of the formation of the stack of the electrically insulating layer structure and the electrically conductive layer structure, the obtained layer structure or component carrier may be subjected to a surface treatment.

In particular, in terms of surface treatment, a surface modification, such as an electrically insulating solder resist, may be applied to one or both of the opposite main surfaces of the layer stack or the component carrier. For example, such a solder resist may be formed over the entire major surface and subsequently patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to the electronic periphery. The surface portion of the component carrier, which remains covered with the solder resist, can be effectively protected from oxidation or corrosion, in particular the surface portion comprising copper.

In the case of a surface treatment, a surface modification may also be selectively applied to exposed electrically conductive surface portions of the component carrier. Such a surface modification may be an electrically conductive covering material on exposed electrically conductive layer structures (e.g. pads, conductive tracks, etc., in particular comprising or consisting of copper) on the surface of the component carrier. If such exposed electrically conductive layer structures are not protected, the exposed electrically conductive component carrier material (in particular copper) may be oxidized, thereby reducing the reliability of the component carrier. The surface finish may then for example be formed as an interface between the surface mounted component and the component carrier. The surface modification has the function of protecting the exposed electrically conductive layer structure (in particular the copper circuit) and enabling a bonding process with one or more components (for example by soldering). Examples of suitable materials for surface modification are Organic Solderability Preservative (OSP), chemical nickel immersion gold (ENIG), chemical nickel immersion palladium immersion gold (ENIPIG), gold (in particular hard gold), chemical tin, nickel-gold, nickel-palladium, etc.

The aspects defined above and further aspects of the invention are apparent from the exemplary embodiments to be described hereinafter and are explained with reference to these exemplary embodiments.

Drawings

Fig. 1 shows a component carrier with a component carrier element according to an exemplary embodiment of the present invention.

Fig. 2 shows a production process for a component carrier.

Fig. 3 shows a layer interface according to an exemplary embodiment of the present invention.

Fig. 4 shows a layer interface according to the prior art.

Fig. 5 shows a surface energy measurement of a surface of a component carrier element according to an exemplary embodiment of the present invention.

Fig. 6 shows surface energy measurement of a surface of a resin layer according to the prior art.

Fig. 7 illustrates the variability of contact angles including exemplary embodiments of the present invention.

Fig. 8 illustrates the variability of CC-attachment including exemplary embodiments of the present invention.

Fig. 9 illustrates an analysis of peel strength including an exemplary embodiment of the present invention.

Detailed Description

The illustration in the drawings is schematically. In different drawings, similar or identical elements are provided with the same reference signs.

According to one exemplary embodiment, it is desirable to improve resin/additional layer (e.g., Solder Resist (SR)/ABF) interface bonding and adhesion and reduce delamination yield loss. It is proposed to add a new process pre-treatment (plasma) before lamination of the further layers (SR) to increase the adhesion and bonding and microstructure polarity. In the SR and ABF examples, this measure supports reactive bonding of epoxy and acrylic resins. Furthermore, the IPC defined ink cross-cut tape test criteria can be used to assess the quality of the final component carrier. In one particular example, the solder resist may include Hitachi SR-FA and the resin may include ABF material (GY 16B). The material may include a high filler content and a low coefficient of thermal expansion (such material may be particularly delaminated by external forces such as a dicing tool (blade cut))

According to an exemplary embodiment, the manufacturing of the component carrier comprises the steps of: process step notes, core initiation, inner layer build-up, ABF lamination, ABF curing, laser via drilling, PET film stripper, desmear, electroless copper plating, photolithography and pattern plating, SR promotion, SR adhesion promotion curing, plasma treatment, SR lamination, SR exposure, SR development, SR UV curing, SR post curing, further surface modification (or application before further surface modification to the plasma treatment), dicing.

Fig. 1 shows a component carrier 101 with a component carrier element 100 according to an exemplary embodiment of the present invention. The component carrier element 100 has a layer stack 110 comprising a plurality of electrically insulating layer structures 102 (e.g., core structures) and a plurality of electrically conductive layer structures 104. On top of the stack 110, as the outermost structure, there is arranged an electrically insulating resin layer structure 106. The surface of the electrical insulation resin layer structure 106 is plasma-treated so that the surface of the electrical insulation resin layer structure 106 has high wettability (the contact angle determined by water is 70 ° or less). On top of the plasma treated electrically insulating resin layer structure 106 (e.g. ABF) a solder resist layer 108 (e.g. epoxy) is laminated. The adhesion at the interface 109 between the solder resist layer 108 and the electrically insulating resin layer structure 106 is of high quality. For example, the quality criteria according to the IPC cross cut test are 0, 1 or 2.

Fig. 3 shows a microscopic image of the interface 109 between the solder resist layer 108 and the electrically insulating resin layer structure 106 as described in fig. 1. It can be seen that the attachment is of high quality and there is no delamination or peeling (compare the prior art example shown in fig. 4).

Fig. 5 shows surface energy measurements used to evaluate surface wettability. The surface of the electrically insulating resin layer structure 106 is plasma treated and has been tested with water. The resulting contact angle was 2.63 °.

Fig. 6 shows surface energy measurements for evaluating the surface wettability of the resin layer 206 according to the prior art. The surface of the resin layer 206 was not plasma treated and had been tested with water. The resulting contact angle was 115.73 °.

Fig. 7 shows the variability of the contact angle of the surface of the electrically insulating resin layer structure before and after plasma treatment (see fig. 5 above). It can be seen that the contact angle is about 115 ° (typically over 100 °) before plasma treatment (poor wetting), and about 2.5 ° (typically at least below 7.5 °) after plasma treatment (high wetting). The results show that the data distribution is small, indicating that the surface property change obtained is less than before treatment. Therefore, the reliability of the obtained surface is also increasing. By plasma treatment, more uniform surface properties of different production batches (different plates) can be achieved. The starting conditions before applying the surface modification can be adjusted to be within a narrow range. Therefore, the process stability (robustness) will also be improved.

Fig. 8 shows the variability of cross-cut (CC) test attachment of the electrically insulating resin layer structure with and without plasma treatment. It can be seen that in the case of plasma treatment the adhesion quality (according to CC-adhesion) is very high, i.e. values of 1 and 2, while the adhesion quality (according to CC-adhesion) is very poor, i.e. values of 3 to 5, as in the case of no plasma treatment.

Fig. 9 shows a Peel Strength (PS) analysis (N/mm) at the interface between the electrically insulating resin layer structure and the electrically conductive layer structure (e.g., copper layer) with and without plasma treatment. After plasma treatment, the overall peel strength increased by 0.03N/mm.

It should be noted that the term "comprising" does not exclude other elements or steps and the "a" or "an" does not exclude a plurality. Also elements described in association with different embodiments may be combined.

It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.

The embodiments of the present invention are not limited to the preferred embodiments shown in the drawings and described above. On the contrary, even in the case of fundamentally different embodiments, many variants of the solutions and principles shown according to the invention can be used.

Claims (10)

1. A component carrier element (100), characterized in that the component carrier element (100) comprises:

a stack (110) comprising at least one electrically insulating layer structure (102) and/or at least one electrically conductive layer structure (104); and

an electrically insulating resin layer structure (106), the electrically insulating resin layer structure (106) being arranged on the stack (110);

wherein a surface of the electrically insulating resin layer structure (106) is plasma-treated so that the surface of the electrically insulating resin layer structure (106) has a high wettability with water at a determined contact angle of 70 ° or less.

2. The component carrier element (100) according to claim 1, wherein the water determines a contact angle of 20 ° or less.

3. The component carrier element (100) according to claim 1, wherein the surface of the electrically insulating resin layer structure (106) is treated by a non-reactive and polar plasma.

4. The component carrier element (100) according to claim 3, wherein the surface of the electrically insulating resin layer structure (106) is O-passed₂Or N₂Plasma treatment.

5. The component carrier element (100) according to claim 1, wherein the surface of the electrically insulating resin layer structure (106) comprises a microstructured polarity.

6. The component carrier element (100) according to claim 1, wherein the electrically insulating resin layer structure (106) comprises one of a reinforced or non-reinforced resin, ajinomoto laminate film, epoxy resin, bismaleimide-triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivative, prepreg material, polyimide, polyamide, liquid crystal polymer, and epoxy laminate film.

7. A component carrier (101), characterized in that the component carrier (101) comprises:

the component carrier element (100) according to claim 1;

a surface modification layer (108) disposed on the electrically insulating resin layer structure (106).

8. The component carrier (101) according to claim 7, wherein the adhesion at the interface (109) between the surface modification layer (108) and the electrically insulating resin layer structure (106) meets a printed circuit society cross-cut test criterion of 2 or better.

9. A component carrier (101), characterized in that the component carrier (101) comprises:

the component carrier element (100) according to claim 1;

an electrically conductive layer disposed on the electrically insulating resin layer structure (106).

10. The component carrier (101) according to claim 9, wherein a peel strength at an interface (109) between the electrically conductive layer and the electrically insulating resin layer structure (106) is 0.45N/mm or higher.

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