CN214586871U - Communication adapter device - Google Patents
Communication adapter device Download PDFInfo
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- CN214586871U CN214586871U CN202120502470.3U CN202120502470U CN214586871U CN 214586871 U CN214586871 U CN 214586871U CN 202120502470 U CN202120502470 U CN 202120502470U CN 214586871 U CN214586871 U CN 214586871U
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Abstract
The embodiment of the application discloses a communication adaptation device. The device comprises: a power module to supply power to the device; a memory storing application data; the GPIO interface comprises a first pin and a second pin, wherein the first pin is connected with the power supply module through the switch unit, and the second pin is connected with the ground; the register is connected with the first pin of the GPIO interface and used for storing the level information of the GPIO interface; and the processor is connected with the register and the memory, and transmits the application data in the memory to a connected target chip through an output interface when the level of the register is low level.
Description
Technical Field
The present disclosure relates to the field of information processing, and more particularly, to a communication adaptation apparatus.
Background
The chip may support physical interfaces such as UART (Universal Asynchronous Receiver/Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), GPIO (General-purpose input/output), and the like. The PC end needs to be equipped with respective communication interface communication adapter devices to access the physical interfaces, which is inconvenient for application development, test and program downloading of the PC end.
In order to realize the access between the PC end and the chip, a communication interface communication adapter device can be configured, wherein the communication interface communication adapter device is mostly a combination of USB to RS232 or RS232 to I2C, and the like, which can not completely meet the access requirement of the chip common UART/I2C/SPI/GPIO multi-interface, and a plurality of communication interface communication adapter devices still need to be equipped in the test process. In addition, from the view of the offline download function, no communication adapter device with the offline download function is found in the market.
SUMMERY OF THE UTILITY MODEL
In order to solve any one of the above technical problems, an embodiment of the present application provides a communication adaptation apparatus.
To achieve the purpose of the embodiments of the present application, an embodiment of the present application provides a communication adaptation apparatus, including:
a power module to supply power to the device;
a memory storing application data;
the GPIO interface comprises a first pin and a second pin, wherein the first pin is connected with the power supply module through a switch unit, the second pin is connected with the ground, and the switch unit is used for controlling whether the first pin and the second pin are conducted or not;
the register is connected with the first pin of the GPIO interface and used for storing the level information of the GPIO interface;
and the processor is connected with the register and the memory, and transmits the application data in the memory to a connected target chip through an output interface when the level of the register is low level.
One of the above technical solutions has the following advantages or beneficial effects:
an off-line downloading mode is realized on the communication adapter device, the off-line downloading of codes/data separated from the upper computer is realized, and the use of occasions separated from the upper computer is facilitated.
Additional features and advantages of the embodiments of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the examples of the embodiments of the present application do not constitute a limitation of the embodiments of the present application.
Fig. 1 is a block diagram of a communication adapter provided in an embodiment of the present application;
fig. 2 is a flowchart illustrating an operation of an online download mode of a communication adapter according to an embodiment of the present application;
fig. 3 is a flowchart illustrating an off-line download mode of a communication adapter according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a software structure of an upper computer provided in the embodiment of the present application;
fig. 5 is a flowchart illustrating downloading of application data in an offline download mode according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, in the embodiments of the present application, features in the embodiments and the examples may be arbitrarily combined with each other without conflict.
Fig. 1 is a block diagram of a communication adapter according to an embodiment of the present application. As shown in fig. 1, the apparatus includes:
a power module to supply power to the device;
a memory storing application data;
the GPIO interface comprises a first pin and a second pin, wherein the first pin is connected with the power supply module through a switch unit, the second pin is connected with the ground, and the switch unit is used for controlling whether the first pin and the second pin are conducted or not;
the register is connected with the first pin of the GPIO interface and used for storing the level information of the GPIO interface;
and the processor is connected with the register and the memory, and transmits the application data in the memory to a connected target chip through an output interface when the level of the register is low level.
In one exemplary embodiment, the apparatus further comprises:
the downloading interface is connected with an upper computer, and the upper computer stores an application program;
and when the level of the register is high level, the processor acquires the application program from the calculation processing unit through the download interface and transmits the application program to the connected target chip through the input interface.
In the above exemplary embodiment, the communication adapter device has two operation modes, i.e., an online mode and an offline mode, wherein the operation mode is determined by the level state of the GPIO control pin.
When the GPIO control pin is at high level, the working mode of the communication adapter device is in an online mode, and the computing processing unit (such as a PC, a mobile device and the like) communicates with the target chip through a physical interface of the communication adapter device converting UART/I2C/SPI to complete the instruction interaction between the PC and the target chip; when the GPIO control pin is in a low level, the working mode of the communication adapter device is an off-line mode, the communication adapter device does not communicate with the calculation processing unit and only communicates with the target chip, namely, codes/data pre-stored in NorFlash can be downloaded to the target chip through a specified interface UART/I2C/SPI under the condition of being separated from the calculation processing unit.
The detection implementation mode of the working mode is as follows:
the left side pin and the right side pin of the GPIO control pin are respectively a high-level pin and a low-level pin, and can be changed through a jumper wire cap or a connecting wire, wherein the GPIO control pin is connected to the high-level pin and is a high level, and the GPIO control pin is connected to the low-level pin and is a low level.
Setting the GPIO control pin to be in an input state, judging a mode state by reading a value of a GPIO data register corresponding to the GPIO control pin by the processor, wherein the GPIO data register is 0 to indicate that the GPIO control pin is connected with a low level, namely an off-line mode; a GPIO data register of 1 indicates that the GPIO control pin is connected at a high level, i.e., in an on-line mode.
In an exemplary embodiment, when the level of the register is a low level, the processor acquires the operation data uploaded by the target chip from the target chip and processes the operation data.
The operation data may be response data generated after the target chip executes the instruction, and the processor may compare the response data with reference data stored in advance to evaluate a result of the target chip executing the instruction.
In an exemplary embodiment, the processor sends the operation data of the target chip to the computation processing unit through the download interface when the level of the register is a high level.
In an exemplary embodiment, the interface type of the output interface includes at least one of a serial peripheral interface SPI, an I2C interface, and a universal asynchronous receiver transmitter UART interface.
In the above exemplary embodiment, the communication adaptation apparatus is provided with a plurality of communication interfaces including:
the interface for communicating with the target chip can be UART, I2C, SPI and GPIO;
the interface for communicating with the upper computer can be a USB interface;
the communication adapter device can receive the instruction of the upper computer and interacts with the target chip through the SPI/I2C/UART/GPIO interface; or receiving the instruction packet data from a USB interface of the upper computer, extracting effective data after unpacking, communicating with an SPI/I2C/UART/GPIO interface of the target chip through a specified interface, packaging the response data and then sending the packaged response data to the upper computer through the USB interface.
In one exemplary embodiment, the download interface is a USB interface;
the power module, with the USB interface links to each other, includes:
the voltage conversion unit is used for converting the voltage provided by the USB interface into a first voltage required by the GPIO interface and a second voltage required by the processor;
and the voltage output unit is used for providing a first voltage for the GPIO interface and providing a second voltage for the processor.
Wherein, power module contains a power conversion chip for with the 5V power that USB provided, convert the required voltage of MCU and GPIO pin into respectively, supply MCU or GPIO pin again, thereby make communication adapter device need not to set up power supply unit, reduce the hardware cost.
In one exemplary embodiment, the apparatus further comprises:
the working indicator light is connected with the processor;
the processor sends a control signal for indicating completion, processing or failure of data transmission to the working indicator lamp so as to control the working state of the working indicator lamp.
And the application data is sent to the target chip through the SPI/I2C/UART interface, and meanwhile, whether the response of each instruction is consistent with the stored response packet or not is compared, so that corresponding prompt information can be written into the liquid crystal screen, and a corresponding indicator lamp is lightened. If all the instruction packets are successfully sent and the response packets are in accordance with each other, the downloading is successful, otherwise, the downloading is failed.
In one exemplary embodiment, the memory is a non-volatile memory NVM.
The following describes a communication adaptation apparatus provided in an embodiment of the present application:
a unified communication adapter device is adopted for a common UART/I2C/SPI/GPIO multi-interface of a chip, and an upper computer can access a UART/I2C/SPI/GPIO physical interface of a target chip through the communication adapter device to realize communication with the target chip.
Those skilled in the art can know that when data downloading is implemented, the corresponding software configuration needs to be preset, for example. The PC terminal is provided with a series of API functions related to the UART/I2C/SPI/GPIO interface of the target chip. The API is used for assisting the upper computer to establish communication with the target chip, and completing debugging, testing and the like of the target chip; and a function of downloading code or data to a target chip.
The workflow of the online mode is explained as follows:
when the working mode is the online mode, the communication adapter communicates with the USB interface of the upper computer, and the SPI/I2C/UART interface of the communication adapter communicates with the target chip through the API provided by the PC-side SDK, or the code/data (e.g., COS code) of the target chip is stored on the off-chip Nor Flash of the communication adapter, and the working flow is as shown in fig. 2.
When the working mode is the off-line mode, the communication adapter device is still powered by the USB (because the communication adapter device is not communicated with the upper computer in the off-line mode, an independent power supply with a USB interface can be used), codes/data (for example, COS codes) stored on the Nor Flash are read by key triggering, and the codes/data are downloaded to a target chip through the SPI/I2C/UART interface, and the states of downloading success or failure are indicated through the liquid crystal screen and the LED lamp. Meanwhile, LOG is downloaded off line and stored in NorFlash, and LOG can be read when the LOG is connected with an upper computer, and the working flow is shown in figure 3.
With regard to interface identification, automatic interface identification is supported, and the processor sends a command by polling three interfaces, takes the first interface capable of normal communication as a subsequent communication interface, and sends codes/data to be stored.
When the functions are realized, the upper computer SDK development kit provides a series of API functions for the communication between the upper computer and the communication adapter device, the user data is packaged according to a private protocol, sent to the communication adapter device through the USB and then converted into the operation of the SPI/I2C/UART/GPIO interface of the target chip.
As shown in fig. 4, the software structure is divided into 3 layers from top to bottom: the system comprises a user layer, a protocol layer and a drive layer, wherein the user layer provides an application of a host end to access an API of the communication adaptation device, and a user can realize the operation of the communication adaptation device through the API; the protocol layer is responsible for converting functions in the API into instructions for communicating with the communication adapter device and packaging the transmitted instruction data into packets or unpacking the received response data; the drive layer controls the USB interface of the host to communicate with the communication adapter device.
The COS code or data is downloaded into the target chip as an example:
the upper computer can call the API to realize the downloading of COS codes or data to the appointed physical interface of the target chip.
The online downloading mode is a traditional downloading mode, the upper computer calls an API of an online mode, the COS is downloaded, a bin file containing the COS is analyzed, bin file data are divided into instruction packets and issued to the communication adapter device through the USB interface, the bin file data are sent to a target chip through the SPI/I2C/UART interface by the communication adapter device, the upper computer informs the communication adapter device through the USB interface to start the SPI/I2C/UART to receive response data of the target chip and transmit the response data back to the PC end for analysis, and the whole downloading process is completed.
As shown in fig. 5, if the offline download mode is adopted, the upper computer calls the API in the offline mode, where the download COS is taken as an example, the instruction packet and the response packet related to the download COS are stored in NorFlash, and the write instruction and data are checked to ensure correct storage. When the communication adapter device is switched to an off-line mode, the instruction packet data stored in the Nor Flash is read through key triggering, the instruction packet data is sent to a target chip through an SPI/I2C/UART interface, meanwhile, whether the response of each instruction is consistent with the stored response packet or not is compared, corresponding prompt information is written into a liquid crystal screen, and a corresponding indicator lamp is lightened. If all the instruction packets are successfully sent and the response packets are in accordance with each other, the downloading is successful, otherwise, the downloading is failed.
The scheme provided by the embodiment of the application has the following advantages that:
the communication between the upper computer and the target chip is established by utilizing an input interface on the communication adapter device, and the access test requirement of a common UART/I2C/SPI/GPIO multi-interface of the chip is met;
the off-line downloading mode can be realized, namely, the codes/data are downloaded into NorFlash of the communication adapter device, and the codes/data can be downloaded to a designated interface of the target chip from the upper computer after the off-line mode is switched, so that the codes/data off-line downloading of the upper computer is realized, and the occasion of the off-line downloading of the codes/data from the upper computer is facilitated;
the LOG which can be downloaded off-line is stored in NorFlash and can be read after being connected with an upper computer, so that later maintenance is facilitated.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.
Claims (8)
1. A communication adaptation apparatus, comprising:
a power module to supply power to the device;
a memory storing application data;
the GPIO interface comprises a first pin and a second pin, wherein the first pin is connected with the power supply module through a switch unit, the second pin is connected with the ground, and the switch unit is used for controlling whether the first pin and the second pin are conducted or not;
the register is connected with the first pin of the GPIO interface and used for storing the level information of the GPIO interface;
and the processor is connected with the register and the memory, and transmits the application data in the memory to a connected target chip through an output interface when the level of the register is low level.
2. The apparatus of claim 1, wherein:
and the processor acquires the operation data uploaded by the target chip from the target chip and processes the operation data when the level of the register is low.
3. The apparatus of claim 1, further comprising:
the downloading interface is connected with an upper computer, and the upper computer stores an application program;
and when the level of the register is high level, the processor acquires the application program from the upper computer through the download interface and transmits the application program to the connected target chip through the input interface.
4. The apparatus of claim 3, wherein:
and the processor sends the operation data of the target chip to the upper computer through the download interface when the level of the register is high level.
5. The apparatus of claim 3, wherein:
the download interface is a USB interface;
the power module, with the USB interface links to each other, includes:
the voltage conversion unit is used for converting the voltage provided by the USB interface into a first voltage required by the GPIO interface and a second voltage required by the processor;
and the voltage output unit is used for providing a first voltage for the GPIO interface and providing a second voltage for the processor.
6. The apparatus of claim 1, further comprising:
the working indicator light is connected with the processor;
the processor sends a control signal for indicating completion, processing or failure of data transmission to the working indicator lamp so as to control the working state of the working indicator lamp.
7. The apparatus of claim 1, wherein the type of interface of the output interface comprises at least one of a Serial Peripheral Interface (SPI), an I2C interface, and a Universal Asynchronous Receiver Transmitter (UART) interface.
8. The apparatus according to claim 1, wherein the memory is a non-volatile memory (NVM).
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| CN202120502470.3U CN214586871U (en) | 2021-03-09 | 2021-03-09 | Communication adapter device |
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| CN202120502470.3U CN214586871U (en) | 2021-03-09 | 2021-03-09 | Communication adapter device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115033520A (en) * | 2022-07-11 | 2022-09-09 | 深圳市金科泰通信设备有限公司 | IIC data transmission method and device, single chip microcomputer equipment and storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115033520A (en) * | 2022-07-11 | 2022-09-09 | 深圳市金科泰通信设备有限公司 | IIC data transmission method and device, single chip microcomputer equipment and storage medium |
| CN115033520B (en) * | 2022-07-11 | 2023-08-08 | 深圳市金科泰通信设备有限公司 | IIC data transmission method and device, singlechip equipment and storage medium |
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