CN214428634U

CN214428634U - Semiconductor device with a plurality of transistors

Info

Publication number: CN214428634U
Application number: CN202120876498.3U
Authority: CN
Inventors: 颜逸飞
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-04-26
Filing date: 2021-04-26
Publication date: 2021-10-19
Anticipated expiration: 2031-04-26

Abstract

The utility model provides a semiconductor device, wherein a substrate is provided with a memory cell area, a peripheral circuit area and a junction area positioned between the memory cell area and the peripheral circuit area; the bit lines are positioned on the substrate and arranged at intervals along the first direction, and extend from the memory cell area to the interface area along the second direction; a plurality of dummy lines are located on the substrate in the interface region, one of the dummy lines is butted against an end of one of the bit lines and aligned in a second direction, and each of the dummy lines includes a first insulating layer and a second insulating layer stacked in sequence on the substrate. In the utility model, the transverse width of the bottom of the first insulating layer is larger than that of the top, the strength of the virtual line is enhanced by increasing the width of the bottom of the virtual line, the virtual line is prevented from lodging due to the larger height and width, and the performance and stability of the device are improved; in addition, because only the width of the bottom of the virtual line is increased, various parameters of the device cannot be influenced.

Description

Semiconductor device with a plurality of transistors

Technical Field

The utility model relates to the field of semiconductor technology, especially, relate to a semiconductor device.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. The memory is provided with a plurality of word line structures and bit line structures, wherein the word line structures are embedded in a substrate, the bit line structures are formed on the substrate and are electrically connected with corresponding memory units, the memory also comprises a capacitor structure, the capacitor structure is used for storing charges representing stored information, and the memory units can be electrically connected with the capacitor structure through a node contact structure, so that the storage function of each memory unit is realized.

The memory also comprises a memory cell area and a peripheral circuit area, wherein the memory cell area is used for forming memory cells of the memory, the peripheral circuit area is used for forming peripheral circuits of the memory, and a boundary area also exists at the boundary between the memory cell area and the peripheral circuits. At present, the ratio of the height to the width of the virtual line in the boundary area is large, and the virtual line is easy to fall down, so that the performance and the stability of the memory are reduced.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a semiconductor device for the height of solving the virtual line in the boundary region is bigger than the width, and easy lodging, and then the performance that leads to the device and the problem of stability decline.

In order to achieve the above object, the present invention provides a semiconductor device, including:

a substrate having a memory cell region, a peripheral circuit region, and a junction region between the memory cell region and the peripheral circuit region;

a plurality of bit lines which are positioned on the substrate and arranged at intervals along a first direction, and extend from the memory cell area to the junction area along a second direction;

and the plurality of virtual lines are positioned on the substrate of the interface area, one virtual line is butted with the end part of one bit line and is aligned along the second direction, each virtual line comprises a first insulating layer and a second insulating layer which are sequentially stacked on the substrate, and the transverse width of the bottom of the first insulating layer is greater than that of the top of the first insulating layer.

Optionally, the lateral width of the bottom of the first insulating layer is greater than twice the lateral width of the top.

Optionally, the lateral width of the first insulating layer gradually decreases from the bottom to the top.

Optionally, a cross section of the first insulating layer along the third direction is a trapezoid.

Optionally, the aspect ratio of the virtual line is greater than 10.

Optionally, the memory cell further includes a first sidewall and a second sidewall, the first sidewall covers the sidewall of the dummy line, and the second sidewall covers the sidewall of the bit line.

Each of the dummy lines further includes a third insulating layer, and the third insulating layer is located between the first insulating layer and the second insulating layer.

Optionally, a part of the thickness of the bottom of the first insulating layer of the dummy line extends laterally to connect with the bottom of the first insulating layer of the adjacent dummy line, so as to cover a part of the surface of the substrate in the interface region.

In the semiconductor device provided by the present invention, a substrate has a memory cell region, a peripheral circuit region, and a junction region between the memory cell region and the peripheral circuit region; the bit lines are positioned on the substrate and arranged at intervals along a first direction, and extend from the memory cell area to the junction area along a second direction; the plurality of dummy lines are located on the substrate of the interface area, one of the dummy lines is butted with an end of one of the bit lines and aligned along the second direction, and each of the dummy lines includes a first insulating layer and a second insulating layer stacked on the substrate in sequence. In the utility model, the transverse width of the bottom of the first insulating layer is larger than that of the top, the strength of the virtual line is enhanced by increasing the width of the bottom of the virtual line, the virtual line is prevented from lodging due to the larger height and width, and the performance and stability of the device are improved; in addition, because only the width of the bottom of the virtual line is increased, various parameters of the device cannot be influenced.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 2a to fig. 2k are schematic structural diagrams corresponding to a corresponding flow of a manufacturing method of a semiconductor device according to an embodiment of the present invention, in which fig. 2k is a top view of the semiconductor device according to an embodiment of the present invention, and fig. 2j is a cross-sectional view of the semiconductor device according to an aa direction and a bb direction in fig. 2k according to an embodiment of the present invention;

fig. 3 is a cross-sectional view of a semiconductor device along aa and bb directions according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram corresponding to a corresponding flow of a manufacturing method of a semiconductor device according to a third embodiment of the present invention;

fig. 5 is a cross-sectional view of a semiconductor device along aa and bb directions according to a third embodiment of the present invention;

wherein the reference numerals are:

100-a substrate; 100A-memory cell area; 100C-junction area; 201-a first layer of buffer material; 202-a first layer of conductive material; 202 a-a first conductive layer; 203-a second layer of conductive material; 203 a-a second conductive layer; 204-a layer of mask material; 204 a-a mask layer; 205-a second layer of buffer material; 206-a first layer of insulating material; 206a — a first insulating layer; 207-a second layer of insulating material; 207 a-second insulating layer; 207 b-a fourth insulating layer; 208 a-a third insulating layer; 208 b-a fifth insulating layer; 300-connecting contacts; 401 — a first opening; 402-a second opening;

BL-bit line; DL-virtual line; WL-word line; S/D-source/drain regions; d1-first direction; d2-second direction; d3-second direction; SP 1-first sidewall; SP 2-second sidewall; STI-trench isolation structure;

x1 — lateral width of the bottom of the first insulating layer;

x2 — lateral width of the bottom of the second insulating layer;

x3 — lateral width of bottom of second sub-opening;

x4 — lateral width of the top of the second sub-opening.

X5-lateral width of the virtual line;

h-the depth of the virtual line.

Detailed Description

The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

Fig. 2k is a top view of the semiconductor device provided in this embodiment, and fig. 2j is a cross-sectional view of fig. 2k along the aa direction and the bb direction. The semiconductor device is, for example, a Memory device such as a Dynamic Random Access Memory (DRAM) device, but not limited thereto.

As shown in fig. 2k and 2j, the semiconductor device includes a substrate 100, a plurality of word lines WL formed in the substrate 100, and a plurality of bit lines BL and a plurality of dummy lines DL formed on the substrate 100.

The substrate 100 is, for example, a silicon substrate (silicon substrate), a silicon containing substrate (silicon containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or the like.

The substrate 100 defines a memory cell region 100A, a peripheral circuit region (not shown), and an interface region 100C between the memory cell region 100A and the peripheral circuit region. A plurality of active regions AA may be further formed in the memory cell region 100A, for example, and the active regions AA may be used to form memory cells; the peripheral circuit region is located at one side of the memory cell region 100A, and is used for forming a peripheral circuit of the semiconductor device; the interface region 100C is located at the boundary between the memory cell region 100A and the peripheral circuit region, and the interface region 100C may be a region that buffers a difference between a structure formed in the memory cell region 100A and a structure formed in the peripheral circuit region, and similarly, the interface region 100C may also be a region for connecting the structure of the memory cell region 100A and the structure of the peripheral circuit region to each other.

As shown in fig. 2k and fig. 2j, in the present embodiment, the peripheral circuit region is located at the right side of the memory cell region 100A. However, in other embodiments, the peripheral circuit region may be disposed in other regions.

Further, a trench isolation structure STI is formed in the substrate 100, and the trench isolation structure STI of the memory cell area 100A defines a plurality of active areas AA, each of which includes, for example, a source/drain area S/D. The peripheral circuit region and the junction region 100C also have the trench isolation structures STI therein, respectively.

The substrate 100 also has word line trenches formed therein, a plurality of which are located in the memory cell region 100A, for accommodating the word lines WL. Specifically, the word line trench extends along the first direction D1 to pass through the corresponding active area AA and the trench isolation structure STI. A plurality of word lines WL are positioned in the word line trench and spaced along the second direction D2, each of the word lines WL extending along the first direction D1 to intersect with a corresponding active area AA in the memory cell area 100A. The source/drain region S/D includes a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the word line WL to jointly form a storage transistor.

The word line WL may include a gate dielectric layer, a gate conductive layer, and a gate insulating layer, wherein the gate dielectric layer covers an inner wall of the word line trench, the gate conductive layer is located on the gate dielectric layer and fills the word line trench with a partial depth, and the gate insulating layer is located on the gate conductive layer and fills a remaining depth of the word line trench.

With continued reference to fig. 2k and fig. 2j, a plurality of bit lines BL are formed on the substrate 100 and at least in the memory cell region 100A. Specifically, in the present embodiment, the bit lines BL are arranged at intervals along a first direction D1, and each of the word lines WL extends from the memory cell region 100A to the interface region 100C along the first direction D1. In this way, each of the bit lines BL also intersects with the corresponding active area AA in the memory cell area 100A.

With continued reference to fig. 2k and fig. 2j, the bit line BL may be a multi-layer structure including at least one conductive layer, a mask layer 204a and a fourth insulating layer 207b stacked in sequence. In this embodiment, the number of the conductive layers is two, that is, a first conductive layer 202a and a second conductive layer 203a, the second conductive layer 203a covers the first conductive layer 202a, and the mask layer 204a and the fourth insulating layer 207b serve as shielding layers for the bit line BL. The material of the first conductive layer 202a includes, for example, doped polysilicon, the material of the second conductive layer 203a includes, for example, a metal (e.g., tungsten, titanium, aluminum, copper, nickel, cobalt, or tantalum), and the material of the fourth insulating layer 207b includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

At least a portion of the bit lines BL may further include connection contacts 300, the connection contacts 300 being disposed in contact holes penetrating the first conductive layer 202a and a portion of the substrate 100 to be electrically connected with source/drain regions S/D within the substrate 100. It is also understood that a portion of the bit lines BL are located on the substrate 100, and another portion of the bit lines BL extend into the substrate 100 and are electrically connected to the source/drain regions S/D in the substrate 100.

Further, a second sidewall SP2 covers sidewalls of the bit line BL, wherein the second sidewall SP2 at least covers sidewalls of the first conductive layer 202a, the second conductive layer 203a, the mask layer 204a, and the fourth insulating layer 207b stacked in sequence, so as to protect the first conductive layer 202a and the second conductive layer 203a from being invaded by the outside together with the shielding layer.

With continued reference to fig. 2k, adjacent the bit lines BL may further define node contacts (not shown) for receiving node contact structures. In a specific embodiment, a plurality of separation lines (not shown) are further formed on the substrate 100, and the separation lines extend along the first direction D1, and the separation lines and the bit lines BL are perpendicular to each other, so that the separation lines and the bit lines BL intersect to surround the node contact windows.

Further, a plurality of the dummy lines DL are formed on the substrate 100 and located in the junction area 100C. Specifically, in this embodiment, the dummy lines DL are arranged at intervals along the first direction D1, and each of the dummy lines DL extends to one end along the first direction D1 and is overlapped with one end of the bit line BL. In this way, one of the dummy lines DL and one of the bit lines BL are aligned with each other in the second direction D2, and one end of each of the dummy lines DL overlaps one end of the corresponding bit line BL to form a continuous line structure in the second direction D2.

The dummy lines DL are disposed at the same layer as the bit lines BL and may be simultaneously prepared at the time of preparation, but unlike the bit lines BL, the dummy lines DL exist only as a pattern without performing some functions, such as transferring an electrical signal, storing electrons, and the like.

With continued reference to fig. 2j, the dummy line DL may be a multi-layer structure, which includes at least a first insulating layer 206a and a second insulating layer 207a stacked in sequence, wherein the second insulating layer 207a covers the first insulating layer 206 a. Further, the sidewalls of the second insulating layer 207a are vertical, that is, the bottom of the second insulating layer 206a has a lateral width equal to that of the top, so that the second insulating layer 207a has a rectangular cross section in the third direction D3 (perpendicular to the thickness direction); the lateral width X1 of the bottom of the first insulating layer 206a is greater than the lateral width X2 of the top, so that the first insulating layer 206a exhibits a narrow-top-to-wide-bottom profile. In this embodiment, the lateral width of the first insulating layer 206a gradually decreases along the bottom-to-top direction, so that the cross section of the first insulating layer 206a in the third direction D3 is a trapezoid, but not limited thereto.

Because the first insulating layer 206a has a structure with a narrow top and a wide bottom, which is equivalent to increasing the width of the bottom of the dummy line DL, the strength of the dummy line DL is enhanced, the dummy line DL is prevented from falling due to the large height and width, and the performance and stability of the device are improved; in addition, because only the width of the bottom of the virtual line DL is increased, various parameters of the device cannot be influenced.

In this embodiment, the height-width ratio of the virtual line DL is greater than 10, that is, the ratio of the lateral width X5 to the depth h of the virtual line DL is greater than 10.

In this embodiment, the lateral width X1 of the bottom of the first insulating layer 206a is greater than twice the lateral width X2 of the top, i.e., X1 > 2X2, so that the anti-collapse effect of the dummy line DL can be increased.

Further, a first sidewall SP1 covers a sidewall of the dummy line DL, wherein the first sidewall SP1 at least covers sidewalls of the first insulating layer 206a and the second insulating layer 207a stacked in sequence.

In this embodiment, the second insulating layer 207a and the fourth insulating layer 207b are two parts of the same film layer, and can be prepared synchronously; similarly, the first side wall SP1 and the second side wall SP2 can be prepared simultaneously, which will be described later.

The first insulating layer 206a and the second insulating layer 207a are both made of insulating materials, and the first insulating layer 206a and the second insulating layer 207a may be made of the same material or different materials. In this embodiment, the first insulating layer 206a is made of silicon oxide, and the second insulating layer 207a is made of silicon nitride.

Based on this, the present embodiment also provides a method for manufacturing a semiconductor device. Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. As shown in fig. 1, the method for manufacturing a semiconductor device includes:

step S100: providing a substrate, wherein the substrate is provided with a memory cell area, a peripheral circuit area and a junction area positioned between the memory cell area and the peripheral circuit area;

step S200: forming a plurality of bit lines on the substrate, wherein the bit lines are arranged at intervals along a first direction and extend from the memory cell area to the junction area along a second direction; and;

step S300: and forming a plurality of dummy lines on the substrate of the interface region, wherein one of the dummy lines is butted with the end of one of the bit lines and aligned along the second direction, and each of the dummy lines comprises a first insulating layer and a second insulating layer which are sequentially stacked on the substrate, wherein the transverse width of the bottom of the first insulating layer is greater than that of the top of the first insulating layer.

The method for manufacturing the semiconductor device provided in this embodiment will be described in detail below with reference to fig. 2a to 2 k.

Referring to fig. 2a, step S100 is performed to provide a substrate 100, where the substrate 100 includes a memory cell area 100A, a peripheral circuit area, and a junction area 100C located between the memory cell area 100A and the peripheral circuit area.

The substrate 100 is formed with a trench isolation structure STI, the trench isolation structure STI in the memory cell area 100A may define a plurality of active areas AA located in the memory cell area 100A, the active areas AA are distributed in an array, and each active area AA includes two source/drain areas S/D.

The STI is formed by, for example, forming at least one isolation trench in the substrate 100 by etching, and then filling the isolation trench with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.

A plurality of word line trenches are formed in the substrate 100 of the memory cell region 100A, the plurality of word line trenches being spaced apart along the second direction D2, each of the word line trenches extending along the first direction D1 to pass through a corresponding one of the active regions AA. Two source/drain regions S/D in each of the active regions AA are arranged at both sides of the corresponding word line trench. Specifically, the source/drain region S/D includes a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the word line trench.

Word lines (not shown) are filled in the word line trenches, so that a plurality of the word lines are also arranged at intervals along the second direction D2, and each of the word lines extends along the first direction D1.

It should be noted that, the source/drain regions S/D may be prepared after the word lines are formed, or the source/drain regions S/D may be preferentially formed and then the word lines are prepared, which is not limited herein.

The forming of the word line may include: forming a gate dielectric layer on the inner wall of the word line groove; forming a gate conductive layer on the gate dielectric layer, wherein the gate conductive layer fills the word line groove with partial depth; and forming a gate insulating layer on the gate conducting layer, wherein the gate insulating layer fills the residual depth of the word line groove.

Steps S200 and S300 are performed to simultaneously form a plurality of bit lines BL and a plurality of dummy lines DL.

Specifically, referring to fig. 2b, a first buffer material layer 201 is formed on the substrate 100. The first buffer material layer 201 may be formed of one or more insulating layers, and for example, the first buffer material layer 201 may be formed of at least one film layer of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

Referring to fig. 2b, a first conductive material layer 202 is formed on the first buffer material layer 201. The first conductive material layer 202 may be a doped polysilicon layer. In this embodiment, the first buffer material layer 201 and the first conductive material layer 202 may be formed by a chemical vapor deposition process (CVD) or a physical vapor deposition Process (PVD). It should be understood that the first buffer material layer 201 and the first conductive layer 202a cover the entire surface of the substrate 100, that is, the first buffer material layer 201 and the first conductive layer 202a are stacked in sequence to cover the memory cell region 100A, the peripheral circuit region, and the interface region 100C.

Referring to fig. 2b, an etching process is performed on the first conductive layer 202a, the first buffer material layer 201 and the substrate 100 with a partial depth to form a contact hole. The contact hole penetrates through the first conductive layer 202a and the first buffer material layer 201 and extends into the substrate 100, and exposes one of the two source/drain regions S/D.

Next, a connection contact 300 is formed in the contact hole, and the connection contact 300 may completely fill the contact hole, such that the connection contact 300 passes through the first conductive layer 202a and the first buffer material layer 201 and extends into the substrate 100 to electrically connect one of the source/drain regions S/D. The connection contact 300 may include a polysilicon layer doped with N-type or P-type ions.

Referring to fig. 2c, a second conductive material layer 203 is formed on the first conductive material layer 202. The second conductive material layer 203 may include one or more conductive material layers. For example, the second conductive material layer 203 may include at least one of a tungsten (W) layer, an aluminum (Al) layer, a copper (Cu) layer, a nickel (Ni) layer, or a cobalt (Co) layer.

In addition, in some embodiments, a diffusion barrier layer may be further formed between the conductive material layers in the second conductive material layer 203. The diffusion barrier layer may be, for example, a titanium nitride (TiN) layer, a Ti/TiN layer, a titanium silicon nitride (TiSiN) layer, a tantalum nitride (TaN) layer, or a tungsten nitride (WN) layer.

With continued reference to fig. 2c, a mask material layer 204 is formed on the second conductive material layer 203. The mask material layer 204 may include at least one of a silicon nitride layer or a silicon oxynitride layer.

It should be understood that the second conductive material layer 203 and the mask material layer 204 cover the entire surface of the substrate 100, that is, the second conductive material layer 203 and the mask material layer 204 cover the memory cell region 100A, the peripheral circuit region and the interface region 100C after being sequentially stacked.

With continued reference to fig. 2C, the mask material layer 204 in the junction area 100C is etched to expose the junction area 100C.

Referring to fig. 2d, using the mask material layer 204 as a mask, etching is performed to remove the second conductive material layer 203, the first conductive material layer 202, and the first buffer material layer 201 in the junction area 100C. At this time, the trench isolation structures STI of the junction region 100C are exposed.

Referring to fig. 2e, a second buffer material layer 205 is formed on the substrate 100, and the second buffer material layer 205 conformally covers the remaining mask material layer 204 and the surface of the substrate 100 in the interface region 100C. The second buffer material layer 205 may include at least one of a silicon nitride layer, and a silicon oxynitride layer. In this embodiment, the material of the second buffer material layer 205 is the same as the material of the first buffer material layer 201, and is silicon oxide.

Referring to fig. 2f, a first insulating material layer 206 is formed on the second buffer material layer 205, and then a planarization process is performed on the first insulating material layer 206. As shown in fig. 2g, in the present embodiment, the second buffer material layer 205 on the memory cell region 100A may be used as a stop layer, and the planarization process is stopped on the mask material layer 204.

Next, a planarization process is performed again to remove the second buffer material layer 205 on the memory cell region 100A (and also remove a portion of the thickness of the mask material layer 204). As shown in fig. 2f, after planarization, the top surface and height of the mask material layer 204 on the memory cell region 100A are flush with the height of the top surface of the first insulating material layer 206 on the interface region 100C.

Referring to fig. 2h, a second insulating material layer 207 is formed on the entire surface of the substrate 100, that is, the second insulating material layer 207 covers the mask material layer 204 and the first insulating material layer 206.

Referring to fig. 2i, an etching process is performed to sequentially etch the second insulating material layer 207 and the first insulating material layer 206 in the junction area 100C to form a first opening 401; and sequentially etching the second insulating material layer 207, the mask material layer 204, the second conductive material layer 203 and the second conductive material layer 204 of the memory cell region 100A to form a second opening 402.

It should be understood that the first opening 401 and the second opening 402 may be formed simultaneously, or one of them may be formed first and then the other one may be formed.

Further, the first opening 401 has two portions that are connected up and down, and the two portions are respectively located in the second insulating material layer 207 and the first insulating material layer 206, for convenience of description, the two portions of the first opening 401 are divided into a first sub opening and a second sub opening, where the first sub opening is located in the second insulating material layer 207, the second sub opening is located in the first insulating material layer 206, and the first sub opening and the second sub opening are connected to form the first opening 401.

The sidewalls of the first sub-opening may be vertical, that is, the top and the bottom of the first sub-opening have the same lateral width along the first direction D1, and thus the cross-section of the first sub-opening in the third direction D3 is rectangular.

The side walls of the second sub-opening are inclined, and the transverse width X4 of the top of the second sub-opening is larger than the transverse width X3 of the bottom of the second sub-opening, so that the second sub-opening has a structure which is wide at the top and narrow at the bottom. In this embodiment, the transverse width of the second sub-opening in the first direction D1 gradually decreases along the top-to-bottom direction, so that the cross section of the second sub-opening in the third direction D3 is an inverted trapezoid, but not limited thereto.

In the present embodiment, the lateral width X4 of the top of the second sub-opening is greater than twice the lateral width X3 of the bottom, i.e., X4 > 2X 3.

As shown in fig. 2i, after the etching is completed, the first insulating material layer 206 remaining on the interface region 100C forms a first insulating layer 206a, the second insulating material layer 207 remaining on the interface region 100C forms a second insulating layer 207a, and the first insulating layer 206a and the second insulating layer 207a are stacked to form a dummy line DL, wherein each of the dummy lines DL is separated by the first opening 401.

With reference to fig. 2i, after the etching is completed, the remaining second insulating material layer 207 on the memory cell region 100A forms a fourth insulating layer 207b, the remaining mask material layer 204 on the memory cell region 100A forms a mask layer 204a, the remaining second conductive material layer 203 on the memory cell region 100A forms a second conductive layer 203a, and the remaining first conductive material layer 202 on the memory cell region 100A forms a first conductive layer 202 a. The first conductive layer 202a, the second conductive layer 203a, the mask layer 204a and the fourth insulating layer 207b are stacked in sequence to form a bit line BL, and each bit line BL is separated by the second opening 402.

Referring to fig. 2j, a first sidewall SP1 is formed on a sidewall of the dummy line DL and a second sidewall SP2 is formed on a sidewall of the bit line BL. The first sidewall SP1 covers sidewalls of the dummy line DL, that is, the first sidewall SP1 covers sidewalls of the stacked second insulating layer 207a and the stacked first insulating layer 206 a. The second sidewall SP2 covers sidewalls of the stacked fourth insulating layer 207b, mask layer 204a, second conductive layer 203a, and first conductive layer 202 a.

In this embodiment, the first sidewall SP1 and the second sidewall SP2 may be formed of at least one film, for example, the first sidewall SP1 and the second sidewall SP2 may be a silicon oxide layer or an ONO structure.

Example two

Fig. 3 is a cross-sectional view of the semiconductor device provided in this embodiment along the aa direction and the bb direction. As shown in fig. 3, the difference from the first embodiment is that in the present embodiment, the dummy line DL further includes a third insulating layer 208a, and the third insulating layer 208a is located between the first insulating layer 206a and the second insulating layer 207 a.

In this embodiment, the first insulating layer 206a, the second insulating layer 207a and the third insulating layer 208a each include at least two or more insulating materials, for example, the first insulating layer 206a, the second insulating layer 207a and the third insulating layer 208a are each composed of two or more materials selected from silicon oxide, silicon nitride and silicon oxynitride, the first insulating layer 206a and the third insulating layer 208a may be made of the same or different materials, preferably, the first insulating layer 206a is made of a different material from the second insulating layer 207a, and the second insulating layer 207a is made of a different material from the third insulating layer 208a, so as to be selected by an etchant during manufacturing.

In this embodiment, the top and bottom of the third insulating layer 208a have the same lateral width, so that the cross section of the third insulating layer 208a along the thickness direction is rectangular.

Correspondingly, the bit line BL further includes a fifth insulating layer 208b, and the fifth insulating layer 208b is located between the fourth insulating layer 207b and the mask layer 204 a.

Therefore, in the manufacturing of the semiconductor device in this embodiment, before the second insulating material layer 207 is formed, a third insulating material layer is further formed, and when the first opening 401 and the second opening 402 are formed, the third insulating material layer needs to be etched. After the etching is completed, the third insulating material layer remaining in the interface region 100C forms the third insulating layer 208a, the fifth insulating layer 208b forms the third insulating material layer remaining in the memory cell region 100A, the first insulating layer 206a, the second insulating layer 207a, and the third insulating layer 208a are sequentially stacked to form the dummy line DL, and the first conductive layer 202a, the second conductive layer 203a, the mask layer 204a, the fifth insulating layer 208b, and the fourth insulating layer 207b are sequentially stacked to form the bit line BL.

It should be understood that, in the embodiment, due to the addition of the third insulating layer 208a between the first insulating layer 206a and the second insulating layer 207a, the second insulating material layer 207 can be made thinner during the fabrication of the dummy lines DL and the bit lines BL, and during the etching, the second insulating material layer 207 and the third insulating material layer can be etched step by step, thereby reducing the difficulty of the fabrication.

EXAMPLE III

Fig. 5 is a cross-sectional view of the semiconductor device provided in this embodiment along the aa direction and the bb direction. As shown in fig. 5, the difference between the first and second embodiments is that in the present embodiment, a part of the thickness of the bottom of the first insulating layer 206a of the dummy line DL extends laterally to connect with the bottom of the first insulating layer 206a of the adjacent dummy line DL, so as to cover a part of the surface of the substrate 100 in the interface region 100C.

Referring to fig. 5, in the present embodiment, the first insulating layers 206a of all the dummy lines DL extend laterally to be connected together to form a film layer, so that at least a portion of the surface of the substrate 100 in the junction area 100C is covered by the first insulating layers 206 a.

In the fabrication of the semiconductor device in this embodiment, similarly to the embodiment, the semiconductor structure in fig. 2h is first fabricated according to the steps in fig. 2a to fig. 2 h. Next, as shown in fig. 2h and fig. 4, first, the second insulating material layer 207 is etched to form a first opening 401 and a second opening 402 penetrating through the second insulating material layer 207, where the first opening 401 and the second opening 402 are located in the interface region 100C and the memory cell region 100A, respectively. Then, the first insulating material layer 206 and the mask material layer 204, the second conductive material layer 203, the first conductive material layer 202, and the connection contact 300 are continuously etched downward simultaneously, so that the first opening 401 and the second opening 402 extend downward.

In this embodiment, the etching rate of the mask material layer 204, the second conductive material layer 203, the first conductive material layer 202 and the connection contact 300 is greater than the etching rate of the first insulating material layer 206, and after the etching of the first insulating material layer 206 is completed, the first insulating material layer 206 has a remaining thickness, that is, the first opening 401 penetrates through the second insulating material layer 207 and extends into the first insulating material layer 206, and the second opening 402 penetrates through the second insulating material layer 207, the mask material layer 204, the second conductive material layer 203, the first conductive material layer 202 and the connection contact 300, and exposes the substrate 100 of the memory cell region 100A.

As shown in fig. 4 and 5, since the first insulating material layer 206 is not completely etched, after the dummy lines DL are formed, a part of the thickness of the bottom of the first insulating layer 206a of each dummy line DL extends laterally to be connected to the bottom of the first insulating layer 206a of the adjacent dummy line DL, and covers a part of the surface of the substrate 100 in the interface region 100C.

It should be understood that the "lateral width" described herein refers to the width along the first direction D1.

In summary, in the semiconductor device provided in this embodiment, the substrate has a memory cell region, a peripheral circuit region, and an interface region located between the memory cell region and the peripheral circuit region; the bit lines are positioned on the substrate and arranged at intervals along a first direction, and extend from the memory cell area to the junction area along a second direction; the plurality of dummy lines are located on the substrate of the interface area, one of the dummy lines is butted with an end of one of the bit lines and aligned along the second direction, and each of the dummy lines includes a first insulating layer and a second insulating layer stacked on the substrate in sequence. In the utility model, the transverse width of the bottom of the first insulating layer is larger than that of the top, the strength of the virtual line is enhanced by increasing the width of the bottom of the virtual line, the virtual line is prevented from lodging due to the larger height and width, and the performance and stability of the device are improved; in addition, because only the width of the bottom of the virtual line is increased, various parameters of the device cannot be influenced.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should also be noted that, although the present invention has been described with reference to the preferred embodiments, the above-mentioned embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device of claim 1, wherein a lateral width of the bottom portion of the first insulating layer is greater than twice a lateral width of the top portion.

3. The semiconductor device according to claim 1 or 2, wherein a lateral width of the first insulating layer is gradually reduced from a bottom to a top.

4. The semiconductor device according to claim 1 or 2, wherein a cross section of the first insulating layer in the third direction is a trapezoid.

5. The semiconductor device of claim 1, wherein an aspect ratio of the dummy line is greater than 10.

6. The semiconductor device according to claim 1, further comprising a first sidewall and a second sidewall, wherein the first sidewall covers a sidewall of the dummy line, and the second sidewall covers a sidewall of the bit line.

7. The semiconductor device according to claim 1, wherein each of the dummy lines further comprises a third insulating layer, the third insulating layer being located between the first insulating layer and the second insulating layer.

8. The semiconductor device according to claim 1, wherein a part of a thickness of a bottom of the first insulating layer of the dummy line extends laterally to connect with a bottom of the first insulating layer of an adjacent dummy line to cover a part of a surface of the substrate of the interface region.