CN214336717U

CN214336717U - Display panel

Info

Publication number: CN214336717U
Application number: CN202120401329.4U
Authority: CN
Inventors: 温质康; 乔小平; 苏智昱
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2021-02-23
Filing date: 2021-02-23
Publication date: 2021-10-01
Anticipated expiration: 2031-02-23

Abstract

The utility model discloses a display panel, include: the thin film transistor is arranged on the front surface of the substrate, an insulating layer in the thin film transistor is provided with a hole, the hole in the insulating layer is communicated with a through hole in the substrate, a second electrode layer and a source electrode in the thin film transistor are arranged on the same layer, and the second electrode layer is connected with the source electrode or the drain electrode; the flat layer covers the thin film transistor and the second electrode layer; the first electrode layer is connected with the source electrode or the drain electrode through a first hole in the flat layer; the first pixel definition layer is arranged on the flat layer and the first electrode layer, the first light-emitting layer is arranged in the second hole of the first pixel definition layer, and the first light-emitting layer is connected with the first electrode layer; the second pixel defining layer is disposed on the back surface of the substrate, and the second light emitting layer is connected to the second electrode layer through the third hole. In the technical scheme, the first light-emitting layer and the second light-emitting layer are driven by the same thin film transistor, and the two light-emitting layers are respectively arranged on the front surface and the back surface of the substrate, so that the resolving power of the display panel is improved.

Description

Display panel

Technical Field

The utility model relates to a show technical field, especially relate to a display panel.

Background

Mini LED (Light Emitting Diode), i.e. sub-millimeter Light Emitting Diode, is characterized by lightness, thinness, low power consumption, good flexibility, high flexibility, fine adjustment of Light adjustment partition, local Light adjustment, and narrow frame … …

The split screen technology that generally adopts thin film transistors to drive the Mini LEDs realizes high resolution in the future. The light emitting layer array of the Mini LED is arranged on the substrate and is positioned on the same layer. Unavoidable gaps exist among the Mini LED lamps, and when the screen is lightened, dark spots and dark stripes appear on the screen. If the higher screen resolution and the more meticulous district of adjusting luminance of will realizing, it is comparatively main direction to reduce the size of Mini LED lamp and reduce the interval between the Mini LED lamp pearl, and it can realize littleer pixel interval display to reduce the clearance between the Mini LED, and then improves the definition and the resolution of panel picture.

SUMMERY OF THE UTILITY MODEL

Therefore, it is desirable to provide a display panel that solves the problem of how to reduce the pitch between pixels of the display panel.

In order to achieve the above object, the present embodiment provides a display panel including a substrate, a thin film transistor, a second electrode layer, a planarization layer, a first electrode layer, a first pixel defining layer, a first light emitting layer, a second pixel defining layer, and a second light emitting layer;

the substrate is provided with a through hole, and the through hole on the substrate is communicated with the front surface of the substrate and the back surface of the substrate;

the thin film transistor is arranged on the front surface of the substrate, an insulating layer in the thin film transistor is provided with a hole, the hole in the insulating layer is communicated with the through hole in the substrate, so that the thin film transistor is exposed out of the through hole in the substrate, a second electrode layer and a source electrode in the thin film transistor are arranged on the same layer, the second electrode layer is connected with the source electrode or a drain electrode, the second electrode layer, the source electrode and the drain electrode are all transparent, and the second electrode layer extends into a third hole in the back surface of the substrate through the side wall of the hole in the insulating layer and the side wall of the through hole in the substrate;

the flat layer is arranged on the thin film transistor and covers the thin film transistor and the second electrode layer;

the first electrode layer is arranged on the flat layer and is connected with the source electrode or the drain electrode through a first hole in the flat layer;

the first pixel definition layer is arranged on the flat layer and the first electrode layer, the first light-emitting layer is arranged in a second hole of the first pixel definition layer, and the first light-emitting layer is connected with the first electrode layer through the second hole;

the second pixel defining layer is disposed on the rear surface of the substrate, the second light emitting layer is disposed in the third hole of the second pixel defining layer, and the second light emitting layer is connected to the second electrode layer through the third hole.

Furthermore, the second electrode layer located in the hole region on the insulating layer is of a hollow structure, a fourth hole on the flat layer is communicated with the hollow region of the second electrode layer, and the second hole is communicated with the fourth hole;

the first light-emitting layer and the second light-emitting layer are both Mini LEDs, lamp bead pins of the first light-emitting layer are connected with the first electrode layer through tin paste, lamp bead pins of the second light-emitting layer are connected with the second electrode layer through the tin paste, and the tin paste in the second hole is also connected with the second light-emitting layer through the fourth hole and the hollow area of the second electrode layer.

Further, the display device further comprises an encapsulation layer, wherein the encapsulation layer is arranged on the first pixel definition layer and covers the first light-emitting layer; or:

the encapsulation layer is disposed on the second pixel defining layer, and covers the second light emitting layer.

Further, the display device further comprises a light reflecting layer, wherein the light reflecting layer covers the second light emitting layer and the second pixel defining layer.

The light shielding layer is arranged between the thin film transistor and the flat layer, the projection of the active layer in the thin film transistor is located in the projection of the light shielding layer, and the direction of the projection is perpendicular to the front surface of the substrate.

Different from the prior art, in the technical scheme, the first light-emitting layer and the second light-emitting layer are driven by the same thin film transistor to be lightened, and the two light-emitting layers are respectively arranged on the front surface and the back surface of the substrate, so that gapless emission of light in the vertical direction is realized. The pixels of the two light emitting layers are overlapped, so that the resolution and the resolution of the display panel are increased, and the brightness of the display panel is improved. The technical scheme can also realize transparent display or double-sided display, and improve the competitiveness of the product.

Drawings

FIG. 1 is a schematic cross-sectional view illustrating an etching stop layer formed on a substrate according to the present embodiment;

FIG. 2 is a schematic cross-sectional view illustrating a light-shielding layer formed on a substrate according to the present embodiment;

FIG. 3 is a schematic cross-sectional view illustrating a planar layer formed on a substrate according to the present embodiment;

FIG. 4 is a schematic cross-sectional view illustrating a first electrode layer formed on a substrate according to the present embodiment;

fig. 5 is a schematic cross-sectional structure diagram illustrating a first pixel defining layer and a second pixel defining layer formed on a substrate according to the present embodiment;

fig. 6 is a schematic cross-sectional view illustrating a first light-emitting layer, a second light-emitting layer and a light-reflecting layer formed on a substrate according to the present embodiment.

Description of reference numerals:

1. a substrate;

11. a through hole;

2. a thin film transistor;

21. a gate electrode; 22. a gate insulating layer; 23. an active layer; 24. etching the barrier layer; 25. a source electrode; 26. a drain electrode; 27. a buffer layer;

3. a second electrode layer;

4. a light-shielding layer;

5. a planarization layer;

51. a first hole; 52. a fourth aperture;

6. a first electrode layer;

7. a first pixel defining layer;

71. a first light-emitting layer; 711. a lamp bead pin; 72. a second hole;

8. a second pixel defining layer;

81. a second light emitting layer; 82. a third aperture;

9. tin paste;

10. a light reflecting layer.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 6, the present embodiment is directed to a method for manufacturing a display panel, which can be performed on a substrate 1, such as a glass substrate or a plastic substrate, where the substrate 1 is used to support various film layers. The manufacturing method of the display panel comprises the following steps: through holes 11 are made in the substrate 1. The through holes 11 may be made by laser drilling or etching. The through hole 11 on the substrate communicates the front surface of the substrate 1 and the back surface of the substrate 1 for serving as a connection point of the second electrode layer 3 and the second light emitting layer 81. The cross section of the through hole 11 is in a shape of a circle, a triangle, a rectangle, a pentagon, etc.

A thin film transistor 2 and a second electrode layer 3 are formed on the front surface of the substrate, and the structure is shown in fig. 1 and 2. The second electrode layer 3 and the source electrode 25 in the thin film transistor 2 are disposed on the same layer, and the second electrode layer 3 is connected to the source electrode 25 or the drain electrode 26. The second electrode layer 3, the source electrode 25 and the drain electrode 26 are all transparent to light, so that light emitted from the second light-emitting layer 81 located on the back surface of the substrate can be irradiated to the front surface direction of the substrate. The second electrode layer 3 extends to the back side of the substrate through the sidewall of the hole on the insulating layer and the sidewall of the through hole on the substrate.

When the insulating layers (the gate insulating layer 22 and the etch stop layer 24) in the thin film transistor 2 are manufactured, a hole is formed in the insulating layer in the through hole region on the substrate, and the through hole on the insulating layer is based on the through hole on the substrate, so that the thin film transistor 2 is exposed out of the through hole on the substrate, and the subsequent manufacturing of the second electrode layer 3 is facilitated.

The display panel driven by the thin film transistor 2 as a switch can achieve the characteristics of high speed, high brightness and high contrast. The thin film transistor 2 may be a top gate structure or a bottom gate structure, and a thin film transistor with a bottom gate structure is exemplified herein.

A gate electrode 21 is formed on the front surface of the substrate, and the structure is shown in fig. 1. Specifically, a photoresist is coated on the substrate, the photoresist is exposed and developed so that a portion where the gate electrode is to be fabricated is opened, and then a gate metal is plated onto the front surface of the substrate, thereby forming the gate electrode 21 on the substrate. After the gate 21 is fabricated, the photoresist is removed. It should be noted that the gate metal can be plated on the substrate by physical vapor deposition. The gate metal is opaque, and the opaque gate is used to protect the upper active layer 23 from being irradiated by the second light emitting layer 81 on the back surface of the substrate, so as to prevent the active layer 23 from being irradiated by light and being failed.

The gate metal may be one or a combination of more of aluminum, molybdenum, copper, and gold, but is not limited thereto. For example, the gate metal is a combination of molybdenum (Mo)/copper (Cu) with a copper film layer thickness of 0.4um (microns) to 0.5um (microns) and a molybdenum film layer thickness of 0.1um (microns) to 0.2um (microns). Preferably, the thickness of the copper film layer is 0.42um and the thickness of the molybdenum film layer is 0.15um in the gate metal of the Mo/Cu combination.

After the gate electrode 21 is formed, a gate insulating layer 22 is formed on the gate electrode 21 to isolate the gate electrode 21 from the active layer 23, and the structure is shown in fig. 1. Specifically, the gate electrode may be coated with an insulating material by plasma enhanced chemical vapor deposition and then etched to form the appropriate gate insulating layer 22. Among them, the insulating material is, but not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), and the like. In order to achieve effective isolation, the gate insulating layer 22 covers the gate electrode 21 and may cover the entire surface of the substrate. The thickness of the gate insulating layer is 0.2um to 0.4 um. Preferably, the thickness of the gate insulating layer is 0.3 um.

The hole in the gate insulating layer may be etched, and the hole in the gate insulating layer may be located at the bottom of the hole in the substrate, that is, the hole in the gate insulating layer may communicate with the hole in the substrate.

After the gate insulating layer 22 is formed, an active layer 23 is formed on the gate insulating layer 22, and the structure is shown in fig. 1. Specifically, an active layer material may be deposited on the gate insulating layer 22 by sputtering, and the active layer material attached to the gate insulating layer 22 is exposed, developed, etched, and stripped to form the active layer 23. The active layer material may be an oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Titanium Oxide (IGZTO), etc., but is not limited thereto.

The thickness of the active layer is 0.03um to 0.06 um. Preferably, the thickness of the active layer is 0.04 um.

After the active layer 23 is manufactured, an etching stop layer 24 is manufactured on the active layer 23, and the etching stop layer 24 protects the active layer 23 from being corroded by the etching solution and the stripping solution, and the structure is shown in fig. 1. In particular, plasma enhanced chemical vapor deposition may be used to deposit the insulating material and then etch the appropriate etch stop layer 24. Among them, the insulating material is, but not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), and the like. In order to effectively protect, the etch stopper layer 24 covers not only the active layer 23 but also the gate insulating layer 22. In some embodiments, the etch stop layer may not need to be fabricated.

The thickness of the etching stopper layer is 0.15um to 0.3 um. Preferably, the etch stop layer has a thickness of 0.02 um.

Before the source electrode 25 and the drain electrode 26 are formed, a fifth hole is formed in the etch stop layer 24, and the structure is shown in fig. 1. The bottom of the fifth hole is a surface of the active layer, and the fifth hole serves not only as a connection point between the active layer and the source electrode 25 but also as a connection point between the active layer 23 and the drain electrode 26. Meanwhile, a sixth hole can be formed in the etching barrier layer 24, the sixth hole is communicated with the hole in the gate insulating layer, and the sixth hole, the hole in the gate insulating layer and the hole in the substrate are communicated, so that the thin film transistor 2 exposes a through hole in the substrate, and the subsequent formation of the second electrode layer 3 is facilitated.

After the etching stop layer 24, the fifth hole and the sixth hole are formed, the source electrode 25, the drain electrode 26 and the second electrode layer 3 are formed on the etching stop layer 24, and the structure is shown in fig. 2. The source and drain metal may be plated by sputtering, and the source and drain metal may be exposed, developed, etched, and stripped to form the source 25, the drain 26, and the second electrode layer 3. The source electrode 25 and the drain electrode 26 are connected to an active layer through a fifth hole, and the source electrode 25 and the drain electrode 26 form ohmic contact with the underlying active layer. The source electrode 25, the drain electrode 26, the active layer 23, and the gate electrode 21 are formed as components of the thin film transistor 2. The source/drain metal is also plated with a thin film inside the sixth hole, and the thin film is continued to the back surface of the substrate to form the second electrode layer 3 coated with a double-sided film. The second electrode layer 3 is connected to the source electrode 25 or the drain electrode 26, so that the thin film transistor 2 can control the second light emitting layer 81 through the second electrode layer 3.

In order to make the light emitted from the second light emitting layer 81 on the back of the substrate penetrate the front direction of the substrate, the source and drain metals are made of a transparent material, so that the second electrode layer 3, the source 25 and the drain 26 are transparent, and the light can penetrate the second electrode layer 3, the source 25 and the drain 26 to the upper side. The source and drain electrode metal can be a laminated film structure, such as Al/Mo or Cu/MoTi. Taking the composition of Al/Mo as an example, the thickness of the Al film layer in the Al/Mo structure is 0.3um to 0.4um, preferably 0.33 um; the thickness of the Mo film layer is 0.02 um-0.08 um, preferably 0.06 um.

It should be noted that the second electrode layer is prepared together with the source electrode, which is a step that can save the process, and of course, the second electrode can be prepared separately or together with the first electrode layer 6.

In order to protect the thin film transistor 2 and prevent the thin film transistor 2 from being damaged by an external circuit, a buffer layer 27 is formed on the thin film transistor 2, and the structure thereof is as shown in fig. 2. Specifically, the thin film transistor 2 may be coated with an insulating material by plasma enhanced chemical vapor deposition, and then etched to obtain the appropriate buffer layer 27. Among them, the insulating material is, but not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), and the like. The buffer layer 27 covers the thin film transistor 2 and the second electrode layer 3, and external structures are blocked by the buffer layer 27 and do not contact the thin film transistor 2 and the second electrode layer 3 under the buffer layer 27.

The active layer in the thin film transistor is easily affected by light, which affects the stability of the thin film transistor, and in order to prevent the active layer from being irradiated by light, the light shielding layer 4 is formed on the buffer layer 27, and the structure is as shown in fig. 2. The light-shielding layer 4 is disposed on the buffer layer 27, and a projection of the active layer in the thin film transistor is located in a projection of the light-shielding layer 4, the projection being in a direction perpendicular to the front surface of the substrate. The light shielding layer may be made of a light-impermeable material, such as metal, black resin, a light shielding tape, or the like. When light irradiates the active layer, the light is shielded by the light shielding layer, and the active layer is not irradiated by the light, so that the performance of the thin film transistor is ensured. The thickness of the light-shielding layer is 0.1um to 0.2 um. Preferably, the light-shielding layer has a thickness of 0.15 um.

Since the substrate is formed with rugged surface due to multiple processes, in order to make the substrate flat and facilitate the subsequent film layer fabrication, a flat layer 5 is fabricated on the buffer layer 27, and the structure is shown in fig. 3. Specifically, the buffer layer may be coated with an insulating material by plasma enhanced chemical vapor deposition, and then etched to obtain a suitable planarization layer 5. Among them, the insulating material is, but not limited to, nitride (silicon nitride or the like), oxide (silicon oxide or the like), polyimide, or the like. The flat layer 5 is located on the buffer layer 27, and the flat layer 5 covers the thin film transistor 2 and the second electrode layer 3. The flat layer 5 has a certain thickness, and the upper surface of the flat layer 5 is a plane and parallel to the front surface of the substrate.

In order to connect the first electrode layer 6 and the thin film transistor, a first hole 51 is formed in the planarization layer 5, and the structure is shown in fig. 3. The bottom of the first hole 51 is the source electrode 25 or the drain electrode 26, and if the first electrode layer 6 needs to be connected with the source electrode 25, the bottom of the first hole 51 is the source electrode 25; if the first electrode layer 6 needs to be connected to the drain electrode 26, the bottom of the first hole 51 is the drain electrode 26.

After the formation of the planarization layer 5, a first electrode layer 6 is formed, and the structure is shown in fig. 4. Specifically, the electrode layer metal may be plated by sputtering or evaporation, and the first electrode layer 6 is formed by exposing, developing, etching, and stripping the electrode layer metal. The electrode layer metal may be a metal or a metal oxide, and for example, the metal oxide may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like. The first electrode layer 6 is connected to the source or the drain through the first hole, and the first electrode layer and the thin film transistor are connected. The thickness of the first electrode layer is 0.06um to 0.08 um. Preferably, the thickness of the first electrode layer is 0.075 um.

After the first electrode layer 6 is manufactured, the first pixel defining layer 7 is manufactured, and the structure is shown in fig. 5. The first pixel definition layer 7 is to define each individual sub-pixel unit of the display panel. The first pixel defining layer 7 covers the first electrode layer 6 and the planarization layer 5. And a second hole 72 is made on the first pixel defining layer 7, and the bottom of the second hole 72 is the first electrode layer 6. The second aperture 72 serves as a connection point between the first electrode layer 6 and the first light-emitting layer 71.

Similarly, the substrate is turned to the back side, and the second pixel defining layer 8 is formed on the back side of the substrate, as shown in fig. 5. And a third hole 82 is formed in the second pixel defining layer 8, the third hole 82 is connected to a through hole in the substrate, the third hole 82 exposes the second electrode layer 3, and the third hole 82 serves as a connection point between the second electrode layer 3 and the second light emitting layer 81.

Then, a first light-emitting layer 71 is formed in the second hole 72, the first light-emitting layer 71 is connected to the first electrode layer 6, a second light-emitting layer 81 is formed in the third hole 82, and the second light-emitting layer 81 is connected to the second electrode layer 3, as shown in fig. 6.

The first light-Emitting layer 71 may be a light-Emitting layer of an OLED (organic light-Emitting Diode) or a light-Emitting layer of a Mini LED. The second light-emitting layer 81 is the same as the first light-emitting layer 71. The light Emitting layer of the OLED makes the display panel an OLED display panel, which is also called an organic light-Emitting display (OLED) or an organic light-Emitting semiconductor. The luminescent layer of the Mini LED makes the display panel a Mini LED display panel. The Mini LED display panel has the advantages of high response speed, high-temperature reliability and long service life while maintaining excellent display effect and flexibility.

Referring to fig. 6, taking manufacturing the first light emitting layer 71 of the Mini LED as an example, the bead pins 711 of the first light emitting layer 71 of the Mini LED are bonded to the first electrode layer 6 by using the solder paste 9, and the first light emitting layer 71 is located in the second hole 72. The thin film transistor controls light emission of the first light-emitting layer 71 through the first electrode layer 6. At this time, the substrate of the first light emitting layer of the bound Mini LED is a screen with a display function.

Similarly, the bead pins 711 of the second light emitting layer 81 of the Mini LED are bound with the second electrode layer 3 by using the solder paste 9, and the second light emitting layer 81 is located in the third hole 82. The thin film transistor 2 controls light emission of the second light emitting layer 81 through the second electrode layer 3.

In a further embodiment, the third aperture is located below the area of the second aperture, and the first light emitting layer and the second light emitting layer are partially overlapping in a direction perpendicular to the front surface of the substrate such that the first light emitting layer and the second light emitting layer are aligned without a gap in a vertical direction.

Referring to fig. 5 and 6, in a further embodiment, when the second electrode layer 3 is manufactured, the second electrode layer in the hole region on the insulating layer is a hollow structure, the hollow region of the second electrode layer is a through hole on the second electrode layer, the through hole on the second electrode layer is communicated with the third hole 82 on the second pixel defining layer 8, and the through hole on the second electrode layer is further communicated with the third hole 82 on the back surface of the substrate. When the flat layer 5 is manufactured, the flat layer 5 is etched to form a fourth hole 52, the fourth hole 52 is communicated with the hollow area of the second electrode layer 3, and the second hole 72 is communicated with the fourth hole 52. Note that if a film layer of the buffer layer 27 is provided under the planarization layer, the fourth hole penetrates through the buffer layer 27 below until it communicates with the hollow region of the second electrode layer, and also communicates with the third hole 82 on the back surface of the substrate. The second hole 72 prepared later is connected with the fourth hole, and the solder paste 9 in the second hole 72 is also connected with the bottom of the second light emitting layer 81 through the fourth hole and the hollow area of the second electrode layer, thereby increasing the stability of the second light emitting layer 81.

In this embodiment, in order to protect the first light emitting layer and prevent water vapor and oxygen from contacting the first light emitting layer, an encapsulation layer is formed on the first pixel defining layer. The structure of the encapsulation layer is not shown in the figures. The encapsulation layer covers the first light emitting layer. Similarly, an encapsulation layer is manufactured on the second pixel definition layer, and the encapsulation layer covers the second light emitting layer. The encapsulation layer may be a transparent silicone gel.

In this embodiment, in order to reflect the light emitted from the second light emitting layer to the front surface of the substrate for light emission, a light reflecting layer 10 is formed on the second pixel defining layer 8, and the structure is as shown in fig. 6. The reflective layer 10 covers the second light emitting layer, the second pixel defining layer, the encapsulation layer, and the like. The material of the light reflecting layer is not limited to metals having reflectivity such as silver, copper, and foil, and the thickness thereof is in the range of 0.1um to 0.2um, preferably 0.15 um.

It should be noted that the first light emitting layer and the second light emitting layer may partially overlap or be next to each other in a direction perpendicular to the front surface of the substrate on the display panel to achieve gapless emission of light in the vertical direction.

In the technical scheme, the first light-emitting layer and the second light-emitting layer are driven to be lightened by the same thin film transistor, and the two light-emitting layers are respectively arranged on the front surface and the back surface of the substrate, so that gapless emission of light in the vertical direction is realized. The pixels of the two light emitting layers are overlapped, so that the resolution and the resolution of the display panel are increased, and the brightness of the display panel is improved. The technical scheme can also realize transparent display or double-sided display, and improve the competitiveness of the product.

Referring to fig. 1 to 6, the present embodiment further provides a display panel, which includes a substrate, a thin film transistor 2, a second electrode layer 3, a planarization layer 5, a first electrode layer 6, a first pixel definition layer 7, a first light emitting layer 71, a second pixel definition layer 8, and a second light emitting layer 81.

The substrate 1 is provided with a through hole 11, and the structure is shown in fig. 1. The through hole 11 on the substrate 1 communicates the front surface of the substrate 1 and the back surface of the substrate 1, and is used as a connection point of the second electrode layer 3 and the second light emitting layer. The cross section of the through hole 11 is in a shape of a circle, a triangle, a rectangle, a pentagon, etc.

The thin film transistor 2 is arranged on the front surface of the substrate and is structured as shown in fig. 1 and fig. 2. The insulating layer in the thin film transistor 2 is provided with a hole, and the hole in the insulating layer is communicated with the through hole in the substrate, so that the thin film transistor 2 is exposed out of the through hole in the substrate.

The second electrode layer 3 and the source electrode 25 in the thin film transistor 2 are disposed on the same layer, and the second electrode layer 3 is connected to the source electrode 25 or the drain electrode 26, and the structure is shown in fig. 2. The second electrode layer 3 extends to the back side of the substrate through the sidewall of the hole in the insulating layer and the sidewall of the through hole in the substrate, and then the second electrode layer 3 is located in the third hole 82. The second electrode layer 3, the source electrode 25 and the drain electrode 26 are all transparent to light, so that light emitted from the second light-emitting layer 81 located on the back surface of the substrate can be irradiated to the front surface direction of the substrate.

The flat layer 5 is disposed on the thin film transistor 2, and the flat layer 5 covers the thin film transistor 2 and the second electrode layer 3, and the structure is shown in fig. 3. The flat layer 5 has a certain thickness, and the upper surface of the flat layer 5 is a plane and parallel to the front surface of the substrate.

The first electrode layer 6 is disposed on the planarization layer 5, and the first electrode layer 6 is connected to the source electrode 25 or the drain electrode 26 through a first hole 51 on the planarization layer 5, as shown in fig. 4. The thickness of the first electrode layer is 0.06um to 0.08 um. Preferably, the thickness of the first electrode layer is 0.075 um.

The first pixel defining layer 7 is used for defining each independent sub-pixel unit of the display panel, and the first pixel defining layer 7 is arranged on the flat layer 5 and the first electrode layer 6, and the structure is shown in fig. 5. The first light emitting layer 71 is disposed in the second hole 72 of the first pixel defining layer 7, and the first light emitting layer 71 is connected to the first electrode layer 6 through the second hole 72, as shown in fig. 6.

Similarly, the second pixel defining layer 8 is disposed on the back surface of the substrate, and the structure is as shown in fig. 5. The second light emitting layer 81 is disposed in the third hole 82 of the second pixel defining layer, and has a structure as shown in fig. 6. The second light emitting layer 81 is connected to the second electrode layer 3 through a third hole 82.

The first light Emitting layer 71 may be a light Emitting layer of an OLED (organic light-Emitting Diode) or a light Emitting layer of a Mini LED. The second light-emitting layer is the same as the first light-emitting layer 71. The light Emitting layer of the OLED makes the display panel an OLED display panel, which is also called an organic light-Emitting display (OLED) or an organic light-Emitting semiconductor. The luminescent layer of the Mini LED makes the display panel a Mini LED display panel. The Mini LED display panel has the advantages of high response speed, high-temperature reliability and long service life while maintaining excellent display effect and flexibility.

Referring to fig. 6, taking the first light emitting layer 71 of the Mini LED as an example, the bead pins 711 of the first light emitting layer 71 of the Mini LED are bonded to the first electrode layer 6 by using the solder paste 9, and the first light emitting layer 71 is located in the second hole 72. The thin film transistor controls light emission of the first light-emitting layer 71 through the first electrode layer 6. The substrate of the first light emitting layer 71 of the Mini LED bonded at this time is a screen having a display function.

Similarly, the bead pins 711 of the second light-emitting layer of the Mini LED are bound with the second electrode layer 3 by using the solder paste 9, and the second light-emitting layer is located in the third hole 82. The thin film transistor controls the light emission of the second light emitting layer through the second electrode layer 3.

In this embodiment, in order to protect the first light emitting layer from water vapor and oxygen contacting the first light emitting layer, an encapsulation layer is further included. The packaging layer is arranged on the first pixel definition layer and covers the first light-emitting layer; or: the encapsulation layer is disposed on the second pixel defining layer, and covers the second light emitting layer.

In this embodiment, in order to reflect the light emitted from the second light emitting layer to the front surface of the substrate for light emission, a light reflecting layer 10 is further included, and the structure is shown in fig. 6. The reflective layer 10 covers the second light emitting layer, the second pixel defining layer, the encapsulation layer, and the like. The material of the light reflecting layer is not limited to metals having reflectivity such as silver, copper, and foil, and the thickness thereof is in the range of 0.1um to 0.2um, preferably 0.15 um.

In this embodiment, in order to irradiate the active layer with light, a light-shielding layer 4 is further included, and the structure is as shown in fig. 2. The light shielding layer 4 is arranged between the thin film transistor 2 and the flat layer 5, and the projection of the active layer in the thin film transistor is positioned in the projection of the light shielding layer 4, and the direction of the projection is vertical to the front surface of the substrate. The light shielding layer may be made of a light-impermeable material, such as metal, black resin, a light shielding tape, or the like. When light irradiates the active layer, the light is shielded by the light shielding layer, and the active layer is not irradiated by the light, so that the performance of the thin film transistor is ensured. The thickness of the light-shielding layer is 0.1um to 0.2 um. Preferably, the light-shielding layer has a thickness of 0.15 um.

Referring to fig. 5 and 6, in a further embodiment, the second electrode layer 3 in the hole region on the insulating layer is a hollow structure, the hollow region of the second electrode layer 3 is a through hole on the second electrode layer 3, the through hole on the second electrode layer is connected to the third hole 82 on the second pixel defining layer 8, and the through hole on the second electrode layer is further connected to the third hole 82 on the back surface of the substrate. When the flat layer 5 is manufactured, the flat layer 5 is etched to form a fourth hole 52, the fourth hole 52 is communicated with the hollow area of the second electrode layer 3, and the second hole 72 is communicated with the fourth hole 52. Note that if a film layer of the buffer layer 27 is provided under the planarization layer, the fourth hole penetrates through the buffer layer 27 below until it communicates with the hollow region of the second electrode layer, and also communicates with the third hole 82 on the back surface of the substrate. The second hole 72 is connected with the fourth hole, and the solder paste 9 in the second hole 72 is also connected with the bottom of the second light-emitting layer through the fourth hole and the hollow area of the second electrode layer, so that the stability of the second light-emitting layer is improved.

It should be noted that the display panel driven by the thin film transistor as a switch can achieve the characteristics of high speed, high brightness and high contrast. The thin film transistor may be a top gate structure or a bottom gate structure.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. A display panel is characterized by comprising a substrate, a thin film transistor, a second electrode layer, a flat layer, a first electrode layer, a first pixel defining layer, a first light emitting layer, a second pixel defining layer and a second light emitting layer;

2. The display panel according to claim 1, wherein the second electrode layer in the hole region of the insulating layer is a hollow structure, and a fourth hole of the flat layer is connected to the hollow region of the second electrode layer, and the second hole is connected to the fourth hole;

3. The display panel according to claim 1, further comprising an encapsulation layer provided on the first pixel defining layer, the encapsulation layer covering the first light emitting layer; or:

4. The display panel according to claim 1, further comprising a light reflecting layer covering the second light emitting layer and the second pixel defining layer.

5. The display panel according to claim 1, further comprising a light shielding layer disposed between the thin film transistor and the planarization layer, wherein a projection of the active layer in the thin film transistor is in a projection of the light shielding layer, and a direction of the projection is perpendicular to the front surface of the substrate.