CN214313214U - Integrated circuit system with super junction transistor mechanism - Google Patents

Abstract

An integrated circuit system comprising a discrete gate superjunction unit, the discrete gate superjunction unit comprising: a highly doped substrate comprising a first polarity; an epitaxial layer comprising the first polarity grown on the highly doped substrate; a stripe-shaped gate trench formed in the epitaxial layer; a stripe-shaped gate polysilicon layer formed in the stripe-shaped gate trench; a dot body implant comprising a second polarity implanted adjacent to the stripe gate trench opposite the stripe gate polysilicon layer; and a conductive column comprising the second polarity implanted in the center of the dot body implant and extending into the epitaxial layer.

Description

Integrated circuit system with super junction transistor mechanism

Technical Field

The present application relates to the field of semiconductor manufacturing, and more particularly to Metal Oxide Semiconductor (MOS) super junction power transistor structures.

Background

The development of voltage control mechanisms has progressed over time. For example, power supplies have evolved from 10 volts to 20 volts, and dc power supplies have evolved to 600 to 700 volts switching power supplies for commercial applications. During the development of high power devices, power transistors have also developed slowly. During development, several groups of intermediate voltage transistors switched in groups cause noise and reliability problems, since the switching characteristics of the individual transistors are not perfectly matched.

As semiconductor technology changes and geometries shrink, maintaining reliable and operable power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) may become more difficult. The high output capacitance and increased on-resistance make most power MOSFETs unsuitable for active switching applications.

Thus, there remains a need for an integrated circuit system having a superjunction transistor mechanism. In view of ever-increasing commercial competitive pressures, along with the growth in consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. In addition, the need to reduce cost, improve efficiency and performance, and meet competitive pressures adds greater urgency to the critical necessity to find answers to these questions.

Solutions to these problems have long been sought, but prior developments have not taught or suggested any solutions, and thus solutions to these problems have long eluded those skilled in the art.

SUMMERY OF THE UTILITY MODEL

One embodiment of the present application provides an integrated circuit system comprising a discrete gate superjunction unit comprising: a highly doped substrate comprising a first polarity; an epitaxial layer comprising a first polarity grown on a highly doped substrate; a stripe-shaped gate trench formed in the epitaxial layer; a stripe-shaped gate polysilicon layer formed in the stripe-shaped gate trench; a body implant comprising a second polarity implanted adjacent to the stripe gate trench opposite the stripe gate polysilicon layer; and a conductive column of a second polarity implanted in the center of the body implant and extending into the epitaxial layer.

Optionally, the stripe-shaped gate trenches in the epitaxial layer comprise a liner oxide layer on the inside of the stripe-shaped gate trenches.

Optionally, the stripe-shaped discrete gate structure is formed by a discrete polysilicon layer in the stripe-shaped gate trench, wherein the stripe-shaped gate polysilicon layer is above the discrete polysilicon layer.

Optionally, a stripe-shaped source contact implant centered over the conductive column on the dot body implant and in the active region.

Optionally, an oxide cap layer on the striped gate polysilicon layer and over the body implant.

Optionally, the striped gate trenches comprise a depth of 1.0 μm and a width of 0.45 μm +/-0.2 μm.

Alternatively, the conductive columns comprise a column depth of 2.0 μm and a column width of 0.5 μm, based on a 30V breakdown voltage.

Optionally, the conductive column is in a column trench and filled with a column epitaxial layer comprising the second polarity.

Optionally, a source metal is on the oxide cap layer and through the etched trenches in the oxide cap layer. Optionally, an active region and a termination region are included, wherein the termination region comprises an isolation space having a floating trench surrounding the active region.

Certain embodiments of the present application have other steps or elements in addition to or in place of those mentioned above. These steps or elements will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.

Drawings

Fig. 1 is a top plan view of an integrated circuit system having a superjunction transistor mechanism in an embodiment of the present application.

Fig. 2 is an example of a top plan view of the integrated circuit system in section 2-2 of fig. 1.

Fig. 3 is an exemplary cross section of the integrated circuit system along section line 3-3 of fig. 2.

FIG. 4 is an exemplary cross section of an integrated circuit system along section line 3-3 of FIG. 2 in an alternative embodiment of the present application.

Fig. 5 is an exemplary cross-section of a portion of a wafer after a stage of mask processing.

Figure 6 is an exemplary cross-section of a portion of a wafer after a stage of a trenching process.

Fig. 7 is an exemplary cross-section of a portion of a wafer after an oxide deposition processing stage.

Fig. 8 is an exemplary cross-section of a portion of a wafer after a polysilicon deposition and implantation processing stage.

Fig. 9 is an exemplary cross-section of a portion of a wafer after an ion implantation processing stage.

Fig. 10 is an exemplary cross-section of a portion of a wafer during a metal deposition processing stage.

Fig. 11 is a flow chart of a method of manufacturing an integrated circuit system including power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cells in an embodiment of the present application.

Detailed Description

The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the present application. It is to be understood that other embodiments will be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It may be evident, however, that the subject application may be practiced without these specific details. In order to avoid obscuring the present application, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the drawing figs. Where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.

For purposes of illustration, the term "horizontal" as used herein is defined as a plane parallel to the plane of the active surface of the top of the integrated circuit die, regardless of its orientation. The term "vertical" refers to a direction perpendicular to the horizontal as just defined. Terms such as "on …," "above …," "below …," "bottom," "top," "side" (as in "side wall," "upper," "lower," "upper," "above …," and "below …" are defined with respect to the horizontal plane.

The term "on …" as used herein means and refers to direct contact between elements without intervening elements. The term "processing" as used herein includes deposition, patterning, exposure, development, etching, cleaning, and/or removal or modification of materials as required in forming the described structures. The term "system" as used herein means and refers to the methods and apparatus of the present application in accordance with the context in which the term is used. The term "growth" as used herein refers to an additional thickness added by means of Chemical Vapor Deposition (CVD) or other deposition process. The term "center" or "centering" refers to positioning an element such that it is equidistant from the edge of another element.

It should also be understood that a noun or element in an embodiment may be described as a singular example. It is to be understood that the use of the singular is not limited to the singular, but that the singular uses a plurality of examples applicable to any particular noun or element in an application. The multiple instances may be the same or similar or may be different.

Referring now to fig. 1, shown therein is a top plan view of an integrated circuit system 100 having a superjunction transistor mechanism in an embodiment of the present application. The top plan view of the integrated circuit system 100 depicts the integrated circuit die 102, such as a super junction Metal Oxide Semiconductor Field Effect Transistor (MOSFET), before the source and gate metals are applied. The integrated circuit die 102 may include an active region 104 and a termination region 106 surrounding the active region 104.

The active region 104 may be defined as a primary current carrying region of the integrated circuit die 102. The active region 104 may provide a current path between a source metal (not shown) and a drain metal (not shown) to be applied opposite the source metal. Termination region 106 may provide an isolation space 114 and a gate metal region 116. The isolation space 114 may contain a stripe-shaped gate trench layer 112 that is isolated from the source metal and the gate metal that may cover regions in the finished device. The isolation space 114 may provide separation between voltages applied to the top of the integrated circuit die 102.

The gate pads 108 may be formed on the outer edge 109 of the integrated circuit die 102. The gate pad 108 may be a region that provides an electrical connection for the stripe-shaped gate trench layer 112. For example, the gate pad 108 is shown as being centered at the outer edge 109 of the integrated circuit die 102, but it should be understood that the gate pad 108 may be placed anywhere along the outer edge 109 of the integrated circuit die 102. The active region 104 may include an array of interconnect metals 110 and an array of striped gate trench layers 112. Termination region 106 may include a striped gate trench layer 112 and no interconnect metal 110 is present. It should be understood by one of ordinary skill in the art that the termination region 106 encompasses the outer edge 109 of the integrated circuit die 102 to surround the active region 104. The interconnect metal 110 may provide electrical connections between an array of source implants (not shown) that will be described below.

The relationship of the active region 104 and the termination region 106 will be further explained in fig. 2 by means of section 2-2 shown on the outer edge 109 of the integrated circuit die 102. Cross section 2-2 is merely an example since termination region 106 surrounds active region 104.

As an example, the integrated circuit die 102 may include a source contact metal (not shown) and a gate metal (not shown) on the gate pad 108 applied in the active region 104 and around the outer edge 109 of the integrated circuit die 102 with an isolation space 114 between the source metal and the gate metal.

Referring now to FIG. 2, there is shown an example of a top plan 201 view of integrated circuit system 100 in section 2-2 of FIG. 1. The top plan view 201 of the integrated circuit system 100 in cross-section 2-2 depicts the termination region 106, which includes the isolation space 114 adjacent to the active region 104. The termination region 106 may extend to an outer edge 109.

An epitaxial layer 202 comprising a first polarity, such as an N-type doping polarity, may comprise an array of spot column implants 204 having a second polarity of a P-type doping polarity. By way of specific example, the dot column implant may be a P-type implant that extends into an N-type epitaxial layer. The dot column implants 204 may be formed as an array across the active region 104 and the termination region 106. The isolation space 114 may include a plurality of floating trenches 206 housed therein. For example, three or more of the floating trenches 206 may fit within the isolation space 114. It is understood that any number of floating trenches 206 may be designated within isolation space 114.

The number of floating trenches 206 formed within the isolation space may depend on the target voltage range of the integrated circuit die 102 of figure 1. For example, if the integrated circuit die 102 is to operate at up to 25 volts, a single one of the floating trenches 206 may be implemented. Two of the floating trenches 206 may be implemented if the integrated circuit die 102 is to operate between 30 volts and 40 volts. As the voltage capacity of the integrated circuit die 102 increases, additional floating trenches 206 may be added so that three of the floating trenches 206 may support a range between 60 volts and 250 volts. Higher voltages would require additional instances of floating trench 206.

As an example, floating trenches 206 are formed in epitaxial layer 202 with a width of 0.45 μm with a tolerance of 0.2 μm. Also, the floating trench 206 may be formed at a depth of about 1.0 μm by a dry etching process, for example. Continuing with the example, floating trenches 206 may be constructed or formed in the same or similar manner as stripe-shaped gate trench layer 112. For example, floating trenches 206 are not connected to a voltage source or to each other and perform an isolation function to surround active region 104.

As an example, the active region 104 may include a plurality of stripe-shaped gate trench layers 112 formed between columns of dot column implants 204. The striped gate trench layer 112 may be constructed in similar size to the floating trenches 206, but the connection of the striped gate trench layer 112 may be different because the striped gate trench layer 112 may be designed to carry a gate voltage that may be provided by a gate metal, as will be discussed later.

In this example, the dot column implants 204 located in the active region 104 may be coupled into columns by stripe-shaped source contacts 208 of a second polarity that include a higher concentration, such as P +. The stripe-shaped source contact 208 may be coupled to a source metal (not shown). The relationship of the elements in fig. 3 is illustrated by section line 3-3. For example, the dot column implants 204 are shown in a distinct rectangular shape, but the shape may also be a circular shape, an elliptical shape, or a rounded rectangle, and does not alter the present application.

It has been found that the size of the isolation region 114 can be adjusted to accommodate the number of floating trenches 206, such as super junction Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), needed to support a target voltage for the integrated circuit die 102. Since the construction of the striped gate trench layers 104 and the floating gates 206 is the same, the target operating voltage can be tailored by applying the source metal in the final fabrication steps. The ability to customize the integrated circuit die 102 in the final manufacturing step may save time and money for the manufacturing process and allow different target voltages to be generated from the same semiconductor wafer, improving the manufacturing process.

Referring now to FIG. 3, an exemplary cross section 301 of integrated circuit system 100 along section line 3-3 of FIG. 2 is shown. In this example, cross section 301 of integrated circuit system 100 depicts two of discrete gate superjunction cells 302 in active area 104 of fig. 1. The construction of a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell including the fabrication of discrete gate superjunction cell 302 is described below. The discrete gate superjunction cell 302 may be considered a MOSFET 302 and will be recognized by those skilled in the art.

In this example, a heavily doped substrate 304 including a first polarity 306 may be provided at 2.2 x 10 per cubic centimeter, for example¹⁹To 7.2X 10¹⁹Dopant concentration within the range of (a). The heavily doped substrate 304 may be covered by forming an epitaxial layer 308 comprising a first polarity 306 on the heavily doped substrate 304. Stripe-shaped gate trenches 310 formed in epitaxial layer 308 may be lined with a liner oxide layer 312, which acts as an insulator. Stripe-shaped polysilicon layer 314, such as heavily doped polysilicon of first polarity 306, may be formed to encloseStripe-shaped polysilicon layer 314. A stripe-shaped gate polysilicon layer 318 may be formed over the stripe-shaped polysilicon layer 314, acting as a gate for the stripe-shaped discrete gate structure 316. The stripe-shaped gate polysilicon layer 318 may be formed of heavily doped polysilicon of the first polarity 306.

Body implants 320 of a second polarity 322 may be implanted between two instances of the stripe-shaped gate trenches 310. A conductive column 324 of the second polarity 322 may be formed centrally between two instances of the stripe-shaped gate trench 310 and include a depth at least twice the depth of the stripe-shaped gate trench 310. As a specific example, the conductive columns 324 may be P-type columns. Additional details of the construction are described in subsequent figures.

The stripe-shaped source contact implant 326 may be formed from an ion implant in the body implant 320. The source region 328 may be formed from an ion implant on the silicon surface 330. The oxide cap layer 332 may be formed of borophosphosilicate glass (BPSG) or Low Temperature Oxide (LTO) by deposition on top of the stripe-shaped gate polysilicon layer 318.

A source metal 334, such as aluminum (Al), copper (Cu), may be applied directly on the stripe-shaped source contact implants 326 and the oxide cap 332. The stripe polysilicon layer 314 may be a field plate electrically connected to the source metal 334 for improving drain-to-source breakdown voltage (BVdss), gate charge, and gate-to-drain charge reduction for faster switching of the MOSFET 302. The drain metal 336, which may comprise titanium (Ti), nickel (Ni), silver (Ag), combinations or alloys thereof, may be applied to the heavily doped substrate 304.

It has been found that discrete gate superjunction cells 302 can provide faster switching, higher Breakdown Voltage (BV), and low conduction resistance (Rdson) based on the discrete gate superjunction build and the presence of conductive columns 324. It is understood that the first polarity 306 is shown as being N-type doped silicon and the second polarity is shown as being P-type doped silicon, but may be reversed without altering the present application. The discrete gate superjunction cells 302 may also provide an improved linear mode of operation, as the conductive columns 324 provide additional voltage blocking capability. It should also be understood that the conductive columns 324 may be formed as a dot or stripe implementation and do not change function.

Referring now to FIG. 4, shown therein is an exemplary cross section 401 of the integrated circuit system 100 along section line 3-3 of FIG. 2 in an alternative embodiment of the present application. In this example, the cross-section of the integrated circuit system 100 depicts two of the stripe-shaped gate cells 402 in the active region 104 of fig. 1.

In this example, stripe gate cells 402 may be formed similar to discrete gate superjunction cells 302. Continuing with this example, stripe-shaped gate cells 402 may also be formed without depositing stripe-shaped polysilicon layer 314 of fig. 3. For example, the location of the stripe-shaped gate polysilicon layer 318 is determined by filling the space within the stripe-shaped gate trench 310 with the liner oxide layer 312. Liner oxide layer 312 is etched back 0.6 μm below silicon surface 330 before stripe gate polysilicon layer 318 is deposited to fill stripe gate trenches 310.

It has been found that strip gate cells 402 can provide faster switching, higher Breakdown Voltage (BV), and low conduction resistance (Rdson) based on the discrete gate superjunction cell 302 construction and the presence of conductive columns 324. It is understood that the first polarity 306 is shown as being N-type doped silicon and the second polarity is shown as being P-type doped silicon, although the first and second polarities may be reversed. The striped gate cells 402 may also provide an improved linear mode of operation since the conductive columns 324 provide additional voltage blocking capability.

Referring now to fig. 5, an exemplary cross-section of a wafer portion 501 after a stage of mask processing is shown. An exemplary cross-sectional depiction of wafer portion 501 depicts that heavily doped substrate 304 including first polarity 306 may be covered by epitaxial layer 308 also including first polarity 306.

The mask layer 502 may be patterned on the surface of the epitaxial layer 308 opposite the heavily doped substrate 304. In this example, mask layer 502 may be formed from a 3000 angstrom oxide deposition formed by CVD. The mask layer may define the exposed regions of epitaxial layer 308 to be exposed in the next processing step.

Referring now to fig. 6, an exemplary cross-section of a wafer portion 601 after a trenching processing stage is shown. In this example, a cross-section of the wafer portion 601 depicts an epitaxial layer 308, the epitaxial layer 308 including an array of striped gate trenches 310 formed therein.

As an example, the stripe-shaped gate trenches 310 may be formed through a dry etching process that tightly controls the size of the stripe-shaped gate trenches 310. Also, stripe-shaped gate trenches 310 may include a depth 602 of substantially 1.0 μm and a width 604 of 0.45 μm +/-0.2 μm, for example. The depth 602 and width 604 allow the next processing stage to be performed.

Referring now to fig. 7, an exemplary cross-section of a wafer portion 701 after an oxide deposition processing stage is shown. In this example, the cross-section of wafer portion 701 depicts liner oxide layer 312 grown to a thickness 702 of 0.1 μm on the interior portions of stripe-shaped gate trenches 310.

As an example, source region 104 and liner oxide layer 312 in the isolation space are coated in the same manner. Also, for example, the size of the liner oxide layer 312 leaves an opening 704 of 0.10 μm to 0.50 μm within the stripe-shaped gate trench 310.

Referring now to fig. 8, an exemplary cross-section of a wafer portion 801 after a polysilicon deposition and implantation processing stage is shown. In this example, the cross-section of wafer portion 801 depicts a striped polysilicon layer 314 that includes a liner oxide layer 312 that may be deposited and etched back 0.60 μm, leaving a polysilicon layer depth 802 of 0.15 μm. Also, for example, liner oxide layer 312 may be deposited by CVD to fill stripe-shaped gate trenches 310 and then etched back to 0.6 μm to provide a dielectric thickness 804 of 0.15 μm over stripe-shaped polysilicon layer 314.

As an example, stripe gate polysilicon layer 318 may be deposited to fill stripe gate trenches 310 and etched back to silicon surface 330, leaving a second polysilicon layer with a depth of 0.6 μm. Continuing with the example, body implants 320 can be implanted in silicon surfaces 330 between instances of striped gate trenches 310, including using 1e¹³/cm²A second polarity 322 of the dose of boron. After the body implant 320, a furnace process may be applied for driving the body implant 320 to a body drive-in depth 806 of, for example, 0.50 um. The source layer 808 may be implanted over the body implant 320. The source layer 808 may have 4e¹⁵/cm²To form the source layer 808. Can be used forA body drive-in process is performed in a 900 ℃ furnace process or Rapid Thermal Annealing (RTA) for forming source and body contacts 810. After the body drive-in process, an oxide cap layer 332 may be formed of LTO/BPSG oxide, which may be deposited on silicon surface 330 at a thickness of 0.3 μm to 0.6 μm.

Referring to fig. 9, an exemplary cross-section of a wafer portion 901 after an ion implantation processing stage is shown. The stripe-shaped source contact implants 326 may be accessed by etching trenches 902, the trenches 902 may be formed by dry etching of the capping layer oxide 332 and the source layer 808.

In this example, the cross-section of the wafer portion 901 depicts the formation of the conductive columns 324, which may be centered in the body implant 912 by etching trenches 902. A conductive column 324 including a second polarity 322 may be implanted. For example, the implantation process may use 1e at five steps of implantation energy (e.g., 300keV/600keV/1MeV/1.5MeV/2.0MeV)¹³/cm²A dose of boron. As a specific example, the purpose is to connect the P-type columns to the P-type body ties. Further, for example, the resulting conductive columns 324 extend below the body implants 320 and into the epitaxial layer 308 to form a column depth 904 of substantially 2.0 μm, and have a column width 906 of substantially 0.5 μm.

After forming the etching trench 902, 4e¹⁵/cm²A source implant process is performed at a first polarity 306 of the dose to form stripe-shaped source contact implants 326. The etched trench 902 may then be formed to a depth of substantially 0.30 μm by a dry etch process of BPSG/LTO and silicon. The stripe-shaped source contact implants 326 may be implanted by etching trenches 902. The stripe contact implant 914 is of a second polarity 322 with a heavy dose. Also, for example, strip contact implant 914 may be formed by implanting 1e¹⁵/cm²The dose implant BF2 was formed and could be activated by a furnace process or a Rapid Thermal Anneal (RTA) process.

In alternative embodiments and examples, conductive columns 324 may be formed by performing a dry etch of trenches 908 in epitaxial layer 308 and filling the trenches with column epitaxial layers 910 of second polarity 322. As a specific example, the dry etched trenches 908 can be filled with a P-type epitaxial layer to form P-type column epitaxial layers 910. As an example, embodiments may be used for medium voltage (60V to 250V) and high voltage devices operating above 250 volts.

It has been found that the conductive column 324 or column epitaxial layer 910 can reduce the drain/source conduction resistance (Rdson) to allow high voltage blocking capability and improve the linear mode of operation. For higher voltage devices, the column depth 904 may be increased. For example, the integrated circuit die 102 of FIG. 1 operating at less than 40V may utilize a column width 906 of substantially 0.5 μm and a column depth 904 of substantially 2.0 μm. The integrated circuit die 102 may operate in a medium voltage range (60V to 250V) to a high voltage range (e.g., above 600V). For medium voltages (60V to 250V), the column width 906 is in the range of 0.5 μm to 2 μm and the column depth 904 is in the range of 2.0 μm to 15 μm. For high voltages (600V to 650V and higher), the column width is in the range of 2.0 μm to 6.0 μm, and the column depth is in the range of 40 μm to 60 μm.

Referring now to fig. 10, an exemplary cross-section of a wafer portion 1001 is shown at a metal deposition processing stage. In this example, the cross-section of wafer portion 1001 depicts an oxide cap layer 332 that may be formed of LTO/BPSG oxide deposited on silicon surface 330.

The source metal 334 may be deposited into the etched trenches 902 to couple the source metal 334 to the strip contact implants 326. A source metal 334, such as aluminum (Al), copper (Cu), or alloys thereof, may be deposited over the oxide cap 332, the etched trenches 902, and the strip contact implants 326. Heavily doped substrate 304 may be exposed for deposition of drain metal 336, such as nickel (Ni), silver (Ag), copper (Cu), or alloys thereof.

The columns having the second polarity may also be stripe shaped. In the present application, the gate trench may also be a closed-cell type.

A source metal 334, such as aluminum (Al), copper (Cu), or alloys thereof, may be deposited over the oxide cap 332, the etched trenches 902, and the strip contact implants 326. Heavily doped substrate 304 may be exposed for deposition of drain metal 336 such as nickel (Ni), silver (Ag), copper (Cu), or alloys thereof.

Referring now to FIG. 11, therein is shown a flow chart of a method 1100 of manufacturing the integrated circuit system 100 in an embodiment of the present application. The method 1100 comprises: manufacturing discrete gate superjunction cells providing a highly doped substrate comprising a first polarity in block 1102; growing an epitaxial layer comprising a first polarity on a highly doped substrate in block 1104; forming stripe-shaped gate trenches in the epitaxial layer in block 1106; implanting a body implant comprising a second polarity adjacent to the stripe gate trench opposite the stripe gate polysilicon layer in block 1108; and implanting a conductive column including a second polarity and extending into the epitaxial layer in a center of the body implant in block 1110.

The resulting methods, processes, apparatuses, devices, products, and/or systems are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacture, application, and utilization. Another important aspect of embodiments of the present application is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.

These and other valuable aspects of the embodiments of the present application thus push the state of the art at least to the next level.

While the present application has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims (10)

1. An integrated circuit system, comprising:

a discrete gate superjunction cell comprising:

a highly doped substrate comprising a first polarity;

an epitaxial layer comprising the first polarity grown on the highly doped substrate;

a stripe-shaped gate trench in the epitaxial layer;

a strip-shaped grid polycrystalline silicon layer in the strip-shaped grid groove;

a body implant comprising a second polarity adjacent to the stripe gate trench opposite the stripe gate polysilicon layer; and

a conductive column including the second polarity in a center of the body implant and extending into the epitaxial layer.

2. The system of claim 1, wherein the stripe-shaped gate trenches in the epitaxial layer comprise a liner oxide layer on an interior of the stripe-shaped gate trenches.

3. The system of claim 1, comprising a striped discrete gate structure through a discrete polysilicon layer in the striped gate trench, wherein the striped gate polysilicon layer is over the discrete polysilicon layer.

4. The system of claim 1, comprising a stripe shaped source contact implant on a dot body implant and centered over the conductive column in an active region.

5. The system of claim 1, comprising an oxide cap layer on the striped gate polysilicon layer and over the body implant.

6. The system of claim 1, wherein the striped gate trenches comprise a depth of 1.0 μ ι η and a width of 0.45 μ ι η +/-0.2 μ ι η.

7. The system of claim 1, wherein the conductive columns comprise a column depth of 2.0 μ ι η and a column width of 0.5 μ ι η based on a 30V breakdown voltage.

8. The system of claim 1, wherein the conductive column is in a column trench and filled with a column epitaxial layer comprising the second polarity.

9. The system of claim 5, comprising a source metal on an oxide cap layer and through an etched trench in the oxide cap layer.

10. The system of claim 1, comprising an active region and a termination region, wherein the termination region comprises an isolation space having a floating trench surrounding the active region.

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