CN214175092U - Computer control board realized based on SW3231 processor - Google Patents
Computer control board realized based on SW3231 processor Download PDFInfo
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- CN214175092U CN214175092U CN202023146941.6U CN202023146941U CN214175092U CN 214175092 U CN214175092 U CN 214175092U CN 202023146941 U CN202023146941 U CN 202023146941U CN 214175092 U CN214175092 U CN 214175092U
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Abstract
The utility model discloses a computer control panel based on SW3231 treater is realized, relate to computer technology field, this computer control panel realizes based on SW3231 treater, memory granule chip is connected respectively to the memory interface of SW3231 treater, realize board-mounted memory design, the PCIE interface is drawn forth to the treater and is connected to PCIE bus extension chip, the USB interface is drawn forth through all kinds of conversion chips to PCIE bus extension chip, RJ45 giga network interface, the VGA interface, SATA interface and DB9 serial ports, this computer control panel carries out supporting design to SW3231 treater and peripheral interface circuit, all kinds of interfaces that actually required are provided, the JTAG interface that the program file of being convenient for burns out is still designed, therefore, the clothes hanger is strong in practicability.
Description
Technical Field
The utility model belongs to the technical field of the computer technology and specifically relates to a computer control panel based on SW3231 treater is realized.
Background
The computer technology is one of the fastest developing scientific technologies in the world, products are continuously upgraded and updated, the current computer hardware products are mainly represented by Intel, generally, computer control boards of safety equipment are basically processors and north-south bridge chips of foreign brands, an open structure is adopted, and non-safety factors such as calculation, reliability, power consumption and the like are mainly considered, so that a plurality of security holes exist in the processors, and lawless persons can easily implant monitoring and monitoring devices to steal national secret information, such as a series of security threats including computer technical defects, viruses, information waste, hackers, information lassos and the like. With the further development of informatization in China, the information security problem is increasingly emphasized, and a computer control board for bearing information security is particularly important for ensuring information security, so that the requirement on a domestic hardware platform is more and more urgent.
SUMMERY OF THE UTILITY MODEL
The present inventor has proposed a computer control panel based on the realization of the SW3231 processor, aiming at the above problems and technical requirements, the technical solution of the present invention is as follows:
a computer control board implemented based on a SW3231 processor, the computer control board comprising:
8 DDR4 memory interfaces with 64-bit data width of the SW3231 processor correspond to 8 built-in DDR4 memory controllers supporting ECC check respectively, and the 8 DDR4 memory interfaces of the SW3231 processor are connected with the memory granule chip respectively; the SW3231 processor is also connected with a CPLD chip, the SW3231 processor is also connected with a FLASH chip to realize an onboard 128G SSD hard disk, and the SW3231 processor is also connected with a DB9 serial port externally provided by a computer control board;
two groups of PCIEX4 interfaces of the SW3231 processor and two groups of PCIEX8 interfaces split by one group of PCIEX16 interfaces are respectively connected to PICE3.0X4 interfaces of 4 PCIEX interface connectors externally provided by the computer control board;
one group of PCIEX8 interfaces split from the other group of PCIEX16 interfaces of the SW3231 processor are connected to the PCIE bus expansion chip;
the PCIE bus expansion chip is connected with the PCIE-to-USB chip to output a USB signal to the computer control board to provide a USB3.0 interface;
the USB-to-multifunctional interface chip is connected with the PCIE-to-USB chip to convert USB signals into serial port signals and JTAG signals, the serial port signals are output to RS232 serial ports of 4 PCIE interface connectors externally provided by the computer control board, and the JTAG signals are output to JTAG interfaces of 4 PCIE interface connectors externally provided by the computer control board;
the PCIE bus expansion chip is connected with the output signal of the PCIE-to-MDI chip and an RJ45 kilomega network interface provided by the computer control board;
the PCIE bus expansion chip is connected with the PCIE-SATA chip to output signals to an SATA3.0 interface provided by the computer control board;
the PCIE bus expansion chip is connected with the PCIE to VGA chip and is connected with a VGA interface provided by the computer control board.
The further technical scheme is that each DDR4 memory interface of the SW3231 processor is respectively connected with 4 memory particle chips, 40 memory particle chips of X16 particles are arranged in a computer control board, the capacity of each memory particle chip is 1GB, and the computer control board is loaded with 32GB memory.
The further technical scheme is that the memory particle chip adopts MT40A512M16 HA-062E.
The further technical scheme is that the computer control board provides 6 USB3.0 interfaces externally, the PCIE-to-USB chip comprises two uPD720201 chips which provide 8 paths of USB signals, the 6 paths of USB signals are respectively connected to the 6 USB3.0 interfaces, and the rest 2 paths of USB signals are connected to the USB-to-multifunctional interface chip to form 4 paths of serial signals and 4 paths of JTAG signals.
The further technical scheme is that the USB-to-multifunctional interface chip comprises two FT4232HL chips, and each FT4232HL chip is respectively connected with one path of USB signal to be converted into 2 paths of serial port signals and 2 paths of JTAG signals.
The technical scheme is that each FT4232HL chip is further connected with two MAX232 chips and two SN74AVCH4T245 chips, each path of serial port signal generated by each FT4232HL chip is output to an RS232 serial port of one path of PCIE interface connector through the MAX232 chip, and each path of JTAG signal generated by each FT4232HL chip is output to a JTAG interface of one path of PCIE interface connector through the SN74AVCH4T245 chip.
The further technical scheme is that the SATA3.0 interface provided by the computer control board comprises an mSATA interface and a 7-pin SATA, the PCIE-to-SATA chip is an 88SE9215 chip, and the 88SE9215 chip is also connected with a FLASH chip.
The further technical scheme is that the PCIE-to-VGA chip is an SM750 chip, a DDR interface of the SM750 chip is also connected with 4 DDR SDRAM chips, and the total capacity of the 4 DDR SDRAM chips is 64 MB.
The further technical scheme is that the computer control board provides two RJ45 gigabit network interfaces, the PCIE-to-MDI chip comprises two I210 chips, each I210 chip is connected to one RJ45 gigabit network interface, and each I210 chip is also connected to a FLASH chip.
The computer control panel further comprises a reset switch, a power indicator, a hard disk indicator and a buzzer.
The utility model has the beneficial technical effects that:
the application discloses computer control panel based on SW3231 treater realization to having carried out supporting design to its peripheral interface circuit, having provided the all kinds of interfaces of actual required, still designed the JTAG interface that is convenient for program file to write, the practicality is strong, provides the control function of host computer, effectively reduces information security hidden danger, but wide application in information security field such as trade such as space flight and aviation, intelligent transportation, electric power railway.
Drawings
FIG. 1 is a block diagram of the overall design of the computer control board of the present application.
Fig. 2 is a block diagram of the design of the memory portion of the computer control board of the present application.
Fig. 3 is a block diagram of a design of a PCIE bus portion in a computer control board of the present application.
Fig. 4 is a block diagram showing the design of the USB interface portion of the computer control board of the present application.
FIG. 5 is a block diagram of the design of the RS232 serial port and JTAG interface portion of the computer control board of the present application.
Fig. 6 is a block diagram showing the design of the SATA interface portion in the computer control board of the present application.
Fig. 7 is a block diagram of the design of the RJ45 gigabit network interface portion of the computer control board of the present application.
Fig. 8 is a block diagram showing the design of the VGA interface section in the computer control board of the present application.
Fig. 9 is a schematic diagram of power supply in the computer control board of the present application.
FIG. 10 is a schematic diagram of the power-up sequence of the computer control board of the present application.
Detailed Description
The following describes the embodiments of the present invention with reference to the accompanying drawings.
The application discloses a computer control panel realized based on a SW3231 processor, please refer to the general design block diagram shown in FIG. 1, the computer control panel includes the following main components: the device comprises a SW3231 processor, a memory particle chip, a CPLD chip, a FLASH chip, a PCIE bus expansion chip, a PCIE-to-USB chip, a USB-to-multifunctional interface chip, a PCIE-to-MDI chip, a PCIE-to-SATA chip and a PCIE-to-VGA chip.
The interface provided by the computer control board mainly comprises: 4 PCIE interface connectors, USB3.0 interfaces, RJ45 gigabit network interfaces, VGA interfaces, SATA3.0 interfaces and DB9 serial ports.
The computer control board has the following scheme design:
(1) memory scheme design
8 DDR4 memory controllers are integrated in the SW3231 processor, each DDR4 memory controller corresponds to 1 DDR4 memory interface with 64-bit data width, 8-bit ECC check is supported, and the transmission rate can reach 3200 Mbps. 8 DDR4 memory interfaces of the SW3231 processor are respectively connected with the memory particle chip. In order to fully utilize the CPU memory bandwidth, the present application adopts an 8-channel single RANK scheme design, and adopts memory granule chips of X16 granules, the capacity of the single memory granule chip is 1GB, 40 memory granule chips are built in a computer control board, each DDR4 memory interface is connected to 4 memory granule chips, as shown in fig. 2, the entire computer control board realizes 32GB memory. The memory particle chip in this application uses MT40a512M16 HA-062E.
(2) PCIE scheme design
The SW3231 processor integrates a maximum of 6 PCIE interfaces conforming to the 4.0 standard and downward compatible with the 3.0/2.0 standard, and has 4 sets of PCIE interfaces by default, two sets (PE0 and PE2) being x16 interfaces and two sets (PE1 and PE3) being x4 interfaces.
According to the application, each group of PCIEX16 interfaces is respectively split into two groups of PCIEX8 interfaces according to PCIE interfaces of 6 RC split processors, wherein the two groups of PCIEX4 interfaces and the two groups of PCIEX8 interfaces split by the group of PCIEX16 interfaces are respectively connected to PICE3.0X4 interfaces of 4 PCIEX interface connectors externally provided by a computer control board, as shown in FIG. 3, one group of PCIEX8 interfaces split by the other group of PCIEX16 interfaces are connected to a PCIEX bus expansion chip, and the other group of PCIEX8 interfaces are not used. The PCIE bus expansion chip in the application adopts a PEX8619 chip.
(3) And designing a USB interface scheme.
The PCIE bus expansion chip is connected with the PCIE-to-USB chip to output USB signals to the computer control board to provide a USB3.0 interface externally. The computer control board of this application provides 6 USB3.0 interfaces outward, and the PCIE changes USB chip includes that two uPD720201 chips provide 8 way USB signals altogether, and wherein 6 way USB signals are connected to 6 USB3.0 interfaces respectively, as shown in FIG. 4.
(4) RS232 serial port and JTAG interface scheme design.
The USB-to-multifunctional interface chip is connected with the PCIE-to-USB chip to convert USB signals into serial port signals and JTAG signals, the serial port signals are output to RS232 serial ports of 4 PCIE interface connectors externally provided by the computer control board, and the JTAG signals are output to JTAG interfaces of the 4 PCIE interface connectors externally provided by the computer control board. As described above, two uPD720201 chips can provide 8 paths of USB signals, while the USB3.0 interface only uses 6 paths of USB signals, and the rest 2 paths of USB signals are connected to the USB-to-multifunctional interface chip to form 4 paths of serial signals and 4 paths of JTAG signals. The USB-to-multifunctional interface chip comprises two FT4232HL chips, each path of USB signals is connected to one FT4232HL chip, and each FT4232HL chip converts one path of USB signals into 2 paths of serial signals and 2 paths of JTAG signals respectively.
In this application, the level required by the JTAG interface is 2.5V, and the JTAG level converted by the FT4232HL chip is 3.3V, so in this application, as shown in fig. 5, each FT4232HL chip is further connected to two MAX232 chips and two SN74AVCH4T245 chips, each serial port signal generated by each FT4232HL chip is output to the RS232 serial port of one PCIE interface connector through the MAX232 chip, each serial port signal of each FT42 4232HL chip is output to the JTAG interface of one PCIE interface connector through the SN74AVCH4T245 chip, and the SN74AVCH4T245 chip is a level conversion chip which converts 3.3V output by the FT4232HL chip into 2.5V and connects to the PCIE interface connector.
(5) And designing a SATA interface scheme.
The PCIE bus expansion chip is connected with the PCIE-SATA chip to output signals to an SATA3.0 interface provided by the computer control board. The SATA3.0 interface provided by the computer control board externally comprises a mSATA interface and a common 7-pin SATA, wherein the mSATA interface is led out through a socket AS0B226-S68Q-7H, and the common 7-pin SATA is led out through a socket LD 1807V-S51P. The PCIE-to-SATA chip used in the present application is an 88SE9215 chip, which is connected to 2 SATA3.0 interfaces, as shown in fig. 6. The 88SE9215 chip is also connected with a FLASH chip, the speed is 6Gbps, the SSD supporting capacity is 128GB, and the storage type adopts MLC NAND FLASH.
(6) And designing an Ethernet scheme.
The PCIE bus expansion chip is connected with the output signal of the PCIE-to-MDI chip and an RJ45 gigabit network interface externally provided by the computer control board. The computer control board of the application provides two RJ45 gigabit network interfaces externally, the PCIE-to-MDI chips used include two I210 chips, each I210 chip is connected to one RJ45 gigabit network interface, as shown in fig. 7, each I210 chip is also connected to a FLASH chip, and a firmware for implementing a copper interface is programmed, so that the computer control board provides 2 channels of 10/100/1000 self-adaptive interfaces.
(7) And displaying the interface scheme design.
The computer control board integrates a display card, and a PCIE bus expansion chip is connected with a PCIE-to-VGA chip and connected with a VGA interface of 1 channel DB15 externally provided by the computer control board. The PCIE-to-VGA chip used in the present application is an SM750 chip, the display memory adopts an external memory, the DDR interface of the SM750 chip is further connected to 4 DDR SDRAM chips, and the total capacity of the 4 DDR SDRAM chips is 64MB, as shown in fig. 8.
Besides, the SW3231 processor is connected with a CPLD chip through an own Lpc/IIC/DCOK/RST port, wherein the CPLD chip used in the application is EPM1270F256C 5N. The SW3231 processor is also connected with a FLASH chip to realize an onboard 128G SSD hard disk, and the FLASH chip used in the application is W25Q16 JVSSG. The SW3231 processor is also connected to a DB9 serial port externally provided by the computer control board through an RS232 port of the SW3231 processor. In addition, this computer control panel still provides reset switch, power indicator, hard disk pilot lamp and bee calling organ etc. these are the comparatively conventional subassembly of current computer control panel, and this application no longer introduces implementation scheme in detail.
(8) And designing a power supply scheme.
The power supply of the computer control board is single 12V power supply, 12V is fed in through four PCIE interface connectors, wide voltage 14V-15V input can be supported, the voltage required by each part is converted through a power management chip, the power management chip used in the method mainly comprises a TPS53319 chip, a ZDO 1117-ADJ chip, an AOZ1232 chip, an RT9059 chip, an ISL8225 chip, a TPS51200 chip, an MP2888A chip and an MP86945A chip, the block diagram of the power supply scheme is shown in FIG. 9, and the power consumption of a mainboard is less than or equal to 200W. Based on the circuit scheme shown in fig. 9, the present application introduces the power-on timing sequence of the computer control board as follows, please refer to the timing diagram of fig. 10:
after the power is supplied by the mainboard single power supply 12V, the standby machines 5V, 3.3VSB and 1.8VSB are directly output, at the moment, the CPLD chip works normally, when the power switch on the mainboard is pressed, a low-level pulse width signal CPLD _ PSIN can be generated to be sent to the CPLD chip, the CPLD chip generates an enabling signal CPLD _ PSON for the subsequent power module to work, the enabling signal CPLD _ PSON drives the power chip TPS53319 to generate a 3.3V power supply, and a 3.3V Powergood signal is sent to the CPLD chip. After the PG signal of 3.3V is effective, the CPLD chip outputs a driving signal to enable 2 TPS53319 and RT9059 to generate voltages of 2.5V, 1.8V and 1.1V respectively, and PG signals corresponding to the three power supply modules are output to the CPLD. After the PG signal of 1.8V is valid, the CPLD outputs a driving signal to respectively enable the AOZ1232, the TPS53355 and the RT9059 to generate 1V, 1.2V (cpu) and 1.2V (SM750), and PG signals corresponding to 3 power modules are output to the CPLD chip. After the PG signal of 1.2V is effective, the CPLD outputs a driving signal to enable TPS51200 and ISL68127 multiphase power supplies to generate 0.6V and 0.75V respectively, and PG signals corresponding to 2 power supply modules are output to the CPLD. And outputting a driving signal to light the board card power lamp after the PGs of all the power modules are effective.
Based on the structures designed by the application, the working characteristics and functions of the computer control board are as follows:
(a) a display interface: the integrated video card is a VGA interface of the 1-path DB15, the resolution is self-adaptive according to the external display, and the maximum support is 1920x1080 resolution.
(b) A PCIE interface: and 4 paths of PCIE buses are supported, wherein 4 paths are PCIE 3.0 interfaces of X4 and are led out through the PCIE interface connector.
(c) SATA interface: 2 paths of SATA3.0 signals, wherein 1 path of mSATA interface and 1 path of 7-pin SATA interface are adopted.
(d) And (3) storing: an onboard 128G SSD hard disk.
(e) Memory: on-board not less than 16GB DDR4 SDRAM, with ECC checking.
(f) Ethernet: a 2-way 1000base-T network interface providing a 2-way RJ45 gigabit network interface.
(g) A USB port: 6-path USB3.0 interface, which is led out through the front panel USB3.0 interface.
(h) Serial port: the 5-path built-in RS232 serial ports and the 4-path built-in RS232 serial ports are respectively connected to the four PCIE interface connectors, and the 1-path DB9 serial ports are arranged.
(i) JTAG interface: and the level standard 2.5V and 4-lane standard JTAG interfaces are respectively connected to the four PCIE interface connectors.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and scope of the present invention are to be considered as included within the scope of the present invention.
Claims (10)
1. A computer control board implemented based on a SW3231 processor, the computer control board comprising:
8 DDR4 memory interfaces with 64-bit data width of the SW3231 processor correspond to 8 built-in DDR4 memory controllers supporting ECC check respectively, and the 8 DDR4 memory interfaces of the SW3231 processor are connected with the memory granule chip respectively; the SW3231 processor is also connected with a CPLD chip, the SW3231 processor is also connected with a FLASH chip to realize an onboard 128G SSD hard disk, and the SW3231 processor is also connected with a DB9 serial port externally provided by the computer control board;
two sets of PCIEX4 interfaces of the SW3231 processor and two sets of PCIEX8 interfaces split by one set of PCIEX16 interfaces are respectively connected to PICE3.0X4 interfaces of 4 PCIEX interface connectors externally provided by the computer control board;
one group of PCIEX8 interfaces split from the other group of PCIEX16 interfaces of the SW3231 processor are connected to the PCIE bus expansion chip;
the PCIE bus expansion chip is connected with the PCIE-to-USB chip and outputs a USB signal to the computer control board to provide a USB3.0 interface;
the USB-to-multifunctional interface chip is connected with the PCIE-to-USB chip to convert USB signals into serial port signals and JTAG signals, the serial port signals are output to RS232 serial ports of 4 PCIE interface connectors externally provided by the computer control board, and the JTAG signals are output to JTAG interfaces of the 4 PCIE interface connectors externally provided by the computer control board;
the PCIE bus expansion chip is connected with a PCIE-to-MDI chip to output signals to an RJ45 gigabit network interface externally provided by the computer control board;
the PCIE bus expansion chip is connected with a PCIE-SATA chip to output signals to an SATA3.0 interface provided by the computer control board;
the PCIE bus expansion chip is connected with a PCIE-to-VGA chip and is connected with a VGA interface externally provided by the computer control board.
2. The computer control board according to claim 1, wherein each DDR4 memory interface of the SW3231 processor is connected to 4 memory granule chips, the computer control board has 40 memory granule chips of X16 granules, the capacity of a single memory granule chip is 1GB, and the computer control board realizes a 32GB memory on board.
3. The computer control board of claim 2, wherein the memory particle chip is MT40a512M16 HA-062E.
4. The computer control board according to claim 1, wherein the computer control board provides 6 USB3.0 interfaces to the outside, the PCIE-to-USB chip includes two updd 720201 chips providing 8 USB signals, the 6 USB signals are connected to the 6 USB3.0 interfaces respectively, and the remaining 2 USB signals are connected to the USB-to-multifunctional interface chip to form 4 serial signals and 4 JTAG signals.
5. The computer control board of claim 4, wherein the USB-to-multi-function interface chip comprises two FT4232HL chips, and each FT4232HL chip is connected with one path of USB signal conversion to form 2 paths of serial signals and 2 paths of JTAG signals.
6. The computer control board of claim 5, wherein each FT4232HL chip is further connected to two MAX232 chips and two SN74AVCH4T245 chips, respectively, each serial port signal generated by each FT4232HL chip is output to an RS232 serial port of one PCIE interface connector through the MAX232 chip, and each JTAG signal generated by each FT4232HL chip is output to a JTAG interface of one PCIE interface connector through the SN74AVCH4T245 chip.
7. The computer control board of claim 1, wherein the SATA3.0 interface externally provided by the computer control board includes a SATA ata interface and a 7-pin SATA, the PCIE-to-SATA chip is an 88SE9215 chip, and the 88SE9215 chip is further connected to the FLASH chip.
8. The computer control board of claim 1, wherein the PCIE-to-VGA chip is an SM750 chip, a DDR interface of the SM750 chip is further connected to 4 DDR SDRAM chips, and a total capacity of the 4 DDR SDRAM chips is 64 MB.
9. The computer control board of claim 1, wherein the computer control board externally provides two RJ45 gigabit network interfaces, the PCIE-to-MDI chip includes two I210 chips, each I210 chip is connected to one RJ45 gigabit network interface, and each I210 chip is further connected to the FLASH chip.
10. The computer control panel of claim 1, further comprising a reset switch, a power indicator light, a hard disk indicator light, and a buzzer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202023146941.6U CN214175092U (en) | 2020-12-23 | 2020-12-23 | Computer control board realized based on SW3231 processor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202023146941.6U CN214175092U (en) | 2020-12-23 | 2020-12-23 | Computer control board realized based on SW3231 processor |
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| CN214175092U true CN214175092U (en) | 2021-09-10 |
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