CN214123469U - High-resolution compensation circuit - Google Patents
High-resolution compensation circuit Download PDFInfo
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- CN214123469U CN214123469U CN202023252544.7U CN202023252544U CN214123469U CN 214123469 U CN214123469 U CN 214123469U CN 202023252544 U CN202023252544 U CN 202023252544U CN 214123469 U CN214123469 U CN 214123469U
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Abstract
The utility model provides a high resolution compensating circuit, subpixel circuit include the transistor: t2, T3 and T4, capacitances C1 and C2; input terminal of T2 and VDATAThe control end of T2 is connected with Scan2, and the output end of T1 is connected with G; the input end of T3 is connected with OVDD, the control end of T3 is connected with EM, and the output end of T3 is connected with S; the input end of T4 is connected with S, the control end of T4 is connected with G, and the output end of T4 is connected with OVSS; one polar plate of C1 is connected with G, and the other polar plate of C1 is connected with S; one pole plate of C2 is connected with OVDD, and the other pole plate of C2 is connected with S. The above technologySurgical procedure, VDATAWriting RGB data voltage, controlling internal compensation circuit of each row of sub-pixels in display region via T1, and writing DC low voltage Vref(ii) a One T1 control V is shared by each rowrefThe structure ensures that the number of transistors in the sub-pixels is less, the area of the sub-pixels is smaller, the number of the sub-pixels accommodated by the panel is more, and the resolution is high.
Description
Technical Field
The utility model relates to a compensating circuit field especially relates to a high resolution compensating circuit.
Background
The AMOLED panel is self-luminous, is thinner and thinner compared with the traditional LCD, and has a high visual angle; but some undesirable factors affect the luminance, such as VTHDrift can affect the panel luminous current; in addition, the aging of the OLED material can also influence the luminous current and further influence the luminous brightness; meanwhile, the impedance of the metal trend of the self has adverse effect on the luminous current, namely I-R drop; these undesirable factors have a severe influence on the panel light emission luminance.
The smaller the area occupied by the pixels is, the larger the number of pixels accommodated in the panel with the same area size is, the higher the resolution is, and the better the picture quality is.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide a high resolution compensation circuit for eliminating VTHAnd the influence of the adverse factors on the current, and simultaneously, the resolution is improved by reducing the occupied area of the pixel.
To achieve the above object, the present application provides a high resolution compensation circuit, comprising: a display area; the display area includes: a sub-pixel circuit comprising a transistor: t2, T3 and T4, capacitances C1 and C2;
input terminal of the T2 and VDATAThe control end of the T2 is connected with Scan2, and the output end of the T2 is connected with a G node;
the input end of the T3 is connected with OVDD, the control end of the T3 is connected with EM, and the output end of the T3 is connected with an S node;
the input end of the T4 is connected with an S node, the control end of the T4 is connected with a G node, and the output end of the T4 is connected with an OVSS;
one plate of the C1 is connected with a G node, and the other plate of the C1 is connected with an S node;
one plate of the C2 is connected with the OVDD, and the other plate of the C2 is connected with the S node.
Further, a peripheral area circuit is also included; the peripheral area circuit is arranged on one side of the display area and is electrically connected with the sub-pixel circuit; the peripheral region circuit includes a transistor: t1;
input terminal of the T1 and VrefAnd the control terminal of the T1 is connected with a Scan1, and the output terminal of the T1 is connected with a G node.
Further, the transistor is a thin film transistor.
Further, the T1 and the T2 are N-type thin film transistors, and the T3 and the T4 are P-type thin film transistors.
Further, the number of the sub-pixel circuits is plural, a plurality of the sub-pixel circuits are arranged in an array, and the G node of each of the sub-pixel circuits in one row is connected to the output terminal of the T1.
Furthermore, the OVSS end of the sub-pixel circuit is connected with the sub-pixel, and the sub-pixel circuit is used for driving the sub-pixel to emit light.
In order to achieve the above object, the present application further provides a driving method of a high resolution compensation circuit, for driving the high resolution compensation circuit according to any one of the embodiments, including:
in Reset phase, high voltage is written into Scan1, low voltage is written into Scan2, and low voltage is written into EM;
in the compensation phase, high voltage is written into Scan1, low voltage is written into Scan2, and high voltage is written into EM;
in the data writing phase, a low voltage is written in Scan1, a high voltage is written in Scan2, and a high voltage is written in EM;
in the light emission phase, a low voltage is written to Scan1, a low voltage is written to Scan2, and a low voltage is written to EM.
Further, in the Reset phase, the T1, T4 and T3 are in an on state, and T2 is in an off state;
during the compensation phase, the T1 and T4 are in an on state, and the T2 and T3 are in an off state;
in the data write phase, the T4 is in an ON state, the T1, T2 and T3 are in an OFF state;
in the light-emitting phase, the T3 and the T4 are in an on state, and the T1 and the T2 are in an off state.
Is different from the prior art, the technical scheme VDATAWriting RGB data voltage, controlling internal compensation circuit of each row of sub-pixels in display region via T1, and writing DC low voltage Vref(ii) a One transistor (i.e., T1) control V is shared by each rowrefThe structure ensures that the number of transistors in the sub-pixels is less, the area of the sub-pixels is smaller, the number of the sub-pixels accommodated by the panel is more, and the resolution is high.
Drawings
FIG. 1 is a diagram of the high resolution compensation circuit;
FIG. 2 is a diagram of the sub-pixel and the sub-pixel circuit structure;
FIG. 3 is a schematic diagram of the Reset phases T1, T2, T3 and T4 turning on or off;
FIG. 4 is a timing diagram of the Reset phase;
FIG. 5 is a schematic diagram of the compensation phases T1, T2, T3 and T4 turning on or off;
FIG. 6 is a timing diagram of the compensation phase segment;
FIG. 7 is a schematic diagram of the data writing phases T1, T2, T3 and T4 being turned on or off;
FIG. 8 is a timing diagram of a data write phase segment;
FIG. 9 is a schematic diagram of the ON or OFF states of the light-emitting periods T1, T2, T3 and T4;
FIG. 10 is a timing diagram of the light-emitting phase segment.
Description of reference numerals:
1. a display area; 2. a peripheral area circuit;
11. a sub-pixel circuit; .
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 10, a high resolution compensation circuit is provided, and fig. 1 and 2 include: the display area 1 includes: a sub-pixel circuit 11, aThe sub-pixel circuit 11 includes a transistor: t2, T3 and T4, capacitances C1 and C2; input terminal of the T2 and VDATAThe control end of the T2 is connected with Scan2, and the output end of the T2 is connected with a G node; the input end of the T3 is connected with OVDD, the control end of the T3 is connected with EM, and the output end of the T3 is connected with an S node; the input end of the T4 is connected with an S node, the control end of the T4 is connected with a G node, and the output end of the T4 is connected with an OVSS; one plate of the C1 is connected with a G node, and the other plate of the C1 is connected with an S node; one plate of the C2 is connected with the OVDD, and the other plate of the C2 is connected with the S node.
It should be noted that OVSS is connected to the sub-pixel, and the sub-pixel circuit 11 is used for driving the sub-pixel to emit light; three sub-pixels form an RGB pixel; vDATAWriting data voltages of RGB; OVDD is the internal working voltage of the device, and OVSS is the voltage of the common grounding end of the circuit, namely the output voltage; the S node is connected with one polar plate of C1 and C2, and is simultaneously connected with the output end of T3 and the input end of T4; the G node is connected with the output end of the T2 and the control end of the T4, and is simultaneously connected with the other plate of the C1. Scan1 and Scan2 are both Scan lines.
Above technical solution, VDATAWriting RGB data voltage, controlling internal compensation circuit of each row of sub-pixels in display region 1 via T1, and writing DC low voltage Vref(ii) a One transistor (i.e., T1) control V is shared for each rowrefThe structure ensures that the number of transistors in the sub-pixels is less, the area of the sub-pixels is smaller, the number of the sub-pixels accommodated by the panel is more, and the resolution is high.
Referring to fig. 1, in some embodiments, a peripheral circuit 2 is further included; the peripheral area circuit 2 is arranged at one side of the display area 1, and the peripheral area circuit 2 is electrically connected with the sub-pixel circuit 11; the peripheral region circuit includes a transistor: t1; input terminal of the T1 and VrefAnd the control terminal of the T1 is connected with a Scan1, and the output terminal of the T1 is connected with a G node. In addition, V isrefThe direct current low voltage is written; while the output terminal of T1 in the peripheral area circuit is connected to the G node in the sub-pixel circuit 11,for controlling a row of said sub-pixel circuits 11; of course, in the present embodiment, the peripheral area circuit 2 is located on the right side of the display area 1.
In some embodiments, the transistor is a thin film transistor. The transistors are various, and T1, T2, T3 and T4 may be thin film transistors, MOS transistors (i.e., metal-oxide-semiconductor field effect transistors MOSFET), junction field effect transistors, or the like. Preferably, T1, T2, T3 and T4 are all Thin Film Transistors (TFT), and the Thin Film transistors are used as switches to drive the liquid crystal pixels to achieve the characteristics of high speed, high brightness and high contrast.
Further, the thin film transistor may be P-type or N-type, that is, in the N-type transistor, the input terminal is a drain, and the output terminal is a source; the input end of the P-type transistor is a source electrode, and the output end of the P-type transistor is a drain electrode; in the application, the T1 and the T2 are N-type thin film transistors, and the T3 and the T4 are P-type thin film transistors.
In a preferred embodiment, the compensation circuit is disposed on a LCD Display panel, the LCD is a short for Liquid Crystal Display, and chinese is a Liquid Crystal Display. The LCD display panel has advantages of small size, low power consumption, and high brightness.
Or in some embodiments, the compensation circuit may be disposed on an OLED display panel, where the OLED is an Organic Light-Emitting Diode, and the chinese language is an Organic electroluminescent display or an Organic Light-Emitting semiconductor. The OLED display panel has the characteristics of lightness, thinness, high brightness, low power consumption, quick response, high definition, good flexibility, high luminous efficiency and the like, and can meet the new requirements of consumers on display technology.
Referring to fig. 1 and 2, in some embodiments, the number of the sub-pixel circuits 11 is multiple, a plurality of the sub-pixel circuits 11 are arranged in an array, and the G node of each of the sub-pixel circuits 11 in a row is connected to the output terminal of the T1. Note that the T1 is used to control a row of sub-pixels, that is, the G nodes in all the sub-pixel circuits 11 in a certain row are connected to the output terminal of the T1. The structure ensures that the number of transistors in the sub-pixel is less, the area of the sub-pixel is smaller, the number of the sub-pixels accommodated by the panel is more, and the resolution is high.
Referring to fig. 8 to 10, on the basis of the compensation circuit, the specific principle is described in conjunction with the driving method of the compensation circuit:
in Reset phase, high voltage is written into Scan1, low voltage is written into Scan2, and low voltage is written into EM; at this time, the T1, the T4 and the T3 are in an on state, and the T2 is in an off state; in the compensation phase (Comp.), high voltage is written into Scan1, low voltage is written into Scan2, and high voltage is written into EM; at this time, the T1 and the T4 are in an on state, and the T2 and the T3 are in an off state; in the Data writing phase (Data in), a low voltage is written in Scan1, a high voltage is written in Scan2, and a high voltage is written in EM; at this time, the T4 is in an on state, and the T1, T2 and T3 are in an off state; in the Light emitting stage (Light in), low voltage is written into Scan1, low voltage is written into Scan2, and low voltage is written into EM; at this time, the T3 and T4 are in an on state, and the T1 and T2 are in an off state.
It should be further noted that, in the Reset phase, Scan1 writes a high voltage, T1 turns on, and the point G writes a Vref voltage; writing low voltage into EM, turning on T3, and writing OVDD VG (Vref) into an S point; VS is OVDD;
compensation phase, EM writes high voltage, T3 is closed, T4 works in saturation region, S point voltage is reduced from OVDD to V point voltageref+VTHAt time T4 is closed, at which time VS＝Vref+VTHI.e. to a VTH(ii) a VG remains unchanged, i.e., VG ═ Vref; data write phase, Scan1 write low voltage, Scan2 write high voltage, T1 close, T2 open, VG＝VDATAG point voltage is VrefChange to VDATADue to the effect of the capacitor, VS＝Vref+Vth+C1/ (C1+C2)(VDATA-Vref) (ii) a In the light emitting stage, low voltage is written in EM, T3 is turned on, the LED is turned on, VSDue to the effect of capacitance, VG＝OVDD-[Vref+Vth+C1/(C1+C2)(VDATA-Vref)](ii) a Then VSG＝VS-VG＝Vth+C1/(C1+C2)(VDATA-Vref) Substituting into P-type TFTCurrent formula IOLED in saturation region is 1/2 μ nCOXW/L (V)SG-VTH)2 obtaining IOLED (1/2 μ nCOXW/L [ C1/(C1+ C2) (V)DATA-Vref)]2(μ n is the field effect mobility, COX is the insulation layer capacitance per unit area and W/L is the TFT channel width to length). From the OLED luminous current formula, it can be understood that the OLED current is only equal to VDATA， VrefThe structure has the advantages of small number of TFTs, small area occupied by the sub-pixels, large number of sub-pixels accommodated by the panel and high resolution.
It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.
Claims (6)
1. A high resolution compensation circuit, comprising: a display area; the display area includes: a sub-pixel circuit comprising a transistor: t2, T3 and T4, capacitances C1 and C2;
input terminal of the T2 and VDATAThe control end of the T2 is connected with Scan2, and the output end of the T2 is connected with a G node;
the input end of the T3 is connected with OVDD, the control end of the T3 is connected with EM, and the output end of the T3 is connected with an S node;
the input end of the T4 is connected with an S node, the control end of the T4 is connected with a G node, and the output end of the T4 is connected with an OVSS;
one plate of the C1 is connected with a G node, and the other plate of the C1 is connected with an S node;
one plate of the C2 is connected with the OVDD, and the other plate of the C2 is connected with the S node.
2. The high resolution compensation circuit of claim 1, further comprising a peripheral area circuit; the peripheral area circuit is arranged on one side of the display area and is electrically connected with the sub-pixel circuit; the peripheral region circuit includes a transistor: t1;
input terminal of the T1 and VrefAnd the control terminal of the T1 is connected with a Scan1, and the output terminal of the T1 is connected with a G node.
3. The high resolution compensation circuit of claim 2, wherein the transistor is a thin film transistor.
4. The high resolution compensation circuit of claim 2, wherein the T1 and T2 are N-type thin film transistors and the T3 and T4 are P-type thin film transistors.
5. The high resolution compensation circuit of claim 2, wherein the plurality of sub-pixel circuits are arranged in an array, and the G node of each sub-pixel circuit in a row is connected to the output terminal of the T1.
6. The high resolution compensation circuit of claim 1, wherein the OVSS terminal of the sub-pixel circuit is connected to a sub-pixel, and the sub-pixel circuit is used to drive the sub-pixel to emit light.
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| CN202023252544.7U CN214123469U (en) | 2020-12-29 | 2020-12-29 | High-resolution compensation circuit |
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| CN202023252544.7U CN214123469U (en) | 2020-12-29 | 2020-12-29 | High-resolution compensation circuit |
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| CN112562595A (en) * | 2020-12-29 | 2021-03-26 | 福建华佳彩有限公司 | High-resolution compensation circuit and driving method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112562595A (en) * | 2020-12-29 | 2021-03-26 | 福建华佳彩有限公司 | High-resolution compensation circuit and driving method thereof |
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