CN214045430U

CN214045430U - Optimized pre-discharge circuit

Info

Publication number: CN214045430U
Application number: CN202023006002.1U
Authority: CN
Inventors: 吴智声; 俞峰
Original assignee: Fujian Scud Power Technology Co Ltd
Current assignee: Fujian Scud Power Technology Co Ltd
Priority date: 2020-12-15
Filing date: 2020-12-15
Publication date: 2021-08-24
Anticipated expiration: 2030-12-15

Abstract

The utility model discloses an optimized pre-discharge circuit, including diode D1, resistance R65, resistance R67, diode D8, field effect transistor Q1 and field effect transistor Q26, the interface GPIO _ ADC, electric capacity C19 and the resistance R67 of singlechip are connected to diode D1's negative pole, resistance R67's other end connecting resistance R66, resistance R60 and field effect transistor Q26's source electrode, the beneficial effects of the utility model are that: 1: the circuit is convenient to modularize and arrange, only two wires need to be radiated from an IO port of the singlechip, the high voltage of BAT + is avoided, and 12v does not pass through other areas to reach a pre-discharge circuit; 2: the circuit saves a plurality of devices and space under the condition that the MOS tube can be completely conducted; 3: in the saved space, only a plurality of devices are added, a pre-discharge feedback can be obtained, and more information of the system can be judged.

Description

Optimized pre-discharge circuit

Technical Field

The utility model relates to a power supply optimization technology field specifically is a pre-discharge circuit who optimizes.

Background

With the progress and development of society, the intellectualization in the aspects of storage, family, trip and the like, the diversification of mobile consumer electronic products, and the adoption of batteries as clean energy providers, the batteries are more and more popular and favored by consumers and become an indispensable part of electronic products. In the application process, the battery is taken as an output end of energy, whether the performance of the battery core meets the use condition or not is considered through test items such as charging, discharging, high-temperature group storage, low-temperature group storage testing and the like under certain conditions, the safety and the operation coefficient in the application are improved, the battery is helped to reduce the failure rate in the use process in the long-term use process, more secure service is provided for a user in the use process, the user acceptance is improved, and the method becomes a significant research subject.

In the prior art, as shown in fig. 1 and 2, in the pre-discharge driving, most of the complex driving is adopted, as shown in fig. 1, the pre-discharge MOS, Q15, is taken from BAT + to C4, which is linearly reduced to a Q6 switch controlled by a single chip microcomputer, where BAT + is high voltage, as shown by an arrow in fig. 1, when PCB is wired, because the layout relationship can pass through the whole PCB, which causes wiring difficulty and violates the principle of high-low voltage isolation, as shown in fig. 2, slightly improved, a V12 power supply of the system is used for MOS transistor driving, but there is a problem that the circuit is based on a modular layout, the entering signal line will be two signal lines of V12 and coyfang at the I/O port of the single chip microcomputer, as shown in fig. 2, even though BAT + is 20 strings, the maximum current is 84/50 a through R56 and R57 current limiting resistors, and the VGS voltage of the small current is much about 2, as shown in table 1, the MOS transistor specification is intended, and 1.4V driving is sufficient to achieve low impedance turn-on in the MOS specification, so that the power consumption in the prior art is large.

TABLE 1

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a pre-discharge circuit of optimizing to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

an optimized pre-discharge circuit comprises a diode D, a resistor R, a diode D, a field effect tube Q and a field effect tube Q, wherein the cathode of the diode D is connected with an interface GPIO _ ADC, a capacitor C and a resistor R of a single chip microcomputer, the other end of the resistor R is connected with the resistor R, the resistor R and the source electrode of the field effect tube Q, the other end of the resistor R is connected with the cathode of the diode D and the grid electrode of the field effect tube Q, the anode of the diode D is connected with an interface GPIO _ EN of the single chip microcomputer, the anode of the diode D is connected with the resistor R and a grounding end, the other end of the capacitor C is connected with the other end of the resistor R, the resistor RS and the grounding end, the other end of the resistor RS is connected with the other end of the resistor R and the source electrode of the field effect tube Q, the drain electrode of the field effect tube Q is connected with a fuse F, the other end of the fuse F is connected with the resistor R and the drain electrode of the field effect tube Q through the resistor R, the other end of the resistor R63 is connected to the drain of the fet Q1 and the drain of the fet Q2 via a resistor R64.

As a further technical solution of the present invention: the field effect transistor Q1 and the field effect transistor Q2 form a charging and discharging power tube.

As a further technical solution of the present invention: the model of the diode D8 is 1N 4148.

As a further technical solution of the present invention: the model of the field effect transistor Q26 is NCE1540 KA.

As a further technical solution of the present invention: the diode D1 is a zener diode.

As a further technical solution of the present invention: the regulated voltage value of the diode D1 is 2.4V.

As a further technical solution of the present invention: the resistance value of the resistor R67 is 1K omega.

As a further technical solution of the present invention: the resistance of the resistor R54 is 1m omega.

As a further technical solution of the present invention: the resistance value of the resistor R66 is 100K omega.

As a further technical solution of the present invention: the field effect transistor Q1 and the field effect transistor Q2 are both N-type field effect transistors.

Compared with the prior art, the beneficial effects of the utility model are that: 1: the circuit is convenient to modularize and wire-layout, only two wires need to be radiated from an IO port of the singlechip, the high voltage of BAT + does not exist, and 12v does not pass through other regions to reach the pre-discharge circuit. 2: the circuit saves a plurality of devices and space under the condition that the MOS tube can be completely conducted. 3: in the saved space, only a plurality of devices are added, a pre-discharge feedback can be obtained, and more information of the system can be judged.

Drawings

Fig. 1 is a circuit diagram of a first prior art.

Fig. 2 is a circuit diagram of a second prior art.

Fig. 3 is a circuit diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 3, an optimized pre-discharge circuit includes a diode D, a resistor R, a diode D, a field effect transistor Q, and a field effect transistor Q, a cathode of the diode D is connected to an interface GPIO _ ADC, a capacitor C, and a resistor R of a single chip microcomputer, another end of the resistor R is connected to the resistor R, and a source of the field effect transistor Q, another end of the resistor R is connected to a cathode of the diode D and a gate of the field effect transistor Q, an anode of the diode D is connected to an interface GPIO _ EN of the single chip microcomputer, an anode of the diode D is connected to the resistor R and a ground terminal, another end of the capacitor C is connected to another end of the resistor R, the resistor RS, and the ground terminal, another end of the resistor RS is connected to another end of the resistor R and the source of the field effect transistor Q, a drain of the field effect transistor Q is connected to a fuse F, another end of the fuse F is connected to the resistor R and the resistor R, another end of the resistor R is connected to a drain of the field effect transistor Q via the resistor R, the other end of the resistor R63 is connected to the drain of the fet Q1 and the drain of the fet Q2 via a resistor R64.

The field effect transistor Q1 and the field effect transistor Q2 form a charging and discharging power tube. Diode D8 is model 1N 4148. The model of the field effect transistor Q26 is NCE1540 KA. The diode D1 is a zener diode. The regulated voltage value of the diode D1 is 2.4V. The resistance of the resistor R67 is 1K Ω. The resistance of the resistor R54 is 1m Ω. The resistance of the resistor R66 is 100K omega. The field effect transistor Q1 and the field effect transistor Q2 are both N-type field effect transistors.

The diode D8 and the resistor R66 in the circuit form a driving circuit of Q26. The resistor R60, the capacitor C19 and the resistor R67 form an a diode D capacitor C sampling circuit, the GPIO _ EN is connected to the single chip microcomputer, the resistor R66 is connected to the GS electrode of the MOS to form a discharge circuit, the GPIO _ EN directly controls the G electrode of the Q26 after reverse connection of the diode, the GPIO _ A diode D capacitor C is connected with the single chip microcomputer, when pre-discharge is needed, the GPIO _ EN outputs high level 3.3V, 2.9V is further generated through diode voltage drop, at the moment, the Q26 is conducted, assuming that the power is full 84 at the moment, the resistor R60 divides voltage to 0.42V, at the moment, the Q26 and the G electrode are raised by 0.42V, 2.48V is left in VGS, still is far larger than 1.4V in a specification. When the voltage division of the battery is 0.42V obtained when the battery is fully charged 84 or the voltage division of the 54V of the under-voltage protection is 0.27V, the divided voltage is sampled by a capacitor C of a diode D, and the singlechip can know whether the pre-discharge is successful or not according to the voltage value.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. An optimized pre-discharge circuit comprises a diode D, a resistor R, a diode D, a field effect tube Q and a field effect tube Q, and is characterized in that the cathode of the diode D is connected with an interface GPIO _ ADC, a capacitor C and a resistor R of a single chip microcomputer, the other end of the resistor R is connected with the resistor R, the resistor R and the source electrode of the field effect tube Q, the other end of the resistor R is connected with the cathode of the diode D and the grid electrode of the field effect tube Q, the anode of the diode D is connected with an interface GPIO _ EN of the single chip microcomputer, the anode of the diode D is connected with the resistor R and a grounding end, the other end of the capacitor C is connected with the other end of the resistor R, the resistor RS and the grounding end, the other end of the resistor RS is connected with the other end of the resistor R and the source electrode of the field effect tube Q, the drain electrode of the field effect tube Q is connected with a fuse F, the other end of the fuse F is connected with the resistor R and the resistor R, the other end of the drain electrode of the field effect tube Q through the resistor R, the other end of the resistor R63 is connected to the drain of the fet Q1 and the drain of the fet Q2 via a resistor R64.

2. The optimized pre-discharge circuit as claimed in claim 1, wherein the fet Q1 and fet Q2 constitute charge/discharge power transistors.

3. An optimized pre-discharge circuit as claimed in claim 1, wherein said diode D8 is of type 1N 4148.

4. The optimized pre-discharge circuit as claimed in claim 1, wherein said fet Q26 is of type NCE1540 KA.

5. An optimized pre-discharge circuit as claimed in claim 1, wherein said diode D1 is a zener diode.

6. An optimized pre-discharge circuit as claimed in claim 5, wherein the diode D1 has a regulated voltage of 2.4V.

7. An optimized pre-discharge circuit as claimed in claim 2, wherein the resistance of the resistor R67 is 1K Ω.

8. An optimized pre-discharge circuit as claimed in claim 2, wherein the resistance of the resistor R54 is 1m Ω.

9. An optimized pre-discharge circuit as claimed in claim 2, wherein the resistance of the resistor R66 is 100K Ω.

10. The optimized pre-discharge circuit as claimed in claim 2, wherein said fets Q1 and Q2 are N-fets.