CN213844058U - Interface circuit for avoiding power failure caused by abnormal reset of MCU (microprogrammed control Unit) - Google Patents
Interface circuit for avoiding power failure caused by abnormal reset of MCU (microprogrammed control Unit) Download PDFInfo
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- CN213844058U CN213844058U CN202022442342.2U CN202022442342U CN213844058U CN 213844058 U CN213844058 U CN 213844058U CN 202022442342 U CN202022442342 U CN 202022442342U CN 213844058 U CN213844058 U CN 213844058U
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Abstract
The utility model discloses an avoid leading to interface circuit of power supply failure because of MCU unusual reset, including MCU module, LIN SBC module and communication interface circuit, the MCU module with LIN SBC module passes through communication interface circuit telecommunications connection, the EN _ LDO end of MCU module with the EN/NINT end of LIN SBC module passes through enable signal interface circuit telecommunications connection, enable signal interface circuit can form the bias voltage messenger the EN/NINT end of SBC LIN module receives effective signal always. The utility model discloses avoid taking place unexpected the closing and leading to the power to fall down because of the inside LDO submodule piece of LIN SBC module, ensure that the RAM data of MCU module does not lose, guarantee that the procedure brush writes and accomplish smoothly.
Description
Technical Field
The utility model relates to an avoid MCU to reset the hardware circuit of back system power down, concretely relates to interface circuit of MCU module control LIN SBC module dormancy.
Background
Under normal working conditions, the LIN SBC module needs to complete three functions: the LIN module is responsible for receiving LIN messages on the LIN network and forwarding the LIN messages to the MCU module; secondly, the voltage of the battery is reduced to 5V by an LDO module integrated in the battery to supply power to the MCU module; and thirdly, receiving the dog feeding signal of the MCU module at regular time, and resetting the MCU module under the condition that the dog feeding signal cannot be normally received. Meanwhile, the LIN SBC module can be dormant by LIN messages sent by the main node and also can be dormant by a control signal of the MCU module, and the LIN SBC module in the dormant state can close an LDO module in the LIN SBC module to achieve the purpose of low power consumption.
MCU is because of unusual the back that resets, and its IO mouth that controls inside LDO module of LIN SBC module and enable is in "superficial" state at the moment of resetting, and the inside LDO module of LIN SBC module that leads to takes place unexpected shutting down. The occurrence of the abnormality can cause the data loss of the RAM in the MCU module, so that when the ECU controller is used for programming, software cannot normally read the relevant flag bit stored in the RAM, and the jump from the bootloader to the application cannot be smoothly realized.
Therefore, there is a need to solve the technical problem of power failure caused by abnormal reset of the MCU.
SUMMERY OF THE UTILITY MODEL
The problem to prior art exists, the utility model provides an avoid leading to the interface circuit of power failure because of MCU resets unusually, use this interface circuit after, avoid taking place unexpected closing and leading to the power failure because of the inside LDO submodule piece of LIN SBC module, cause the inside RAM data of MCU module to lose unusually, guarantee that the procedure brush writes the smooth completion of process, ensure normally to read the relevant marker bit of storage in RAM, realize the marker bit smoothly and jump.
In order to solve the technical problem, the utility model discloses a technical scheme is:
the utility model provides an avoid leading to power supply failure's interface circuit because of MCU abnormal reset, including MCU module, LIN SBC module and communication interface circuit, the MCU module with LIN SBC module passes through communication interface circuit telecom connection, the EN _ LDO end of MCU module with the EN/NINT end of LIN SBC module is through enabling signal interface circuit telecom connection, enabling signal interface circuit can form the bias voltage messenger the EN/NINT end of LIN SBC module receives effective signal always.
The utility model discloses a solve its technical problem, the further technical scheme who adopts is:
furthermore, the enable signal interface circuit includes a fourth resistor R4, a fifth resistor R5 and a PMOS transistor, one end of the fourth resistor R4 is electrically connected to the S pole of the PMOS transistor and connected to a third power VCC, the other end of the fourth resistor R4 is electrically connected to the EN _ LDO terminal, the G pole of the PMOS transistor, one end of the fifth resistor R5, the other end of the fifth resistor R5 is grounded, and the D pole of the PMOS transistor is electrically connected to the EN/NINT terminal.
Further, the resistance of the fourth resistor R4 and the resistance of the fifth resistor R5 are both 10k ohms.
Furthermore, the MCU module is further provided with a first LIN _ RX end, a first LIN _ TX end, a WDO end, and a RST _ B end;
the LINSBC module is provided with a TRAM sub-module, a WD sub-module and an LDO sub-module, the TRAM sub-module is provided with a second LIN _ TX end and a second LIN _ RX end, the WD sub-module is provided with a WDI end and a WDR end, and the LDO sub-module comprises an EN/NINT end and an LDO _ OUT end;
a first LIN _ RX end, a first LIN _ TX end, a WDO end and a RST _ B end of the MCU module are respectively in telecommunication connection with a second LIN _ TX end, a second LIN _ RX end, a WDI end and a WDR end of the LIN SBC module through the communication interface circuit;
the LIN SBC module is electrically connected with a first power supply VBAT;
the TRAM submodule is used for establishing communication with the MCU module;
the WD submodule is used for acquiring a timing dog feeding signal sent by the MCU module; when the effective timing dog feeding signal sent by the MCU is not received within the specified time, the WD submodule controls the RST _ B terminal of the MCU module to reset the MCU module through the WDR port of the WD submodule;
the LDO submodule is turned on when the EN/NINT end of the LDO submodule is in an effective signal state, and a power supply is output to the MCU module.
Further, the LDO submodule is electrically connected with an output power filter circuit, the output power filter circuit includes a capacitor C and a fourth power VCC, one end of the capacitor C is electrically connected with the LDO _ OUT terminal and the fourth power VCC respectively, and the other end of the capacitor C is grounded.
The communication interface circuit further includes a first resistor R1, a second resistor R2, and a third resistor R3, wherein the first LIN _ RX end, the first LIN _ TX end, the WDO end, and the RST _ B end are electrically connected to the second LIN _ TX end, the second LIN _ RX end, the WDI end, and the WDR end, respectively, one end of the first resistor R1 is electrically connected to an electrical connection between the first LIN _ TX end and the second LIN _ RX end, one end of the second resistor R2 is electrically connected to an electrical connection between the RST _ B end and the WDR end, the other end of the first resistor R1 and the other end of the second resistor R2 are electrically connected to a second power source VCC, one end of the third resistor R3 is electrically connected to an electrical connection between the WDO end and the WDI end, and the other end of the third resistor R3 is grounded.
Further, a diode D is connected in series between the LIN SBC module and the first power source VBAT.
Further, the resistance value of the first resistor R1, the resistance value of the second resistor R2, and the resistance value of the third resistor R3 are all 10k ohms.
Further, the capacitance value of the capacitor C is 10 μ F.
The utility model has the advantages that:
the utility model discloses enable signal interface circuit's effect is when the IO mouth of MCU module is in the floating state, third power VCC, fourth resistance R4, fifth resistance R5 can provide a stable bias voltage for the PMOS pipe, guarantee that the PMOS pipe switches on all the time, realize with this that the EN/NINT end of LIN SBC module can receive effective signal all the time, thereby avoid the LDO submodule inside the LIN SBC module to take place unexpected closing, guarantee that the procedure is brushed the process and is accomplished smoothly, avoid the RAM data of MCU module inside to lose unusually, ensure normally to read the relevant marker bit of storage in RAM, realize the marker bit to jump smoothly;
secondly, the utility model discloses can lead to its state to become "when floating" after MCU module resets, can rely on the cross-over to provide the bias voltage at PMOS pipe source S utmost point, the bias resistance between the G utmost point, guarantee that the PMOS pipe is in "on" state always, thereby ensure that the EN/NINT end of LIN SBC module can receive the effective signal always, and only need to export the effective signal with EN _ LDO end on the MCU module, can close the LDO submodule inside LIN SBC module with this purpose that reaches the low-power consumption, convenient operation, easy realization;
three, the utility model discloses LDO submodule piece electricity is connected with output power supply filter circuit, and output power supply filter circuit includes electric capacity C and fourth power VCC, and LDO _ OUT end and fourth power VCC are connected to electric capacity C's one end electricity respectively, and electric capacity C's other end ground connection, electric capacity C's capacitance value are 10 mu F, realize power steady voltage output through electric capacity filtering.
The above description is only an overview of the technical solution of the present invention, and in order to make the technical means of the present invention clearer and can be implemented according to the content of the description, the following detailed description is made with reference to the preferred embodiments of the present invention and accompanying drawings.
Drawings
Fig. 1 is an interface circuit schematic diagram for avoiding power failure due to abnormal reset of MCU.
The parts in the drawings are marked as follows:
the device comprises a communication interface circuit 1, an enabling signal interface circuit 2, an MCU module 3, a LINSBC module 4, a TRAM sub-module 41, a WD sub-module 42, an LDO sub-module 43 and an output power filter circuit 5.
Detailed Description
The following description is provided for illustrative embodiments of the present invention, and the advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure of the present invention. The present invention can also be implemented in other different ways, i.e. different modifications and changes can be made without departing from the scope of the present invention.
Examples
The utility model provides an avoid leading to power supply failure's interface circuit because of MCU unusual reset, as shown in fig. 1, including MCU module 3, LIN SBC module 4 and communication interface circuit 1, MCU module 3 with LIN SBC module 4 passes through communication interface circuit 1 telecom connection, the EN _ LDO end of MCU module with the EN/NINT end of LIN SBC module 4 is through enabling signal interface circuit 2 telecom connection, enabling signal interface circuit 2 can form the bias voltage messenger the EN/NINT end of LIN SBC module receives effective signal always.
The enable signal interface circuit comprises a fourth resistor R4, a fifth resistor R5 and a PMOS (P-channel metal oxide semiconductor) tube, one end of the fourth resistor R4 is electrically connected with the S pole of the PMOS tube and connected with a third power VCC, the other end of the fourth resistor R4 is electrically connected with the EN _ LDO end, the G pole of the PMOS tube and one end of the fifth resistor R5, the other end of the fifth resistor R5 is grounded, and the D pole of the PMOS tube is electrically connected with the EN/NINT end.
The resistance value of the fourth resistor R4 and the resistance value of the fifth resistor R5 are both 10k ohms.
The MCU module is also provided with a first LIN _ RX end, a first LIN _ TX end, a WDO end and a RST _ B end;
the LINSBC module is provided with a TRAM sub-module 41, a WD sub-module 42 and an LDO sub-module 43, the TRAM sub-module is provided with a second LIN _ TX end and a second LIN _ RX end, the WD sub-module is provided with a WDI end and a WDR end, and the LDO sub-module comprises an EN/NINT end and an LDO _ OUT end;
a first LIN _ RX end, a first LIN _ TX end, a WDO end and a RST _ B end of the MCU module are respectively in telecommunication connection with a second LIN _ TX end, a second LIN _ RX end, a WDI end and a WDR end of the LIN SBC module through the communication interface circuit;
the LIN SBC module is electrically connected with a first power supply VBAT;
the TRAM submodule is used for establishing communication with the MCU module;
the WD submodule is used for acquiring a timing dog feeding signal sent by the MCU module; when the effective timing dog feeding signal sent by the MCU is not received within the specified time, the WD submodule controls the RST _ B terminal of the MCU module to reset the MCU module through the WDR port of the WD submodule;
the LDO submodule is turned on when the EN/NINT end of the LDO submodule is in an effective signal state, and a power supply is output to the MCU module.
The LDO submodule electricity is connected with output power supply filter circuit 5, output power supply filter circuit 5 includes electric capacity C and fourth power VCC, electric connection is respectively connected to electric capacity C's one end LDO _ OUT end with fourth power VCC, electric capacity C's other end ground connection.
The communication interface circuit 1 includes a first resistor R1, a second resistor R2, and a third resistor R3, wherein the first LIN _ RX end, the first LIN _ TX end, the WDO end, and the RST _ B end are electrically connected to the second LIN _ TX end, the second LIN _ RX end, the WDI end, and the WDR end, respectively, one end of the first resistor R1 is electrically connected to an electrical connection between the first LIN _ TX end and the second LIN _ RX end, one end of the second resistor R2 is electrically connected to an electrical connection between the RST _ B end and the WDR end, the other end of the first resistor R1 and the other end of the second resistor R2 are electrically connected to a second power source VCC, one end of the third resistor R3 is electrically connected to an electrical connection between the WDO end and the WDI end, and the other end of the third resistor R3 is grounded.
And a diode D is connected in series between the LIN SBC module and the first power supply VBAT.
The resistance value of the first resistor R1, the resistance value of the second resistor R2 and the resistance value of the third resistor R3 are all 10k ohms.
The capacitance value of the capacitor C is 10 muF.
The utility model discloses working process and principle:
the interface circuit is electrically connected between the LIN SBC module and the master control MCU module, and the MCU module controls an LDO sub-module enabling signal in the LIN SBC module;
on the premise of not needing any adjustment of software, the phenomenon that when the MCU module is abnormally reset, the LDO sub-module in the LIN SBC module is unexpectedly closed due to the fact that the IO port of the MCU module is in a floating state instantly after being reset is avoided, and therefore the RAM data in the MCU module is abnormally lost;
the problem is not solved, the utility model discloses in the inside LDO submodule piece enable signal link of MCU module control LIN SBC module, scurry into "enable signal interface circuit", the core of this circuit is electronic switch PMOS pipe, when the MCU module leads to its state to become "superficial" because of reseing, can rely on the bias voltage that the cross-over connection provided at the S utmost point of PMOS pipe, the bias voltage resistance between the G utmost point, guarantee this PMOS pipe is in "conducting" state always, thereby ensure that the enable EN/NINT end of LIN SBC module can receive effective signal always; in addition, if the MCU module does need to turn off the LDO sub-module inside the LIN SBC module to achieve the purpose of low power consumption, the electronic switch can be turned off only by outputting a "high" signal from the EN _ LDO terminal of the MCU module, and the logic signal state is as shown in table 1 below.
TABLE 1
The above is only the embodiment of the present invention, not so above only is the embodiment of the present invention, not so limiting the patent scope of the present invention, all of which utilize the equivalent structure made by the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, all of which are included in the patent protection scope of the present invention.
Claims (9)
1. The utility model provides an avoid leading to power failure's interface circuit because of MCU unusual reset, includes MCU module (3), LIN SBC module (4) and communication interface circuit (1), MCU module (3) with LIN SBC module (4) pass through communication interface circuit (1) telecom connection, a serial communication port, the EN _ LDO end of MCU module with EN/NINT end of LIN SBC module (4) is through enabling signal interface circuit (2) telecom connection, enabling signal interface circuit (2) can form the bias voltage messenger the EN/NINT end of LIN SBC module receives effective signal always.
2. The interface circuit for avoiding power failure due to abnormal reset of the MCU according to claim 1, wherein: the enable signal interface circuit comprises a fourth resistor R4, a fifth resistor R5 and a PMOS (P-channel metal oxide semiconductor) tube, one end of the fourth resistor R4 is electrically connected with the S pole of the PMOS tube and connected with a third power VCC, the other end of the fourth resistor R4 is electrically connected with the EN _ LDO end, the G pole of the PMOS tube and one end of the fifth resistor R5, the other end of the fifth resistor R5 is grounded, and the D pole of the PMOS tube is electrically connected with the EN/NINT end.
3. The interface circuit for avoiding power failure due to abnormal reset of the MCU according to claim 2, wherein: the resistance value of the fourth resistor R4 and the resistance value of the fifth resistor R5 are both 10k ohms.
4. The interface circuit for avoiding power failure due to abnormal reset of the MCU according to claim 1, wherein: the MCU module is also provided with a first LIN _ RX end, a first LIN _ TX end, a WDO end and a RST _ B end;
the LIN SBC module is provided with a TRAM sub-module (41), a WD sub-module (42) and an LDO sub-module (43), the TRAM sub-module is provided with a second LIN _ TX end and a second LIN _ RX end, the WD sub-module is provided with a WDI end and a WDR end, and the LDO sub-module comprises an EN/NINT end and an LDO _ OUT end;
a first LIN _ RX end, a first LIN _ TX end, a WDO end and a RST _ B end of the MCU module are respectively in telecommunication connection with a second LIN _ TX end, a second LIN _ RX end, a WDI end and a WDR end of the LIN SBC module through the communication interface circuit;
the LIN SBC module is electrically connected with a first power supply VBAT;
the TRAM submodule is used for establishing communication with the MCU module;
the WD submodule is used for acquiring a timing dog feeding signal sent by the MCU module; when the effective timing dog feeding signal sent by the MCU is not received within the specified time, the WD submodule controls the RST _ B terminal of the MCU module to reset the MCU module through the WDR port of the WD submodule;
the LDO submodule is turned on when the EN/NINT end of the LDO submodule is in an effective signal state, and a power supply is output to the MCU module.
5. The interface circuit according to claim 4, wherein the power down of the power supply due to abnormal reset of the MCU is avoided by: the LDO submodule electricity is connected with output power supply filter circuit (5), output power supply filter circuit (5) include electric capacity C and fourth power VCC, electric capacity C's one end electricity is connected respectively LDO _ OUT end with fourth power VCC, electric capacity C's other end ground connection.
6. The interface circuit according to claim 5, wherein the power down of the power supply due to abnormal reset of the MCU is avoided, further comprising: the communication interface circuit (1) comprises a first resistor R1, a second resistor R2 and a third resistor R3, wherein the first LIN _ RX terminal, the first LIN _ TX terminal, the WDO terminal and the RST _ B terminal are respectively and electrically connected with the second LIN _ TX terminal, the second LIN _ RX terminal, the WDI terminal and the WDR terminal, one end of the first resistor R1 is electrically connected with the electrical connection position of the first LIN _ TX terminal and the second LIN _ RX terminal, one end of the second resistor R2 is electrically connected with the electrical connection position of the RST _ B terminal and the WDR terminal, the other end of the first resistor R1 and the other end of the second resistor R2 are both electrically connected and are both electrically connected with a second power supply VCC, one end of the third resistor R3 is electrically connected with the electrical connection position of the WDO terminal and the WDI terminal, and the other end of the third resistor R3 is grounded.
7. The interface circuit for avoiding power failure due to abnormal reset of the MCU according to claim 6, wherein: and a diode D is connected in series between the LIN SBC module and the first power supply VBAT.
8. The interface circuit according to claim 7, wherein the power down of the power supply due to abnormal reset of the MCU is avoided, further comprising: the resistance value of the first resistor R1, the resistance value of the second resistor R2 and the resistance value of the third resistor R3 are all 10k ohms.
9. The interface circuit according to claim 5, wherein the power down of the power supply due to abnormal reset of the MCU is avoided, further comprising: the capacitance value of the capacitor C is 10 muF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022442342.2U CN213844058U (en) | 2020-10-28 | 2020-10-28 | Interface circuit for avoiding power failure caused by abnormal reset of MCU (microprogrammed control Unit) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022442342.2U CN213844058U (en) | 2020-10-28 | 2020-10-28 | Interface circuit for avoiding power failure caused by abnormal reset of MCU (microprogrammed control Unit) |
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| Publication Number | Publication Date |
|---|---|
| CN213844058U true CN213844058U (en) | 2021-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022442342.2U Active CN213844058U (en) | 2020-10-28 | 2020-10-28 | Interface circuit for avoiding power failure caused by abnormal reset of MCU (microprogrammed control Unit) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213844058U (en) |
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- 2020-10-28 CN CN202022442342.2U patent/CN213844058U/en active Active
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