CN213752689U

CN213752689U - Chip packaging structure, metal frame and electronic equipment

Info

Publication number: CN213752689U
Application number: CN202022581305.XU
Authority: CN
Inventors: 姜域; 殷昌荣
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2020-11-10
Filing date: 2020-11-10
Publication date: 2021-07-20
Anticipated expiration: 2030-11-10

Abstract

The utility model discloses a chip packaging structure, metal crate and electronic equipment, chip packaging structure includes: the front surface of the metal frame is provided with a chip bonding area and a non-chip bonding area, and the back surface of the metal frame is provided with a plurality of bonding pads for connecting an external circuit; the back surface of the chip is provided with a plurality of pins, and the pins are fixedly connected with the chip bonding area; the plastic packaging layer surrounds the chip and the metal frame and exposes the bonding pad; wherein the non-chip bonding region has at least one first three-dimensional microstructure and/or the front side of the chip has at least one second three-dimensional microstructure. By the technical scheme, the metal frame and the chip are optimized, so that layering between the plastic packaging layer and the metal frame and between the plastic packaging layer and the chip are solved, and the quality and the reliability of chip packaging are improved.

Description

Chip packaging structure, metal frame and electronic equipment

Technical Field

The utility model relates to a chip package technical field, more specifically say, relate to a chip package structure, metal crate and electronic equipment.

Background

With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.

The core component of the electronic device for realizing various functions is a control chip. The chip needs to be packaged and protected to form a chip packaging structure, so that the chip is prevented from being damaged by external force. In the prior art, the interfaces of the plastic package layer and other components in the chip package structure are easily layered, so that the reliability of the chip package structure is low.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a chip package structure, metal frame and electronic equipment through the structure of optimizing metal frame and chip to solve the layering between plastic envelope layer and metal frame and/or chip, promote the quality and the reliability of chip package.

In order to achieve the above object, the present invention provides the following technical solutions:

a chip package structure, the chip package structure comprising:

the front surface of the metal frame is provided with a chip bonding area and a non-chip bonding area, and the back surface of the metal frame is provided with a plurality of bonding pads for connecting an external circuit;

the back surface of the chip is provided with a plurality of pins, and the pins are fixedly connected with the chip bonding area;

the plastic packaging layer surrounds the chip and the metal frame and exposes the bonding pad;

wherein the non-chip bonding region has at least one first three-dimensional microstructure at least for increasing the bonding area of the metal frame and the plastic encapsulation layer, and/or the front surface of the chip has at least one second three-dimensional microstructure at least for increasing the bonding area of the chip and the plastic encapsulation layer.

Preferably, in the above chip packaging structure, the first three-dimensional microstructure includes a first groove located in a front surface of the metal frame.

Preferably, in the above chip packaging structure, a line width of the first groove in the first direction is 10 μm to 300 μm;

the depth of the first groove is not more than 100 mu m;

wherein the first direction is parallel to a front surface of the metal frame.

Preferably, in the above chip packaging structure, the depth of the first groove is not greater than half of the thickness of the metal frame.

Preferably, in the above chip packaging structure, a distance between the first groove and the side surface of the chip is not less than 50 μm.

Preferably, in the chip packaging structure, if a plurality of first grooves are provided, the distance between two adjacent first grooves is not less than 50 μm;

the first groove is not less than 50 μm away from the side surface of the metal frame.

Preferably, in the above chip packaging structure, the first three-dimensional microstructure includes a first bump on the front surface of the metal frame.

Preferably, in the above chip packaging structure, the front surface of the chip has a patterned adhesive layer;

the adhesive layer comprises a plurality of second bulges positioned on the front surface of the chip; the second three-dimensional microstructure includes the second protrusion.

Preferably, in the above chip packaging structure, the front surface of the chip has a second groove, and the second three-dimensional microstructure includes the second groove.

Preferably, in the above chip packaging structure, a vertical projection of the first three-dimensional microstructure on the front surface of the metal frame is a circle, an ellipse or a polygon;

the vertical projection of the second three-dimensional microstructure on the front surface of the chip is circular, oval or polygonal.

The utility model also provides a metal frame, the front of the metal frame is provided with a chip bonding area and a non-chip bonding area, and the back of the metal frame is provided with a plurality of bonding pads for connecting an external circuit;

the non-chip bonding region is provided with at least one first three-dimensional microstructure, and the first three-dimensional microstructure is at least used for increasing the combination area of the metal frame and the plastic packaging layer.

The utility model also provides an electronic equipment, electronic equipment includes above-mentioned arbitrary chip packaging structure.

According to the above description, the utility model provides an among the chip package structure, metal crate and the electronic equipment that technical scheme provided, through optimizing metal crate's structure, design into the first three-dimensional microstructure who has a plurality of archs or a plurality of recesses with metal crate's non-chip bonding district, through increasing the combination area of plastic envelope layer and metal crate, form the gomphosis face, the anti shear stress of the faying face that makes plastic envelope layer and metal crate strengthens, reduce the layering probability of taking place, thereby solve the layering between plastic envelope layer and metal crate, promote the quality and the reliability of chip package.

Furthermore, the structure of the chip is optimized, the front surface of the chip is designed into a second three-dimensional microstructure with a plurality of bulges or a plurality of grooves, and a tabling surface is formed by increasing the combination area of the plastic packaging layer and the chip, so that the shearing stress resistance of the combination surface of the plastic packaging layer and the chip is enhanced, the occurrence probability of layering is reduced, the layering between the plastic packaging layer and the chip is solved, and the quality and the reliability of chip packaging are improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structure, ratio, size and the like shown in the drawings of the present specification are only used for matching with the content disclosed in the specification, so as to be known and read by people familiar with the technology, and are not used for limiting the limit conditions which can be implemented by the present invention, so that the present invention does not have the substantial significance in the technology, and any structure modification, ratio relationship change or size adjustment should still fall within the scope which can be covered by the technical content disclosed by the present invention without affecting the efficacy which can be produced by the present invention and the achievable purpose.

FIG. 1 is a cross-sectional view of a conventional chip package structure;

fig. 2 is a cross-sectional view of a chip package structure according to an embodiment of the present invention;

fig. 3 is a cross-sectional view of another chip package structure according to an embodiment of the present invention;

fig. 4 is a cross-sectional view of another chip package structure according to an embodiment of the present invention;

fig. 5 is a cross-sectional view of another chip package structure according to an embodiment of the present invention;

fig. 6 is a top view of a chip package structure according to an embodiment of the present invention;

fig. 7 is a cross-sectional view of a substrate carrier according to an embodiment of the present invention;

fig. 8 is a cross-sectional view of a chip according to an embodiment of the present invention;

fig. 9 is a top view of an electronic device according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention will be described in detail and fully with reference to the accompanying drawings, wherein the description is only for the purpose of illustrating the embodiments of the present invention and is not intended to limit the scope of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As described in the background, a chip (IC) needs to be packaged and protected to form a chip package structure, so as to prevent the chip from being damaged by external force. IC packages are generally protected by a molding compound to form a chip package structure. In order to facilitate the connection between the chip package structure and the external circuit, the chip needs to be bonded on the IC carrier, and a common IC carrier includes a PCB or a metal frame for carrying the IC and conducting signals between the chip and the external circuit.

With the continuous development of scientific progress, the plastic package semiconductor device gradually replaces the original metal and ceramic package device. But the reliability level of the plastic package semiconductor device is lower in the early and middle development stages, and along with the development of new process technologies such as the use of high-purity and low-stress plastic package materials, high-quality chip passivation, chip bonding, internal coating materials, lead bonding, accelerated screening process, automatic molding and the like, the reliability of the plastic package semiconductor device gradually catches up with the metal package and ceramic package devices.

The inventor finds that in the plastic packaged semiconductor device, the interface between the plastic package layer and the carrier plate such as the chip, the plastic package layer and the metal frame is easy to be layered, because the interface between the plastic package layer and other materials belongs to an adhesive structure, and the two materials of the interface are combined together by the acting force between molecules, rather than the processes that the two materials are mutually dissolved, mutually diffused and form a compound.

The interface between the plastic packaging layer of the plastic semiconductor device and other materials has a delamination phenomenon, which can cause the performance reduction of the device and even the circuit failure. Such as: the delamination is generated at the interface of the plastic packaging layer and the chip, so that the bonding lead of the chip can cause the increase of the connection resistance or the open circuit due to mechanical damage such as the tilting of the bonding lead (including an inner bonding point and an outer bonding point), the cracking of a bonding joint, the disconnection of the bonding lead and the like; the delamination of the plastic package layer from the metal frame and other interfaces provides a channel for the intrusion of moisture and contaminants, which causes failure problems such as popcorn effect and the like, thereby affecting the package quality and reliability.

Wherein, the plastic package body absorbs moisture through diffusion, and finally the package body and the surrounding environment reach an equilibrium state under certain temperature and humidity conditions. At this time, the plastic package body is put into a reflow oven for heating reflow soldering, moisture in the plastic package body is changed into gas at high temperature to form saturated water vapor, the vapor pressure is generated in the package body along with the increase of the vapor amount, when the pressure reaches a certain degree, cracks are generated at the weak part of stress concentration for releasing the pressure, the plastic package body starts to generate cracks from the inside, and the phenomena of delamination and cracking are caused, which is commonly called popcorn effect.

Referring to fig. 1, fig. 1 is a cross-sectional view of a conventional chip package structure. As shown in fig. 1, the chip package structure includes: a metal frame 11 having a chip bonding region and a non-chip bonding region on a front surface (i.e., an upper surface) of the metal frame 11, the metal frame 11 having a plurality of pads 12 on a rear surface thereof for connecting an external circuit; the back surface of the chip 13 is provided with a plurality of leads 14, and the leads 14 are fixedly connected with the chip bonding area; and the plastic package layer 15 surrounds the chip 13 and the metal frame 11, and the bonding pad 12 is exposed.

In the manner shown in fig. 1, the non-chip bonding region on the front surface of the metal frame 11 is a plane, and the front surface of the chip 13 is also a plane, which easily causes a delamination phenomenon at the bonding surfaces between the plastic package layer 15 and the chip 13, and between the plastic package layer 15 and the metal frame 11, for example, the bonding surface between the chip 13 and the plastic package layer 15 at the position of the area a1, and the bonding surface between the plastic package layer 15 and the metal frame 11 at the position of the area a2, and in addition, because the area of the bonding surface between the metal frame 11 and the plastic package layer 15 is small, the area of the bonding surface between the plastic package layer 15 and the chip 13 is small, the bonding force is weak, it is difficult to resist internal and external stresses, and the bonding surface is a plane, external moisture can quickly permeate along the plane, thereby inducing a large-area failure problem and a popcorn effect, thereby affecting the chip package quality and reducing reliability.

Therefore, in order to solve the above problems, the present invention provides a chip package structure, a metal frame, a chip and an electronic device, the chip package structure including:

According to the above description, the utility model provides an among the chip package structure, metal crate, chip and the electronic equipment that technical scheme provided, through optimizing metal crate's structure, design into the first three-dimensional microstructure that has a plurality of archs or a plurality of recesses with metal crate's non-chip bonding district, through the combination area that increases plastic envelope layer and metal crate, form the gomphosis face, the anti-shear stress who makes plastic envelope layer and metal crate's faying face strengthens, reduce the layering probability of taking place, thereby solve the layering between plastic envelope layer and metal crate, promote the quality and the reliability of chip package.

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 2, fig. 2 is a cross-sectional view of a chip package structure according to an embodiment of the present invention.

As shown in fig. 2, the chip package structure includes:

a metal frame 21, wherein the front surface of the metal frame 21 is provided with a chip bonding area and a non-chip bonding area, and the back surface of the metal frame 21 is provided with a plurality of bonding pads 22 for connecting an external circuit;

the chip 23, the back of the chip 23 has a plurality of leads 24, the leads 24 are fixedly connected with the chip bonding region;

a molding compound layer 25, wherein the molding compound layer 25 surrounds the chip 23 and the metal frame 21 and exposes the bonding pad 22;

wherein the non-chip bonding region has at least one first three-dimensional microstructure 26, and the first three-dimensional microstructure 26 is at least used for increasing the bonding area of the metal frame 21 and the molding layer 25, and/or the front surface of the chip 23 has at least one second three-dimensional microstructure (not shown), and the second three-dimensional microstructure is at least used for increasing the bonding area of the chip 23 and the molding layer 25.

The embodiment of the application comprises the following three modes: the first three-dimensional microstructures 26 are individually disposed, or the second three-dimensional microstructures are individually disposed, or both the first three-dimensional microstructures 26 and the second three-dimensional microstructures are disposed, and the illustration of only the first three-dimensional microstructures 26 is given in fig. 2 as an example.

In the embodiment of the present invention, the first three-dimensional microstructure 26 includes a first groove located in the front surface of the metal frame 21, and the first three-dimensional microstructure 26 can be directly formed by laser grooving on the surface of the metal frame 21.

A line width of the first groove in the first direction is in a range of 10 μm to 300 μm; the depth of the first groove is not more than 100 mu m; wherein the first direction is parallel to the front surface of the metal frame 21. The depth of the first groove is not more than half of the thickness of the metal frame 21. The distance between the first groove and the side face of the chip 23 is not less than 50 μm; if a plurality of the first grooves are provided, the distance between two adjacent first grooves is not less than 50 μm; the first groove is spaced from the side of the metal frame 21 by a distance of not less than 50 μm.

As shown in fig. 3, fig. 3 is a cross-sectional view of another chip package structure provided by an embodiment of the present invention, in this manner, the first three-dimensional microstructure 26 includes a first protrusion located on the surface of the metal frame 21, and a patterned adhesive layer can be formed on the surface of the metal frame 21 through a printing process, so that the adhesive layer forms an uneven structure, and the bump (the first protrusion) of the adhesive layer is used as the first three-dimensional microstructure 26. Wherein the adhesive layer has a greater adhesion to the metal frame 21 than the plastic layer 25 has to the metal frame 21. The first protrusions may be formed on the surface of the metal frame 21 by using a glue layer with strong adhesion. A line width of the first protrusions in the first direction is in a range of 10 μm to 300 μm; the height of the first protrusion is not more than 100 μm. The height of the first protrusion is not more than half of the thickness of the metal frame 21. The distance between the first bump and the chip 23 is not less than 50 μm; if a plurality of the first projections are provided, the distance between two adjacent first projections is not less than 50 μm; the first protrusion is spaced from the side of the metal frame 21 by a distance of not less than 50 μm.

In the mode shown in fig. 2 and 3, by optimizing the structure of the metal frame 21, the non-chip bonding area of the metal frame 21 is designed into the first three-dimensional microstructure 26 having a plurality of first protrusions or a plurality of first grooves, and by increasing the bonding area of the plastic package layer 25 and the metal frame 21, a mating surface is formed, so that the shear stress resistance of the bonding surface of the plastic package layer 25 and the metal frame 21 is enhanced, and the probability of the plastic package layer 25 and the metal frame 21 being layered can be reduced, thereby solving the layering between the plastic package layer 25 and the metal frame 21, improving the quality and reliability of chip packaging, and additionally, the structure forming the mating surface can also increase the water vapor intrusion path, thereby preventing the water vapor intrusion from affecting the performance and the service life of the chip.

In other ways, the structure of the chip 23 may be optimized individually, and the chip 23 may be designed as the second three-dimensional microstructure 31 having a plurality of second protrusions or a plurality of second grooves. However, in order to better improve the quality and reliability of the chip package, the structures of the metal frame 21 and the chip 23 may be optimized simultaneously, and the bonding surfaces of the metal frame 21 and the chip 23 and the molding layer 25 are designed to be three-dimensional microstructures 31 having a plurality of protrusions or a plurality of grooves.

As shown in fig. 4, fig. 4 is a cross-sectional view of another chip package structure provided by an embodiment of the present invention, a patterned adhesive layer is disposed on a front surface of the chip 23, and the adhesive layer includes the second three-dimensional micro structure 31 and is a plurality of second protrusions disposed on the front surface of the chip. Wherein, the adhesiveness of the glue layer and the chip 23 is larger than that of the plastic packaging layer 25 and the chip 23. The second three-dimensional microstructure 31 may be fabricated on the surface of the chip 23 by selecting a glue layer with strong adhesion. Further, the adhesive layer includes a plurality of second protrusions located on the front surface of the chip 23, and a groove is formed between two adjacent second protrusions; the second three-dimensional microstructures 31 include the second protrusions. The glue layer of the desired pattern structure may be formed on the front surface of the chip 23 through a printing process or a coating process.

In the mode shown in fig. 4, the non-chip bonding region of the metal frame 21 is designed to be the first three-dimensional microstructure 26 having a plurality of first grooves, and the front surface of the chip 23 is designed to be the second three-dimensional microstructure 31 having a plurality of second protrusions, and by increasing the bonding area between the plastic package layer 25 and the metal frame 21, and between the plastic package layer 25 and the chip 23, a fitting surface is formed, so that the shear stress resistance of the bonding surface between the plastic package layer 25 and the metal frame 21, and between the plastic package layer 25 and the chip 23 is enhanced, and the probability of delamination between the plastic package layer 25 and the metal frame 21, and between the plastic package layer 25 and the chip 23 is reduced, thereby improving the quality and reliability of chip packaging. This embodiment is illustrated by the first three-dimensional microstructure 26 shown in fig. 2, but in other embodiments, the first three-dimensional microstructure 26 shown in fig. 3 may be used.

As shown in fig. 5, fig. 5 is a cross-sectional view of another chip package structure provided in an embodiment of the present invention, which is different from the manner shown in fig. 4 in that the front surface of the chip 23 has a second groove, and the second three-dimensional microstructure 31 includes the second groove. A second groove is directly formed on the surface of the chip 23 as the second three-dimensional microstructure 31, and the second three-dimensional microstructure 31 may be directly formed by laser grooving on the surface of the chip 23. In this way, the non-chip bonding region of the metal frame 21 is also designed to be the first three-dimensional microstructure 26 with a plurality of first protrusions, the front surface of the chip 23 is designed to be the second three-dimensional microstructure 31 with a plurality of second grooves, and a fitting surface is formed by increasing the joint area of the plastic package layer 25 and the metal frame 21, and the joint area of the plastic package layer 25 and the chip 23, so that the shear stress resistance of the joint surfaces of the plastic package layer 25 and the metal frame 21, and the plastic package layer 25 and the chip 23 is enhanced, the probability of the plastic package layer 25 and the metal frame 21, and the probability of the plastic package layer 25 and the chip 23 being layered is reduced, and thus the layering between the plastic package layer 25 and the metal frame 21, and between the plastic package layer 25 and the chip 23 are solved, and the quality and reliability of chip packaging are improved. This embodiment is illustrated by the first three-dimensional microstructure 26 shown in fig. 3, but in other embodiments, the first three-dimensional microstructure 26 shown in fig. 2 may be used.

In the mode shown in fig. 4 and 5, by optimizing the structures of the metal frame 21 and the chip 23, the bonding surfaces of the metal frame 21, the chip 23 and the plastic package layer 25 are designed to be three-dimensional microstructures having a plurality of protrusions or a plurality of grooves, and by increasing the bonding area of the plastic package layer 25, the metal frame 21 and the chip 23, a fitting surface is formed, so that the shear stress resistance of the bonding surfaces is enhanced, thereby reducing the layering probability of the plastic package layer 25, the metal frame 21 and the chip 23, and improving the quality and reliability of chip package.

Referring to fig. 6, fig. 6 is a top view of a chip package structure according to an embodiment of the present invention. As shown in fig. 6, the vertical projection of the first three-dimensional microstructure 26 on the front surface of the metal frame 21 may be circular, oval or polygonal; the vertical projection of the second three-dimensional microstructure 31 on the front surface of the chip 23 may be circular, elliptical or polygonal. Wherein the shape of the first three-dimensional microstructure 26 and the second three-dimensional microstructure 31 can be set based on requirements.

According to the above description, the utility model provides an among the chip package structure, through optimizing metal frame's structure, design into the first three-dimensional microstructure who has a plurality of archs or a plurality of recesses with metal frame's non-chip bonding district, through increasing the combination area of plastic envelope layer and metal frame, form the gomphosis face, the anti shear stress of the faying face that makes plastic envelope layer and metal frame strengthens, reduce the layering probability of taking place, thereby solve the layering between plastic envelope layer and metal frame, promote chip package's quality and reliability.

Based on the above embodiment, another embodiment of the present invention further provides a metal frame, as shown in fig. 7, fig. 7 is a sectional view of the metal frame provided by the embodiment of the present invention, the front surface of the metal frame 21 has a chip bonding region and a non-chip bonding region, and the back surface of the metal frame 21 has a plurality of pads 22 for connecting an external circuit.

Wherein the non-chip bonding region has at least one first three-dimensional microstructure 26, and the first three-dimensional microstructure 26 is at least used for increasing the bonding area of the metal frame 21 and the plastic encapsulation layer 25. In this embodiment, the metal frame in the chip package structure shown in fig. 2 is taken as an example, and the metal frame 21 may also be as shown in fig. 3. The non-chip bonding area of the metal frame 21 is designed into a first three-dimensional microstructure 26 with a plurality of bulges or a plurality of grooves, and a jogged surface is formed by increasing the combination area of the plastic packaging layer and the metal frame 21, so that the shearing stress resistance of the combination surface of the plastic packaging layer and the metal frame 21 is enhanced, the occurrence probability of layering is reduced, the layering between the plastic packaging layer and the metal frame 21 is solved, and the quality and the reliability of chip packaging are improved.

Based on the above embodiment, the utility model discloses another embodiment still provides a chip, as shown in fig. 8, fig. 8 is the utility model provides a tangent plane picture of chip, the front of chip 23 has the three-dimensional microstructure 31 of second, the three-dimensional microstructure 31 of second is used for increasing the bonding area of chip 23 and plastic envelope layer at least. The back surface of the chip 23 has a plurality of leads 24, and the leads 24 may be connected to a metal frame by a lower solder 33. In this manner, the chip structure in the chip package structure shown in fig. 5 in the above embodiment is taken as an example for explanation, and the chip 23 may also be in the manner shown in fig. 4. In the chip 23 shown in fig. 8, the second three-dimensional microstructure 31 is formed by a second groove disposed on the front surface of the chip 23, and as described in the above embodiment, the second three-dimensional microstructure 31 may also be formed by an adhesive layer on the surface of the chip 23.

In this embodiment, by optimizing the structure of the chip 23, the front surface of the chip 23 is designed to be the second three-dimensional microstructure 31 having a plurality of protrusions or a plurality of grooves, and by increasing the bonding area between the plastic package layer and the chip 23, a fitting surface is formed, so that the shear stress resistance of the bonding surface between the plastic package layer and the chip 23 is enhanced, the occurrence probability of delamination is reduced, the delamination between the plastic package layer and the chip 23 is solved, and the quality and reliability of chip packaging are improved.

Based on the above embodiment, the present invention further provides an electronic device, which includes the chip package structure described in the above embodiment. Fig. 9 shows the electronic device, and fig. 9 is a top view of the electronic device according to an embodiment of the present invention.

The electronic device 100 can be an electronic device with a display function, such as a mobile phone, a tablet computer, a television, and the like, and the electronic device 100 adopts the chip packaging structure provided in the above embodiment, so that the problem of layering between a plastic packaging layer and a metal frame and between chips can be solved, and the quality and reliability of chip packaging can be improved.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. As for the metal frame, the chip and the electronic device disclosed in the embodiments, since they correspond to the chip package structure disclosed in the embodiments, the description is relatively simple, and the relevant points can be referred to the description of the chip package structure part.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip package structure, comprising:

2. The chip package structure according to claim 1, wherein the first three-dimensional microstructure comprises a first groove in a front surface of the metal frame.

3. The chip packaging structure according to claim 2, wherein a line width of the first groove in the first direction is 10 μm to 300 μm;

the depth of the first groove is not more than 100 mu m;

wherein the first direction is parallel to a front surface of the metal frame.

4. The chip package structure according to claim 2, wherein a depth of the first recess is not greater than half a thickness of the metal frame.

5. The chip package structure according to claim 2, wherein the first groove is spaced from the side surface of the chip by a distance of not less than 50 μm.

6. The chip packaging structure according to claim 2, wherein if a plurality of the first grooves are provided, a distance between two adjacent first grooves is not less than 50 μm;

7. The chip package structure according to claim 1, wherein the first three-dimensional microstructure comprises a first bump on the front surface of the metal frame.

8. The chip package structure according to claim 1, wherein the front surface of the chip has a patterned adhesive layer;

9. The chip package structure according to claim 1, wherein the front surface of the chip has a second recess, and the second three-dimensional microstructure comprises the second recess.

10. The chip package structure according to any one of claims 1 to 9, wherein a vertical projection of the first three-dimensional microstructure on the front surface of the metal frame is circular, elliptical or polygonal;

11. The metal frame is characterized in that the front surface of the metal frame is provided with a chip bonding area and a non-chip bonding area, and the back surface of the metal frame is provided with a plurality of bonding pads for connecting an external circuit;

12. An electronic device, characterized in that the electronic device comprises a chip package structure according to any one of claims 1-10.