CN2136479Y - Loss-of-phase accumulation timing counter - Google Patents

Abstract

The utility model relates to a loss-of-phase accumulation timing counter, which is composed of a voltage sampling circuit, a current sampling circuit, a no-voltage decision logic circuitry, an accumulating timing display circuit, a time base generator, an accumulating pulse generator, a timing pulse generator, etc. The utility model causes a timing counter using days and months as a metering unit to be improved into an instrument using hours as the metering unit; thus, the application of the utility model is convenient, and the utility model provides an accurate data of quantity of electricity for electric power departments.

Description

Loss-of-phase accumulation timing counter

But the utility model relates to the instrument of a kind of cummulative metering phase failure time, belongs to field of measuring technique.

In electric power system, when circuit generation phase shortage (one mutually or two-phase), electric energy meter degree can reduce or stop; if artificially become; then can be for stealing provide convenience, in order to monitor this state, power department requires to install phase failure calculagraph; calculagraph commonly used at present; take the life as the long-pending metering of unit list, big like this measurement unit is when the clearing electric weight, and dispute or misunderstanding take place in regular meeting; many notes or few meter all can cause damage to a certain side.

The purpose of this utility model provides a kind of hour being the technical scheme of measurement unit, thereby provides continuous data accurately and conveniently for non-full-phase state.

The purpose of this utility model is by ingenious design and utilize the sprocket pulse signal and the summation pulse signal is realized.

Below in conjunction with accompanying drawing the utility model is done further narration.

Fig. 1 is a theory diagram of the present utility model.

Fig. 2 is the part electrical schematic diagram.

Fig. 3 is a voltage sample circuit.

Fig. 4 is a current sampling circuit.

Fig. 5 is the frequency division oscillogram of frequency divider CD4040.

Fig. 6 is that (wherein " 1 " representative has electricity (pressing or stream) to the calculagraph truth table, and " 0 " representative does not have.

Disconnected phase calculagraph generally all has voltage sample circuit, current sampling circuit, decompression decision logic circuity, accumulator and corresponding display circuit. Calculagraph after the improvement, be provided with a time-base generator 1, summation pulse generator 2 and timing impulse generator 3, described time-base generator produce one 36 seconds be the cycle count signal in cycle, described summation pulse generator 2 is one three and a door YM3, its three input lines meet respectively 06 of frequency divider CD4040,07,011 output pin, described timing impulse generator also is one or three AND circuits, its three input lines connect 06 of frequency divider, 07,011 output pin, 07 be 07 output pin through the anti-phase acquisition of not gate F1, summation pulse signal and sprocket pulse signal all cause the decompression decision logic circuity respectively as control signal cumulative and the timing operation.

The decompression decision logic circuity is by forming with door YM4, YM5, YM6 and not gate F2, F3, F4, F5, F6, each with the door three input lines in, article one, through not gate F2(or F3, F4) connect voltage sample circuit, article one, meet sprocket pulse output line T1, another connects current sampling circuit behind not gate F5, the F6 of two series connection, with the electronic switch of the output termination accumulator of door.

Cumulative timing displaing circuit is by accumulator 9,10,11, display 12,13,14 and electronic switch K1, K2, K3, K4, K5, K6, K7 form, wherein, the data input pin 36,39 of accumulator meets sprocket pulse electronic switch K1 or K2, K3, and its cumulative operating control signal pin 34,42 meets summation pulse electronic switch K5 or K6, K7.

In order when normal phase shortage takes place, to remind operating personnel to note, the utility model also is provided with a sound light alarming circuit, sound light alarming circuit by with door YM7, YM8, electronic switch K4, K8, resistance R 3 and alarm lamp JD and hummer FM form, wherein, three incoming lines of YM7 connect the correspondent voltage sample circuit respectively, in three incoming lines of YM8, article one, meet not gate F6, the 3rd pin that meets frequency divider CD4040, a series side that connects analog switch K4 and resistance R 3, its output line meets electronic switch K8, and the circuit that the latter then controls JD and FM opens and closes.

The embodiment that is provided below in conjunction with accompanying drawing 2-6 is described in further detail respectively the formation and the effect of each circuit of the utility model.

One, time base circuit:

Its purpose is to produce to be the train of impulses in cycle in 0.01 hour=36 seconds.

The frequency of the f=32768Hz that is produced by crystal resonator ZT is made 1024 frequency divisions through ABG103 frequency dividing circuit piece: 32768 ÷ 1024=32Hz, again by triode BG(9013) amplify, one three 1152 frequency divisions that are connected into a YM1 in CD4040 and CD4073 obtain one and were the cycle count signal in cycle in 36 seconds.From CD4040 06,07(07), 011 frequency division output pin can " with going out " YM2, YM3 pulse per second (PPS), these two was that the pulse of (this example is selected 1 second) at interval of certain sequential is arranged in the cycle with 36 seconds, just offered " sprocket pulse " signal T1 of logical circuit and " summation pulse " signal T2 of back.Thereby finished the purpose of chronomere's generation in 0.01 hour.

Two, decompression decision logic circuity:

Whether making above-mentioned " sprocket pulse " and " summation pulse " give count display and make it accumulated counts " this is the task of decompression decision logic circuity.Its logic algebra formula is UIT1=1, as long as satisfy no-voltage, electric current is arranged, this condition of sprocket pulse is arranged, at this moment open with door YM4, YM5, YM6 and be output as 1, start electronic switch (this example is selected CD4066(1)), switch closure once provides data accumulation 0.01 to the display that adds up.

Above condition is as satisfying, as: U=0(U=1) voltage is arranged promptly, then YM4, YM5, YM6 and Men Buhui open, and the numeral of display can not add 0.01.And for example I=0 can not open yet.Just open when having only UI=1, the truth table of Fig. 6 has shown the designing requirement of this logical circuit.

Three, the timing displaing circuit that adds up:

Its task comes a pulse to add " 1 " at lowest order.That is count in former demonstration and to add 0.01 on the N.The N max cap. is eight.Behind the meter full 999999.99, no longer count, necessary manual reset also will be walked 114 years but walk on everyday, so within the life-span of electron device, can meet the demands fully.

The process that the totalizer of present embodiment and display adopt UM3153 integrated package (daily output) to add up is equivalent to the 1+1+1+1 of computing machine ..., promptly these two keys of " 1 " and "+" are alternately pressed.Sprocket pulse T1 provides the data-signal that adds " 1 " (promptly 0.01) by CD4066 electronic switch break-make, this moment, display showed that " 1 " summation pulse T2 provides "+" operation signal by the break-make of electronic switch K5, K6, K7, and display has added " 1 " on former demonstration number.Because of the radix point on the dial plate between ten and hundred, macroscopical reading promptly increases by 0.01.During circuit design, make YM3 constantly export the summation pulse signal, such design arrangement can be saved element, reduces cost.

Four, voltage and current sample circuit:

Because of voltage transformer (VT) three-phase 100V alternating voltage and middle cross streams electric current can't directly be sent into the logic decision circuit.Must become the direct current signal of 0-5V earlier.The electric current and voltage sample circuit i.e. purpose and designing for this reason.

From the angle of error in dipping, the input impedance of voltage sampling is high more good more, and the input impedance of current sampling is the smaller the better, so just can not make the numerical value of original watt metering that bigger influence takes place because of the intervention of this instrument.Present embodiment adds the above unbalanced resistance of string 27K, R by three small transformers ₄, Rc selects 27K, R _BSelect 600 Europe), star connection, the realization three-phase is taken a sample respectively, and through rectification, filtering becomes the 0-5V DC voltage.Be distributed into A, B, C three tunnel logic decision circuit, as sampled signal.

In current sampling circuit, by the alternating current rheology 0-5V DC voltage of a small current mutual inductor with 0.02A-5A, by voltage stabilizing diode as secondary short-circuit component, DC voltage after the conversion is sent into before the decompression logic decision circuit through two not gate F5, F6 shaping, as I participate in phase " with " signal.

Five, little electric current floating charge circuit:

Complete machine power consumption less than 200 μ A, but do not replenish as having, and the power supply of this circuit can not long-term work.Therefore, in sampling, the utility model also adds a floating charge circuit.Floating charging routing resistance R8 and diode D series connection constitutes, and the other end of R8 is connected on the DC side of voltage or current return, the positive pole of another termination power of D, by it to battery charge.Theoretical Calculation and experiment show that the design neither overcharges, and also do not owe to fill, and just make it balance.Can make the permanent work of instrument like this.

Six, sound light alarming circuit:

Warning circuit requires: any phase, and two-phase or three-phase open circuit entirely, decompression, then red light is bright, and with the sound, its Boolean algebra formula is expressed as:

U _A+ U+ U _C=1, no U _A, or do not have U _B, or do not have Uc output is all arranged.

With realizing promptly with door:

Here by YM7 as and door, electronic switch K4 of 4066 has finished the alarming logic requirement with R3 formation not gate.Again through YM8 and electric current I, second signal 06 with, promptly produce correct alerting signal: electric current is arranged, do not have arbitrary phase voltage K4 is opened, alarm lamp JD and hummer FM have light, generation.The shift electrician can be handled early.

Can supervise and measure the open-phase fault of supply line according to the scheme that the utility model provides, and directly show phase shortage accumulation hour data with liquid crystal display, meet the traditional custom with the kilowatt-hour meter degree of power system. How many days supervisory personnel need not go to calculate every month again, and every day how many hours. The statistics electric quantity loss only needs the numeral on the display be multiply by this unit average electric power kilowatt number, namely gets charge value, and is convenient and accurate. The utility model also has ingenious, the simple in structure advantage of design, can be widely used as the supervision instrument of power department phase shortage metering.

Claims (5)

1, a kind of phase failure calculagraph that adds up, it is by voltage sample circuit, current sampling circuit, decompression decision logic circuity, totalizer and corresponding display are formed, it is characterized in that, it also is provided with a time-base generator 1, summation pulse generator 2 and timing impulse generator 3, described time-base generator produce one 36 seconds be the cycle count signal in cycle, described summation pulse generator 2 be one three with a YM ₃, its three incoming lines meet frequency divider CD respectively ₄₀₄₀06,07,011 output pin, described timing impulse generator also is one or three AND circuit, its three incoming lines connect 06,07,011 output pin of frequency divider, 07 is that 07 output pin is through not gate F ₁Anti-phase acquisition, summation pulse signal and sprocket pulse signal all cause the decompression decision logic circuity respectively as the control signal that adds up with timing operation.

2, calculagraph according to claim 1, it is characterized in that, the decompression decision logic circuity is by forming with door YM4, YM5, YM6 and not gate F2, F3, F4, F5, F6, each with the door three incoming lines in, article one, through not gate F2(or F3, F4) connect voltage sample circuit, article one, meet sprocket pulse output line T1, another connects current sampling circuit behind not gate F5, the F6 of two series connection, with the electronic switch of the output termination totalizer of door.

3, calculagraph according to claim 2, it is characterized in that, add up timing displaing circuit by totalizer 9,10,11, display 12,13,14 and electronic switch K1, K2, K3, K4, K5, K6, K7 form, wherein, the data input pin 36,39 of totalizer meets sprocket pulse electronic switch K1 or K2, K3, and its operating control signal pin 34,42 that adds up meets summation pulse electronic switch K5 or K6, K7.

4, calculagraph according to claim 3, it is characterized in that, it also is provided with a sound light alarming circuit, described sound light alarming circuit by with door YM7, YM8, electronic switch K4, K8, resistance R 3 and alarm lamp JD and hummer FM form, wherein, three incoming lines of YM7 connect the correspondent voltage sample circuit respectively, and in three incoming lines of YM8, one meets not gate F6, article one, connect the 3rd pin of frequency divider CD4040, article one, connect the series side of analog switch K4 and resistance R 3, its output line meets electronic switch K8, and the circuit that the latter then controls JD and FM opens and closes.

5, calculagraph according to claim 4, it is characterized in that it also is provided with a power supply floating charge circuit, described floating charging routing resistance R8 and diode D series connection constitute, another termination voltage of R3 or the DC side of current sampling circuit, the positive pole of another termination power of D.

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