CN213637494U - Voltage generation module and power management chip - Google Patents
Voltage generation module and power management chip Download PDFInfo
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- CN213637494U CN213637494U CN202022755999.4U CN202022755999U CN213637494U CN 213637494 U CN213637494 U CN 213637494U CN 202022755999 U CN202022755999 U CN 202022755999U CN 213637494 U CN213637494 U CN 213637494U
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Abstract
The utility model provides a voltage generation module and power management chip. The voltage generation module comprises a reference voltage generation circuit, a comparison circuit, a switch circuit and a voltage control circuit; a reference voltage generation circuit generates a first reference voltage and a second reference voltage; the comparison circuit provides a turn-on control signal or a turn-off control signal; the voltage control circuit controls an output voltage signal output by the voltage output end according to the first reference voltage when the switch circuit is disconnected between the control input end and the voltage output end. The utility model provides a current voltage generation module can not be under the prerequisite that does not set up extra mask layer or band gap reference module, accurate generation output voltage signal to when input voltage is less than predetermined output voltage, output voltage signal is input voltage, is higher than when input voltage during predetermined output voltage, output voltage signal's voltage value is stable at the problem of settlement voltage value.
Description
Technical Field
The utility model relates to a voltage generation technical field especially relates to a voltage generation module and power management chip.
Background
For a power management chip with a wide input voltage range (2.5V-45V), an additional voltage VDD needs to be generated as a power supply for an internal core circuit. When the input voltage is lower than a set value of VDD, VDD follows the input voltage; when the input voltage is higher than a set value of VDD, VDD stabilizes at a predetermined value. The conventional voltage generation module for generating VDD cannot accurately generate VDD on the premise of not providing an additional mask layer or a bandgap reference module.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a main aim at provides a voltage generation module and power management chip solves current voltage generation module and can not be under the prerequisite that does not set up extra mask layer or band gap reference module, accurate generation output voltage signal to when input voltage is less than predetermined output voltage, output voltage signal is input voltage, is higher than when input voltage during predetermined output voltage, output voltage signal's voltage value is stable at the problem of settlement voltage value.
In order to achieve the above object, the present invention provides a voltage generating module, comprising a reference voltage generating circuit, a comparing circuit, a switching circuit and a voltage control circuit, wherein,
the reference voltage generating circuit is respectively electrically connected with an input end, a first reference voltage end and a second reference voltage end, and is used for generating a first reference voltage and a second reference voltage according to the input voltage provided by the input end, outputting the first reference voltage through the first reference voltage end, and outputting the second reference voltage through the second reference voltage end;
the comparison circuit is respectively electrically connected with the input end and the second reference voltage end, and is used for comparing the second reference voltage with the input voltage, providing a starting control signal for the control end of the switch circuit when the input voltage is smaller than the second reference voltage, and providing a stopping control signal for the control end of the switch circuit when the input voltage is larger than the second reference voltage;
the control end of the switch circuit is electrically connected with the comparison circuit, the first end of the switch circuit is electrically connected with the input end, the second end of the switch circuit is electrically connected with the voltage output end, the switch circuit is used for controlling the input end to be communicated with the voltage output end when the control end of the switch circuit receives the starting control signal, and is also used for controlling the input end to be disconnected with the voltage output end when the control end receives the stopping control signal;
the voltage control circuit is respectively electrically connected with the first reference voltage end and the voltage output end and is used for controlling an output voltage signal output by the voltage output end according to the first reference voltage when the switch circuit controls the disconnection between the input end and the voltage output end.
Optionally, the reference voltage generating circuit includes a first generating branch, a second generating branch, and a third generating branch; the first generating branch comprises a first control end, the second generating branch comprises a second control end, and the third generating branch comprises a third control end; the first control end, the second control end and the third control end are electrically connected with each other;
a first current flowing through the first generating branch, a second current flowing through the second generating branch, and a third current flowing through the third generating branch are equal;
the first generating branch is electrically connected with the input end and used for generating the first current according to the input voltage;
the second generation branch is electrically connected with the first reference voltage end and used for generating the second current according to the first reference voltage end;
the third generating branch is electrically connected to the second reference voltage terminal, and is configured to generate the third current according to the second reference voltage.
Optionally, the first generating branch includes a first generating transistor, a second generating transistor, a first resistor, a second resistor, a first control transistor, a second control transistor, and a third control transistor, wherein,
a first electrode of the first control transistor is electrically connected with the input end, and a control electrode of the first control transistor and a second electrode of the first control transistor are both electrically connected with the first control end;
a control electrode of the second control transistor is electrically connected with the first control end, a first electrode of the second control transistor is electrically connected with the input end, and a second electrode of the second control transistor is electrically connected with the first electrode of the first generation transistor;
a control electrode of the third control transistor is electrically connected with a start control end and the first electrode of the first generating transistor respectively, a first electrode of the third control transistor is electrically connected with the first control end, and a second electrode of the third control transistor is electrically connected with the control electrode of the first generating transistor and the first end of the first resistor respectively;
a second pole of the first generating transistor is electrically connected with a second end of the first resistor and a first voltage end respectively;
a first end of the second resistor is electrically connected to a second pole of the third control transistor, and a second end of the second resistor is electrically connected to a first pole of the second generating transistor;
a control electrode of the second generating transistor is electrically connected to a first electrode of the second generating transistor, and a second electrode of the second generating transistor is electrically connected to a second end of the first resistor;
the first current is the sum of the current flowing through the first resistor and the current flowing through the second resistor.
Optionally, the first generating transistor and the second generating transistor are NPN-type triodes;
the first control transistor and the second control transistor are P-type transistors, and the third control transistor is an N-type transistor.
Optionally, the second generating branch includes a fourth control transistor and a third resistor circuit;
a control electrode of the fourth control transistor is electrically connected with the second control end, a first electrode of the fourth control transistor is electrically connected with the input end, and a second electrode of the fourth control transistor is electrically connected with the first voltage end through the third resistor circuit;
the second current is a current flowing through the third resistance circuit.
Optionally, the third resistor circuit includes at least one third resistor connected in series with each other;
the fourth control transistor is a P-type transistor.
Optionally, the third generating circuit includes a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor, and a fourth resistor;
a control electrode of the fifth control transistor is electrically connected with the third control end, a first electrode of the fifth control transistor is electrically connected with the input end, and a second electrode of the fifth control transistor is electrically connected with a first end of the fourth resistor;
a control electrode of the sixth control transistor is electrically connected to the third control terminal, a first electrode of the sixth control transistor is electrically connected to the input terminal, and a second electrode of the sixth control transistor is electrically connected to the first electrode of the eighth control transistor;
a control electrode of the seventh control transistor is electrically connected to a control electrode of the eighth control transistor, a first electrode of the seventh control transistor is electrically connected to the second end of the fourth resistor, and a second electrode of the seventh control transistor is electrically connected to the second electrode of the eighth control transistor;
a control electrode of the eighth control transistor is electrically connected to a first electrode of the eighth control transistor, and a second electrode of the eighth control transistor is electrically connected to the first voltage terminal;
a first end of the fourth resistor is electrically connected to the second reference voltage terminal.
Optionally, the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are P-type transistors.
Optionally, the comparison circuit includes a first comparison transistor, a second comparison transistor, a third comparison transistor, and a fourth comparison transistor;
a control electrode of the first comparison transistor is electrically connected with a control electrode of the second comparison transistor, a first electrode of the first comparison transistor is electrically connected with the input end, and a second electrode of the first comparison transistor is electrically connected with a control end of the switch circuit;
a control electrode of the second comparison transistor is electrically connected with a second electrode of the second comparison transistor, a first electrode of the second comparison transistor is electrically connected with the input end, and a second electrode of the second comparison transistor is electrically connected with a first end of the fourth resistor;
a control electrode of the third comparison transistor is electrically connected with a starting control end, a first electrode of the third comparison transistor is electrically connected with a control end of the switch circuit, and a second electrode of the third comparison transistor is electrically connected with a first voltage end;
a control electrode of the fourth comparison transistor is electrically connected to a control electrode of the third comparison transistor, a first electrode of the fourth comparison transistor is electrically connected to a second terminal of the fourth resistor, and a second electrode of the fourth comparison transistor is electrically connected to the first voltage terminal.
Optionally, the first comparison transistor and the second comparison transistor are both P-type transistors, and the third comparison transistor and the fourth comparison transistor are both N-type transistors.
Optionally, the switching circuit comprises a switching transistor;
the control electrode of the switch transistor is the control end of the switch circuit, the first electrode of the switch transistor is the first end of the switch circuit, and the second electrode of the switch transistor is the second end of the switch circuit.
Optionally, the switching transistor is a P-type transistor.
Optionally, the voltage control circuit includes a buffer, a voltage control transistor, and a control capacitor;
the input end of the buffer is electrically connected with the first reference voltage end, and the output end of the buffer is electrically connected with the control electrode of the voltage control transistor; the buffer is used for providing the first reference voltage to a control electrode of the voltage control transistor;
a first pole of the voltage control transistor is electrically connected with the input end, and a second pole of the voltage control transistor is electrically connected with the voltage output end;
the first end of the control capacitor is electrically connected with the output end of the buffer, and the second end of the control capacitor is electrically connected with the first voltage end.
Optionally, the voltage control transistor is an N-type transistor.
Optionally, the voltage generating module of the present invention further includes a ninth control transistor; the reference voltage generating circuit comprises a second generating branch; the second generating branch comprises a fourth control transistor and a third resistance circuit;
a second pole of the fourth control transistor is electrically connected with the third resistance circuit through the ninth control transistor;
and the control electrode of the ninth control transistor is electrically connected with the input end of the buffer, the first electrode of the ninth control transistor is electrically connected with the second electrode of the fourth control transistor, and the second electrode of the ninth control transistor is electrically connected with the first voltage end through the third resistor circuit.
Optionally, the ninth control transistor is an N-type transistor.
The utility model also provides a power management chip, generate the module including foretell voltage.
The embodiment of the utility model provides a voltage generation module and power management chip have adopted reference voltage generation circuit, comparison circuit, switch circuit and voltage control circuit, can generate according to input voltage output voltage signal; when the input voltage is lower than the preset output voltage, the output voltage signal is the input voltage, and when the input voltage is higher than the preset output voltage, the voltage value of the output voltage signal is stabilized at the set voltage value. The embodiment of the utility model provides a voltage generate module's structure uncomplicated, and the embodiment of the utility model provides a voltage generate module need not extra mask layer and Bandgap (band gap benchmark) module.
Drawings
Fig. 1 is a structural diagram of a voltage generation module according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a voltage generation module according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a voltage generating module according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The transistors adopted in all the embodiments of the utility model can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, to distinguish the two electrodes of the transistor except the control electrode, one of the two electrodes is referred to as a first electrode, and the other electrode is referred to as a second electrode.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode.
The voltage generating module according to the embodiment of the present invention comprises a reference voltage generating circuit 11, a comparing circuit 12, a switching circuit 13 and a voltage control circuit 14, wherein,
the reference voltage generating circuit 11 is electrically connected to an input terminal, a first reference voltage terminal Vt1 and a second reference voltage terminal Vt2, respectively, and is configured to generate a first reference voltage Vreg and a second reference voltage Vldo according to an input voltage VIN provided by the input terminal, output the first reference voltage Vreg through the first reference voltage terminal Vt1, and output the second reference voltage Vldo through the second reference voltage terminal Vt 2;
the comparison circuit 12 is electrically connected to the input terminal and the second reference voltage terminal Vt2, and configured to compare the second reference voltage Vldo and the input voltage VIN, provide an on control signal to the control terminal of the switch circuit 13 when the input voltage VIN is smaller than the second reference voltage Vldo, and provide an off control signal to the control terminal of the switch circuit 13 when the input voltage VIN is greater than the second reference voltage Vldo;
the control terminal of the switch circuit 13 is electrically connected to the comparison circuit 12, the first terminal of the switch circuit 13 is electrically connected to the input terminal, the second terminal of the switch circuit 13 is electrically connected to the voltage output terminal O1, the switch circuit 13 is configured to control the input terminal to be connected to the voltage output terminal O1 when the control terminal receives the on control signal, and is further configured to control the input terminal to be disconnected from the voltage output terminal O1 when the control terminal receives the off control signal;
the voltage control circuit 14 is electrically connected to the first reference voltage terminal Vt1 and the voltage output terminal O1, respectively, and is configured to control the output voltage signal output by the voltage output terminal O1 according to the first reference voltage Vreg when the switch circuit controls the disconnection between the input terminal and the voltage output terminal O1.
The embodiment of the utility model provides a voltage generation module has adopted reference voltage generation circuit 11, comparison circuit 12, switch circuit 13 and voltage control circuit 14, can generate according to input voltage VIN output voltage signal; when the input voltage VIN is lower than the predetermined output voltage, the output voltage signal is the input voltage VIN, and when the input voltage VIN is higher than the predetermined output voltage, the voltage value of the output voltage signal is stabilized at the set voltage value. The embodiment of the utility model provides a voltage generation module's structure uncomplicated, and the embodiment of the utility model provides a voltage generation module do not need extra mask layer and Bandgap (band gap benchmark) module to the output voltage signal that produces does not receive the temperature to influence, and can be when input voltage is lower (for example, be less than 3V) fine following input voltage, satisfy low pressure work demand.
In particular implementation, the reference voltage generating circuit may include a first generating branch, a second generating branch, and a third generating branch; the first generating branch comprises a first control end, the second generating branch comprises a second control end, and the third generating branch comprises a third control end; the first control end, the second control end and the third control end are electrically connected with each other;
a first current flowing through the first generating branch, a second current flowing through the second generating branch, and a third current flowing through the third generating branch are equal;
the first generating branch is electrically connected with the input end and used for generating the first current according to the input voltage;
the second generation branch is electrically connected with the first reference voltage end and used for generating the second current according to the first reference voltage end;
the third generating branch is electrically connected to the second reference voltage terminal, and is configured to generate the third current according to the second reference voltage.
In an embodiment of the present invention, the reference voltage generating circuit may include a first generating branch, a second generating branch, and a third generating branch, the first generating branch generating the first current according to the input voltage, the second generating branch generating the second current according to the first reference voltage terminal; the third generating branch generates the third current according to the second reference voltage, and the first control terminal, the second control terminal and the third control terminal are electrically connected to each other, so that the first current flowing through the first generating branch, the second current flowing through the second generating branch and the third current flowing through the third generating branch are equal, thereby obtaining a first reference voltage independent of temperature and a second reference voltage independent of temperature.
Optionally, the first generating branch includes a first generating transistor, a second generating transistor, a first resistor, a second resistor, a first control transistor, a second control transistor, and a third control transistor, wherein,
a first electrode of the first control transistor is electrically connected with the input end, and a control electrode of the first control transistor and a second electrode of the first control transistor are both electrically connected with the first control end;
a control electrode of the second control transistor is electrically connected with the first control end, a first electrode of the second control transistor is electrically connected with the input end, and a second electrode of the second control transistor is electrically connected with the first electrode of the first generation transistor;
a control electrode of the third control transistor is electrically connected with a start control end and the first electrode of the first generating transistor respectively, a first electrode of the third control transistor is electrically connected with the first control end, and a second electrode of the third control transistor is electrically connected with the control electrode of the first generating transistor and the first end of the first resistor respectively;
a second pole of the first generating transistor is electrically connected with a second end of the first resistor and a first voltage end respectively;
a first end of the second resistor is electrically connected to a second pole of the third control transistor, and a second end of the second resistor is electrically connected to a first pole of the second generating transistor;
a control electrode of the second generating transistor is electrically connected to a first electrode of the second generating transistor, and a second electrode of the second generating transistor is electrically connected to a second end of the first resistor;
the first current is the sum of the current flowing through the first resistor and the current flowing through the second resistor.
In specific implementation, the starting control end can be electrically connected with a starting control circuit;
the start-up control circuit may be configured to output a start-up control current signal when performing voltage generation.
Optionally, the first voltage terminal may be a ground terminal or a low voltage terminal, but is not limited thereto.
In an embodiment of the present invention, the first generating transistor and the second generating transistor are NPN transistors;
the first control transistor and the second control transistor are P-type transistors, and the third control transistor is an N-type transistor;
but not limited thereto.
Optionally, the second generating branch includes a fourth control transistor and a third resistor circuit;
a control electrode of the fourth control transistor is electrically connected with the second control end, a first electrode of the fourth control transistor is electrically connected with the input end, and a second electrode of the fourth control transistor is electrically connected with the first voltage end through the third resistor circuit;
the second current is a current flowing through the third resistance circuit.
In a specific implementation, the third resistor circuit may include at least one third resistor connected in series with each other;
the fourth control transistor is a P-type transistor, but not limited thereto.
Optionally, the third generating circuit includes a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor, and a fourth resistor;
a control electrode of the fifth control transistor is electrically connected with the third control end, a first electrode of the fifth control transistor is electrically connected with the input end, and a second electrode of the fifth control transistor is electrically connected with a first end of the fourth resistor;
a control electrode of the sixth control transistor is electrically connected to the third control terminal, a first electrode of the sixth control transistor is electrically connected to the input terminal, and a second electrode of the sixth control transistor is electrically connected to the first electrode of the eighth control transistor;
a control electrode of the seventh control transistor is electrically connected to a control electrode of the eighth control transistor, a first electrode of the seventh control transistor is electrically connected to the second end of the fourth resistor, and a second electrode of the seventh control transistor is electrically connected to the second electrode of the eighth control transistor;
a control electrode of the eighth control transistor is electrically connected to a first electrode of the eighth control transistor, and a second electrode of the eighth control transistor is electrically connected to the first voltage terminal;
a first end of the fourth resistor is electrically connected to the second reference voltage terminal.
In an embodiment of the present invention, the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are P-type transistors, but not limited thereto.
Optionally, the comparison circuit includes a first comparison transistor, a second comparison transistor, a third comparison transistor, and a fourth comparison transistor;
a control electrode of the first comparison transistor is electrically connected with a control electrode of the second comparison transistor, a first electrode of the first comparison transistor is electrically connected with the input end, and a second electrode of the first comparison transistor is electrically connected with a control end of the switch circuit;
a control electrode of the second comparison transistor is electrically connected with a second electrode of the second comparison transistor, a first electrode of the second comparison transistor is electrically connected with the input end, and a second electrode of the second comparison transistor is electrically connected with a first end of the fourth resistor;
a control electrode of the third comparison transistor is electrically connected with a starting control end, a first electrode of the third comparison transistor is electrically connected with a control end of the switch circuit, and a second electrode of the third comparison transistor is electrically connected with a first voltage end;
a control electrode of the fourth comparison transistor is electrically connected to a control electrode of the third comparison transistor, a first electrode of the fourth comparison transistor is electrically connected to a second terminal of the fourth resistor, and a second electrode of the fourth comparison transistor is electrically connected to the first voltage terminal.
In an embodiment of the present invention, the first comparing transistor and the second comparing transistor are both P-type transistors, and the third comparing transistor and the fourth comparing transistor are both N-type transistors, but not limited thereto.
Optionally, the switching circuit comprises a switching transistor;
the control electrode of the switch transistor is the control end of the switch circuit, the first electrode of the switch transistor is the first end of the switch circuit, and the second electrode of the switch transistor is the second end of the switch circuit.
In an embodiment of the present invention, the switch transistor may be a P-type transistor, but is not limited thereto.
Optionally, the voltage control circuit includes a buffer, a voltage control transistor, and a control capacitor;
the input end of the buffer is electrically connected with the first reference voltage end, and the output end of the buffer is electrically connected with the control electrode of the voltage control transistor; the buffer is used for providing the first reference voltage to a control electrode of the voltage control transistor;
a first pole of the voltage control transistor is electrically connected with the input end, and a second pole of the voltage control transistor is electrically connected with the voltage output end;
the first end of the control capacitor is electrically connected with the output end of the buffer, and the second end of the control capacitor is electrically connected with the first voltage end.
In specific implementation, the buffer can improve the driving capability of the output end.
In an embodiment of the present invention, the voltage control transistor is an N-type transistor, but not limited thereto.
As shown in fig. 2, on the basis of the embodiment of the voltage generation module shown in fig. 1, the voltage generation module further includes a start control circuit 20; the reference voltage generating circuit may comprise a first generating branch 21, a second generating branch 22 and a third generating branch 23;
the first generating branch 21 includes a first generating transistor Q1, a second generating transistor Q2, a first resistor R1, a second resistor R2, a first control transistor M1, a second control transistor M2, and a third control transistor M3, wherein,
the source electrode of the first control transistor M1 is electrically connected with the input end, and the gate electrode of the first control transistor M1 and the drain electrode of the first control transistor M1 are both electrically connected with a first control end; the input end is used for providing an input voltage VIN; the first control end, the second control end and the third control end are electrically connected with each other;
the gate of the second control transistor M2 is electrically connected to the first control terminal, the source of the second control transistor M2 is electrically connected to the input terminal, and the drain of the second control transistor M2 is electrically connected to the collector of the first generating transistor Q1;
the gates of the third control transistor M3 are electrically connected to the start control terminal S1 and the collector of the first generating transistor Q1, respectively, the drain of the third control transistor M3 is electrically connected to the first control terminal, and the source of the third control transistor M3 is electrically connected to the base of the first generating transistor Q1 and the first terminal of the first resistor R1, respectively;
the emitters of the first generating transistor Q2 are respectively and electrically connected with the second end of the first resistor R1 and the ground end GND;
a first terminal of the second resistor R2 is electrically connected to the drain of the third control transistor M3, and a second terminal of the second resistor R2 is electrically connected to the collector of the second generating transistor Q2;
the base of the second generating transistor Q2 is electrically connected to the collector of the second generating transistor Q2, and the emitter of the second generating transistor Q2 is electrically connected to the second terminal of the first resistor R1;
the second generating branch 22 comprises a fourth control transistor M4 and a third resistance circuit R3;
the gate of the fourth control transistor M4 is electrically connected to the second control terminal, the source of the fourth control transistor M4 is electrically connected to the input terminal, and the drain of the fourth control transistor M4 is electrically connected to the ground terminal GND through the third resistor circuit R3;
the third generating circuit 23 includes a fifth control transistor M5, a sixth control transistor M6, a seventh control transistor M7, an eighth control transistor M8, and a fourth resistor R4;
the gate of the fifth control transistor M5 is electrically connected to the third control terminal, the source of the fifth control transistor M5 is electrically connected to the input terminal, and the drain of the fifth control transistor M5 is electrically connected to the first terminal of the fourth resistor R4;
the gate of the sixth control transistor M6 is electrically connected to the third control terminal, the source of the sixth control transistor M6 is electrically connected to the input terminal, and the drain of the sixth control transistor M6 is electrically connected to the source of the eighth control transistor M8;
the gate of the seventh control transistor M7 is electrically connected to the gate of the eighth control transistor M8, the drain of the seventh control transistor M7 is electrically connected to the second end of the fourth resistor R4, and the source of the seventh control transistor M7 is electrically connected to the drain of the eighth control transistor M8;
the gate of the eighth control transistor M8 is electrically connected with the drain of the eighth control transistor M8, and the source of the eighth control transistor M8 is electrically connected with the ground terminal GND;
a first end of the fourth resistor R4 is electrically connected to a second reference voltage terminal Vt 2;
the comparison circuit 12 includes a first comparison transistor M11, a second comparison transistor M12, a third comparison transistor M13, and a fourth comparison transistor M14;
the gate of the first comparison transistor M11 is electrically connected with the gate of the second comparison transistor M12, the source of the first comparison transistor M11 is electrically connected with the input terminal, and the drain of the first comparison transistor M11 is electrically connected with the gate of the switch transistor M0;
the gate of the second comparison transistor M12 is electrically connected with the drain of the second comparison transistor M12, the source of the second comparison transistor M12 is electrically connected with the input terminal, and the drain of the second comparison transistor M12 is electrically connected with the first terminal of the fourth resistor R1;
the gate of the third comparison transistor M13 is electrically connected with the start control circuit 20, the drain of the third comparison transistor M13 is electrically connected with the gate of the switch transistor M0, and the source of the third comparison transistor M13 is electrically connected with the ground terminal GND; the starting control circuit 20 is used for outputting starting control current when voltage generation is carried out, so that M1, M2, M3 and Q1 work normally;
the gate of the fourth comparison transistor M14 is electrically connected with the gate of the third comparison transistor M13, the drain of the fourth comparison transistor M14 is electrically connected with the second end of the fourth resistor R4, and the source of the fourth comparison transistor M14 is electrically connected with the ground end GND;
the switching circuit 13 includes a switching transistor M0;
the gate of the switch transistor M0 is the control terminal of the switch circuit 13, the source of the switch transistor M0 is the first terminal of the switch circuit 13, and the drain of the switch transistor M0 is the second terminal of the switch circuit 13;
the source of the switch transistor M0 is electrically connected with the input terminal, and the drain of the switch transistor M0 is electrically connected with the voltage output terminal O1;
the voltage control circuit 14 comprises a buffer B1, a voltage control transistor M20 and a control capacitor C0;
an input terminal of the buffer B1 is electrically connected to the first reference voltage terminal Vt1, and an output terminal of the buffer B1 is electrically connected to the gate of the voltage control transistor M20; the buffer B1 is used to provide the first reference voltage Vreg to the gate of the voltage control transistor M20, so as to enhance the driving capability of the gate of M20 (in the embodiment of the present invention, since the size of M20 is larger, the driving capability of the gate of M20 needs to be improved);
the drain of the voltage control transistor M20 is electrically connected with the input terminal, and the source of the voltage control transistor M20 is electrically connected with the voltage output terminal O1;
the first end of the control capacitor C0 is electrically connected to the output end of the buffer B1, and the second end of the control capacitor C0 is electrically connected to the ground GND.
In the embodiment shown in fig. 2, the reference numeral C1 is a first capacitor, a first terminal of C1 is electrically connected to the voltage output terminal O1, and a second terminal of C1 is electrically connected to the ground terminal GND.
In the embodiment shown in fig. 2, Q1 and Q2 are NPN transistors, M1 and M2 are PMOS transistors (P-type metal-oxide-semiconductor transistors), M3 is NMOS transistors (N-type metal-oxide-semiconductor transistors), M4 is PMOS transistors, M5 and M6 are PMOS transistors, M7 and M8 are NMOS transistors, M11 and M12 are PMOS transistors, and M13 and M14 are NMOS transistors; m0 is a PMOS transistor, M20 is an NMOS transistor, but not limited thereto.
In the embodiment shown in fig. 2, when generating the voltage, the start control circuit 20 provides a start control current signal, and charges the parasitic capacitance of the gate of M3 through the start control current signal to raise the potential of the gate of M3, so that M3, M13, and M14 are all turned on, but not limited thereto.
In operation of the embodiment of the voltage generating module shown in figure 2 of the present invention,
m4 mirrors the current of M1 and this current flows through R3 to get Vreg; the ratio of the current flowing through M4 to the current flowing through M1 is equal to the ratio K1 between the width-to-length ratio of M4 and the width-to-length ratio of M1, and the current flowing through M1 flows through R3 to obtain Vreg; by selecting the ratio of the resistance value R2z of R2 to the resistance value R1z of R1, Vreg can be made independent of temperature; wherein K1 is a positive number;
m5 mirrors the current of M1, and this current flows through R4, generating Vldo across R4; the ratio of the current flowing through M5 to the current flowing through M1 is equal to the ratio K2 between the width-length ratio of M5 and the width-length ratio of M1, and Vldo is independent of temperature by selecting the ratio of the resistance value R2z of R2 to the resistance value R1z of R1; wherein K2 is a positive number;
the current flowing through R1 is equal to Vbe _ Q1/R1, the current flowing through R2 is equal to Δ Vbe/R2;
wherein Δ Vbe is equal to Vbe _ Q2-Vbe _ Q1;
the current flowing through R3 is equal to (Vbe _ Q1/R1z + Δ Vbe/R2z) XK 1;
when M12 is turned off, the current flowing through R4 is equal to (Vbe _ Q1/R1z + Δ Vbe/R2z) XK 2;
wherein Vreg is a first reference voltage, Vldo is a second reference voltage, Vbe _ Q1 is the voltage between the base of Q1 and the emitter of Q1, Vbe _ Q2 is the voltage between the base of Q2 and the emitter of Q2; Δ Vbe is equal to the difference of Vbe _ Q2 and Vbe _ Q1;
according to the proportional relation of the currents, Vreg and Vldo can be obtained, and the Vreg and Vldo are independent of the temperature;
when voltage generation is carried out, under the control of a starting control current provided by S1, the related circuit starts to work, when VIN is smaller than Vldo, M11 and M12 are both turned off, the grid of M0 is connected to a ground end GND through M13, M0 is turned on, and an output voltage signal output by O1 is an input voltage VIN;
m11, M12, M13 and M14 form a comparator, VIN and Vldo are compared, when VIN increases and the difference between VIN and Vldo is larger than the absolute value of the threshold voltage of M12, M11 and M12 are turned on, then the gate of M0 and the source of M0 are both connected to VIN, M0 is turned off, at this time, the output voltage signal output by O1 is controlled by M20, M20 is in a saturation region (the gate-source voltage of M20 is larger than the threshold voltage Vth _ M20 of M20), and the voltage value of the output voltage signal is equal to Vreg-Vth _ M20. As VIN continues to increase, O1 continues to output an output voltage signal that is unaffected by VIN because M20 is always in the saturation region.
In the embodiment of the present invention, since Vbe _ Q1 is negatively correlated with temperature, Δ Vbe is negatively correlated with temperature, and Vreg and Vldo can be made independent of temperature by selecting the ratio of the resistance R2z of R2 to the resistance R1z of R1.
The embodiment of the voltage generation module shown in fig. 2 of the present invention is operated, Vreg depends on the ratio of the resistance value of R3 to the resistance value of R1, and the ratio of the resistance value of R3 to the resistance value of R2 is independent of temperature.
Optionally, the voltage generation module according to the embodiment of the present invention further includes a ninth control transistor;
a second pole of the fourth control transistor is electrically connected with the third resistance circuit through the ninth control transistor;
and the control electrode of the ninth control transistor is electrically connected with the input end of the buffer, the first electrode of the ninth control transistor is electrically connected with the second electrode of the fourth control transistor, and the second electrode of the ninth control transistor is electrically connected with the first voltage end through the third resistor circuit.
In an embodiment of the present invention, the ninth control transistor may be an N-type transistor, but is not limited thereto.
As shown in fig. 3, on the basis of the embodiment of the voltage generating module shown in fig. 2, the voltage generating module according to the embodiment of the present invention further includes a ninth control transistor M30;
m4 is electrically connected to R3 through M30;
the gate of M30 is electrically connected with the input end of the buffer B1, the gate of M30 is electrically connected with the drain of M30, the drain of M30 is electrically connected with the drain of M4, and the source of M30 is electrically connected with the ground end GND through the third resistance circuit R3.
In the embodiment shown in fig. 3, M30 is an NMOS transistor, but not limited thereto.
The embodiment shown in fig. 3 of the present invention is different from the embodiment shown in fig. 2 in the working process:
when VIN increases and the difference between VIN and Vldo is greater than the absolute value of the threshold voltage of M12, M11 and M12 are turned on, then the gate of M0 and the source of M0 are both connected to VIN, M0 is turned off, at this time, the output voltage signal output by O1 is controlled by M20, M20 is in the saturation region (the gate-source voltage of M20 is greater than the threshold voltage Vth _ M20 of M20), at this time, M30 is also in the saturation region, and the voltage value of the output voltage signal is equal to Vreg + Vth _ M30-Vth _ M20; as VIN continues to increase, O1 continues to output an output voltage signal that is unaffected by VIN because M20 is always in the saturation region.
Since M30 and M20 are the same type of transistor, Vth _ M30 and Vth _ M20 can be made approximately equal, so that the voltage value of the output voltage signal is equal to Vreg when VIN is large.
The embodiment of the utility model provides a power management chip include foretell voltage generation module.
The embodiment of the utility model provides a display device can be any products or parts that have the display function such as cell-phone, panel computer, TV set, display, notebook computer, digital photo holder frame, navigator.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (17)
1. A voltage generation module comprises a reference voltage generation circuit, a comparison circuit, a switch circuit and a voltage control circuit,
the reference voltage generating circuit is respectively electrically connected with an input end, a first reference voltage end and a second reference voltage end, and is used for generating a first reference voltage and a second reference voltage according to the input voltage provided by the input end, outputting the first reference voltage through the first reference voltage end, and outputting the second reference voltage through the second reference voltage end;
the comparison circuit is respectively electrically connected with the input end and the second reference voltage end, and is used for comparing the second reference voltage with the input voltage, providing a starting control signal for the control end of the switch circuit when the input voltage is smaller than the second reference voltage, and providing a stopping control signal for the control end of the switch circuit when the input voltage is larger than the second reference voltage;
the control end of the switch circuit is electrically connected with the comparison circuit, the first end of the switch circuit is electrically connected with the input end, the second end of the switch circuit is electrically connected with the voltage output end, the switch circuit is used for controlling the input end to be communicated with the voltage output end when the control end of the switch circuit receives the starting control signal, and is also used for controlling the input end to be disconnected with the voltage output end when the control end receives the stopping control signal;
the voltage control circuit is respectively electrically connected with the first reference voltage end and the voltage output end and is used for controlling an output voltage signal output by the voltage output end according to the first reference voltage when the switch circuit controls the disconnection between the input end and the voltage output end.
2. The voltage generating module of claim 1, wherein the reference voltage generating circuit comprises a first generating branch, a second generating branch, and a third generating branch; the first generating branch comprises a first control end, the second generating branch comprises a second control end, and the third generating branch comprises a third control end; the first control end, the second control end and the third control end are electrically connected with each other;
a first current flowing through the first generating branch, a second current flowing through the second generating branch, and a third current flowing through the third generating branch are equal;
the first generating branch is electrically connected with the input end and used for generating the first current according to the input voltage;
the second generation branch is electrically connected with the first reference voltage end and used for generating the second current according to the first reference voltage end;
the third generating branch is electrically connected to the second reference voltage terminal, and is configured to generate the third current according to the second reference voltage.
3. The voltage generating module of claim 2 wherein the first generating branch comprises a first generating transistor, a second generating transistor, a first resistor, a second resistor, a first control transistor, a second control transistor, and a third control transistor, wherein,
a first electrode of the first control transistor is electrically connected with the input end, and a control electrode of the first control transistor and a second electrode of the first control transistor are both electrically connected with the first control end;
a control electrode of the second control transistor is electrically connected with the first control end, a first electrode of the second control transistor is electrically connected with the input end, and a second electrode of the second control transistor is electrically connected with the first electrode of the first generation transistor;
a control electrode of the third control transistor is electrically connected with a start control end and the first electrode of the first generating transistor respectively, a first electrode of the third control transistor is electrically connected with the first control end, and a second electrode of the third control transistor is electrically connected with the control electrode of the first generating transistor and the first end of the first resistor respectively;
a second pole of the first generating transistor is electrically connected with a second end of the first resistor and a first voltage end respectively;
a first end of the second resistor is electrically connected to a second pole of the third control transistor, and a second end of the second resistor is electrically connected to a first pole of the second generating transistor;
a control electrode of the second generating transistor is electrically connected to a first electrode of the second generating transistor, and a second electrode of the second generating transistor is electrically connected to a second end of the first resistor;
the first current is the sum of the current flowing through the first resistor and the current flowing through the second resistor.
4. The voltage generating module of claim 3, wherein the first generating transistor and the second generating transistor are NPN transistors;
the first control transistor and the second control transistor are P-type transistors, and the third control transistor is an N-type transistor.
5. The voltage generating module of claim 2 wherein the second generating branch comprises a fourth control transistor and a third resistor circuit;
a control electrode of the fourth control transistor is electrically connected with the second control end, a first electrode of the fourth control transistor is electrically connected with the input end, and a second electrode of the fourth control transistor is electrically connected with the first voltage end through the third resistor circuit;
the second current is a current flowing through the third resistance circuit.
6. The voltage generating module of claim 5, wherein the third resistor circuit comprises at least one third resistor connected in series with each other;
the fourth control transistor is a P-type transistor.
7. The voltage generating module of claim 2, wherein the third generating circuit comprises a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor, and a fourth resistor;
a control electrode of the fifth control transistor is electrically connected with the third control end, a first electrode of the fifth control transistor is electrically connected with the input end, and a second electrode of the fifth control transistor is electrically connected with a first end of the fourth resistor;
a control electrode of the sixth control transistor is electrically connected to the third control terminal, a first electrode of the sixth control transistor is electrically connected to the input terminal, and a second electrode of the sixth control transistor is electrically connected to the first electrode of the eighth control transistor;
a control electrode of the seventh control transistor is electrically connected to a control electrode of the eighth control transistor, a first electrode of the seventh control transistor is electrically connected to the second end of the fourth resistor, and a second electrode of the seventh control transistor is electrically connected to the second electrode of the eighth control transistor;
a control electrode of the eighth control transistor is electrically connected to a first electrode of the eighth control transistor, and a second electrode of the eighth control transistor is electrically connected to a first voltage terminal;
a first end of the fourth resistor is electrically connected to the second reference voltage terminal.
8. The voltage generating module of claim 7, wherein the five control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are P-type transistors.
9. The voltage generating module of claim 7, wherein the comparison circuit comprises a first comparison transistor, a second comparison transistor, a third comparison transistor, and a fourth comparison transistor;
a control electrode of the first comparison transistor is electrically connected with a control electrode of the second comparison transistor, a first electrode of the first comparison transistor is electrically connected with the input end, and a second electrode of the first comparison transistor is electrically connected with a control end of the switch circuit;
a control electrode of the second comparison transistor is electrically connected with a second electrode of the second comparison transistor, a first electrode of the second comparison transistor is electrically connected with the input end, and a second electrode of the second comparison transistor is electrically connected with a first end of the fourth resistor;
a control electrode of the third comparison transistor is electrically connected with a starting control end, a first electrode of the third comparison transistor is electrically connected with a control end of the switch circuit, and a second electrode of the third comparison transistor is electrically connected with a first voltage end;
a control electrode of the fourth comparison transistor is electrically connected to a control electrode of the third comparison transistor, a first electrode of the fourth comparison transistor is electrically connected to a second terminal of the fourth resistor, and a second electrode of the fourth comparison transistor is electrically connected to the first voltage terminal.
10. The voltage generating module of claim 9, wherein the first and second comparison transistors are both P-type transistors, and the third and fourth comparison transistors are both N-type transistors.
11. The voltage generating module of any one of claims 1 to 10 wherein the switching circuit comprises a switching transistor;
the control electrode of the switch transistor is the control end of the switch circuit, the first electrode of the switch transistor is the first end of the switch circuit, and the second electrode of the switch transistor is the second end of the switch circuit.
12. The voltage generating module of claim 11 wherein the switching transistor is a P-type transistor.
13. The voltage generation module of any one of claims 1 to 10 wherein the voltage control circuit comprises a buffer, a voltage control transistor, and a control capacitor;
the input end of the buffer is electrically connected with the first reference voltage end, and the output end of the buffer is electrically connected with the control electrode of the voltage control transistor; the buffer is used for providing the first reference voltage to a control electrode of the voltage control transistor;
a first pole of the voltage control transistor is electrically connected with the input end, and a second pole of the voltage control transistor is electrically connected with the voltage output end;
the first end of the control capacitor is electrically connected with the output end of the buffer, and the second end of the control capacitor is electrically connected with the first voltage end.
14. The voltage generating module of claim 13 wherein the voltage control transistor is an N-type transistor.
15. The voltage generating module of claim 13, further comprising a ninth control transistor; the reference voltage generating circuit comprises a second generating branch; the second generating branch comprises a fourth control transistor and a third resistance circuit;
a second pole of the fourth control transistor is electrically connected with the third resistance circuit through the ninth control transistor;
and the control electrode of the ninth control transistor is electrically connected with the input end of the buffer, the first electrode of the ninth control transistor is electrically connected with the second electrode of the fourth control transistor, and the second electrode of the ninth control transistor is electrically connected with the first voltage end through the third resistor circuit.
16. The voltage generating module of claim 15 wherein the ninth control transistor is an N-type transistor.
17. A power management chip comprising a voltage generation module according to any one of claims 1 to 16.
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| CN202022755999.4U CN213637494U (en) | 2020-11-25 | 2020-11-25 | Voltage generation module and power management chip |
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| CN202022755999.4U CN213637494U (en) | 2020-11-25 | 2020-11-25 | Voltage generation module and power management chip |
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Address after: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee after: Beijing ESWIN Computing Technology Co.,Ltd. Patentee after: HEFEI YISIWEI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee before: Beijing yisiwei Computing Technology Co.,Ltd. Patentee before: HEFEI YISIWEI INTEGRATED CIRCUIT Co.,Ltd. |
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Address after: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee after: Beijing ESWIN Computing Technology Co.,Ltd. Patentee after: Hefei Yisiwei Computing Technology Co.,Ltd. Address before: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee before: Beijing ESWIN Computing Technology Co.,Ltd. Patentee before: HEFEI YISIWEI INTEGRATED CIRCUIT Co.,Ltd. |
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