CN213602424U - Lithium battery cathode protection circuit - Google Patents

Lithium battery cathode protection circuit Download PDF

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CN213602424U
CN213602424U CN202022166686.5U CN202022166686U CN213602424U CN 213602424 U CN213602424 U CN 213602424U CN 202022166686 U CN202022166686 U CN 202022166686U CN 213602424 U CN213602424 U CN 213602424U
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nmos transistor
well
nmos
deep
protection circuit
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贺江平
王俊喜
孙晓良
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Shenzhen Siyuan Semiconductor Co ltd
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Shenzhen Siyuan Semiconductor Co ltd
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02E60/10—Energy storage using batteries

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Abstract

The utility model provides a lithium battery cathode protection circuit, including first NMOS pipe, the second NMOS pipe, the third NMOS pipe, the fourth NMOS pipe, the fifth NMOS pipe, the triode, first resistance and second resistance, wherein, second NMOS pipe is managed to the fifth NMOS and is managed to connect in parallel each other with first NMOS after establishing ties between series connection and, the source connection power of first NMOS pipe, the drain electrode ground connection of first NMOS pipe, the projecting pole of triode is connected and is connected jointly with the source electrode of first NMOS pipe, the collecting electrode of triode is connected and is connected jointly ground with the drain electrode of first NMOS pipe, first resistance and third NMOS pipe are parallelly connected mutually, the fourth NMOS pipe, parallelly connected mutually with the second resistance after establishing ties between the fifth NMOS pipe. The utility model provides a technical scheme can further reduce battery protection integrated circuit's design cost to improve protection circuit's security and reliability.

Description

Lithium battery cathode protection circuit
Technical Field
The utility model relates to a semiconductor field especially relates to a lithium cell negative pole protection circuit.
Background
Currently, lithium ion batteries are very widely powered in portable applications. Since lithium ion batteries have a stability problem, a battery protection IC is generally used as a protection circuit of a battery system. In addition to providing protection against battery overcharge and overdischarge, charge and discharge current limits, etc., the battery protection IC also needs to be able to protect the lithium battery and the IC itself from damage during positive and negative connection of the battery to the charger.
The conventional structures for protecting the negative electrode of the lithium battery comprise a single power NMOS structure and a double power NMOS structure, and the conventional single power NMOS structure can be only used under low voltage. When the battery charger is plugged or touched between VDD and VM, instantaneous high voltage can occur to VM voltage, which may cause damage to an IC of a single power NMOS structure; the double-power NMOS can be applied to a scene that instantaneous high voltage occurs in the VM, but the cost of using the double-power NMOS is high, and the size area of a chip is large.
Therefore, it is an urgent objective to reduce the design cost of the battery protection integrated circuit and to improve the safety and reliability of the protection circuit.
SUMMERY OF THE UTILITY MODEL
In view of this, an object of the present invention is to provide a lithium battery negative protection circuit, which can reduce the design cost of a battery protection integrated circuit and improve the safety and reliability of the protection circuit.
The utility model provides a lithium battery negative pole protection circuit, this circuit include first NMOS pipe, second NMOS pipe, third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, triode, first resistance and second resistance, wherein, the second NMOS pipe the third NMOS pipe the fourth NMOS pipe between the fifth NMOS pipe series connection and after establishing ties with first NMOS pipe is parallelly connected each other, the source electrode connection power of first NMOS pipe, the drain electrode ground connection of first NMOS pipe, the projecting pole of triode with the source electrode connection of first NMOS pipe is connected and is connected jointly the power, the collecting electrode of triode with the drain electrode connection of first NMOS pipe and common ground connection, first resistance with third NMOS pipe is parallelly connected mutually, the fourth NMOS pipe after establishing ties between the fifth NMOS pipe with the second resistance is parallelly connected mutually.
Preferably, the substrate of the first NMOS transistor is connected to anodes of the first two diodes, and cathodes of the first two diodes are connected to the source of the first NMOS transistor and the drain of the first NMOS transistor, respectively.
Preferably, the source electrode of the second NMOS tube is connected to the power supply, the drain electrode of the second NMOS tube is connected to the source electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected to the source electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected to the source electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected to the drain electrode of the first NMOS tube and commonly grounded, the two ends of the first resistor are respectively connected to the source electrode and the drain electrode of the third NMOS tube, the two ends of the second resistor are respectively connected to the source electrode of the fourth NMOS tube and the drain electrode of the fifth NMOS tube, and the base electrode of the triode is connected to the source electrode of the third NMOS tube.
Preferably, the substrate of the second NMOS transistor is connected to anodes of two diodes of the second group, and cathodes of the two diodes of the second group are respectively connected to a source of the second NMOS transistor and a drain of the second NMOS transistor.
Preferably, the substrate of the third NMOS transistor is connected to anodes of two diodes of the third group, and cathodes of the two diodes of the third group are respectively connected to a source of the third NMOS transistor and a drain of the third NMOS transistor.
Preferably, the substrate of the fourth NMOS transistor is connected to anodes of two diodes in the fourth group, and cathodes of the two diodes in the fourth group are respectively connected to a source of the fourth NMOS transistor and a drain of the fourth NMOS transistor.
Preferably, the substrate of the fifth NMOS transistor is connected to anodes of the fifth two diodes, and cathodes of the fifth two diodes are respectively connected to the source of the fifth NMOS transistor and the drain of the fifth NMOS transistor.
Preferably, the first NMOS tube internal structure includes a deep N-well disposed at a bottom layer, a high-voltage P-well and two N-wells stacked on the deep N-well and spaced from each other, and a P-well far from the deep N-well, the high-voltage P-well is stacked at a middle position on the deep N-well, the two N-wells are respectively located at two sides of the high-voltage P-well and stacked at edge positions on the deep N-well, and the P-well is adjacent to one of the N-wells.
Preferably, the high-voltage P-well includes a P-type substrate and two doped regions located at two sides of the P-type substrate, the P-type substrate is used as a substrate of the first NMOS transistor, the two doped regions are used as a source of the first NMOS transistor, the two N-wells are used as a drain of the first NMOS transistor, the doped region of the N-well and the doped region of the high-voltage P-well are used as a gate of the first NMOS transistor, and the P-well far from the deep N-well is grounded.
Preferably, the internal structure of any one of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor includes a deep N-well disposed at the bottom layer, a P-well and two N-wells stacked on the deep N-well and abutting against each other, and a P-well far away from the deep N-well, the P-well stacked on the deep N-well is located at the middle position on the deep N-well, and the two N-wells are located at the edge positions on the deep N-well, respectively.
Preferably, the P-well stacked on the deep N-well includes two P-type substrates and two doped regions, the two P-type substrates are used as the substrate of the second NMOS transistor together, the two doped regions are used as the source and the drain of the second NMOS transistor respectively, a gate of the second NMOS transistor is disposed between the two doped regions, and the P-well far from the deep N-well is grounded.
The utility model provides a technical scheme has following advantage: by changing the structure of the single-power NMOS substrate selection circuit, the single-power NMOS can meet the application requirement of high voltage at the moment of plugging and unplugging the charger; meanwhile, the IC is protected in the application of positive connection and negative connection of the charger and the battery, the design cost of the battery protection integrated circuit can be reduced, and the safety and the reliability of the protection circuit are improved.
Drawings
Fig. 1 is a schematic structural diagram of a lithium battery negative electrode protection circuit according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of the internal structure of a first NMOS transistor and a second NMOS transistor according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a lithium battery negative electrode protection circuit according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The following will describe the lithium battery negative electrode protection circuit provided by the present invention in detail.
Fig. 1 is a schematic flow chart of a lithium battery negative protection circuit according to an embodiment of the present invention.
In this embodiment, the lithium battery negative electrode protection circuit, in particular, the lithium battery negative electrode protection circuit applied to a single power NMOS high-voltage lithium battery, can further reduce the design cost of the battery protection integrated circuit, and improve the safety and reliability of the protection circuit.
In this embodiment, the lithium battery negative protection circuit includes a first NMOS transistor MN and a second NMOS transistor MN0And a third NMOS transistor MN1And a fourth NMOS transistor MN2And a fifth NMOS transistor MN3The power transistor comprises a triode QN, a first resistor R1 and a second resistor R2, wherein the first NMOS transistor MN is a power NMOS transistor, the maximum drain-source voltage of the first NMOS transistor MN reaches dozens of volts, and the triode QN is a parasitic triode NPN of the first NMOS transistor.
In this embodiment, the second NMOS transistor MN0And a third NMOS transistor MN1And a fourth NMOS transistor MN2And a fifth NMOS transistor MN3Are connected in series and are connected in parallel with the first NMOS transistor MN after being connected in series, specifically, the second NMOS transistor MN0The source electrode of the NMOS transistor is connected with a power supply voltage VM, and a second NMOS transistor MN0Drain electrode of the transistor is connected with a third NMOS transistor MN1The source of (a) is provided,third NMOS transistor MN1Drain electrode of the transistor is connected with a fourth NMOS transistor MN2Source electrode of (1), fourth NMOS transistor MN2Is connected with the fifth NMOS tube MN3Source electrode of (1), fifth NMOS transistor MN3The drain electrode of the first NMOS transistor MN is connected with the drain electrode of the first NMOS transistor MN and is commonly grounded to GND, and two ends of the first resistor R1 are respectively connected with the third NMOS transistor MN1And two ends of the second resistor R2 are respectively connected with the fourth NMOS transistor MN2Source electrode and fifth NMOS transistor MN3The base of the triode QN and the third NMOS transistor MN1Are connected.
In this embodiment, the source of the first NMOS transistor MN is connected to the power supply voltage VM, the drain of the first NMOS transistor MN is grounded GND, the emitter of the transistor QN is connected to the source of the first NMOS transistor MN and commonly connected to the power supply voltage VM, the collector of the transistor QN is connected to the drain of the first NMOS transistor MN and commonly grounded GND, and the first resistor R1 and the third NMOS transistor MN are connected to the drain of the first NMOS transistor MN and commonly grounded GND1In parallel, specifically, one end of the first resistor R1 is connected to the third NMOS transistor MN1The other end of the first resistor R1 is connected with the third NMOS transistor MN1Drain electrode of (1), fourth NMOS transistor MN2And a fifth NMOS transistor MN3After being connected in series, the second resistor R2 is connected in parallel, specifically, one end of the second resistor R2 is connected with the fourth NMOS transistor MN2The other end of the second resistor R2 is connected with the fifth NMOS transistor MN3Of the substrate.
In this embodiment, the lithium battery negative electrode protection circuit further includes five groups of two diodes.
In this embodiment, the substrate BULK of the first NMOS transistor MN is connected to the anodes of the first two diodes, and the cathodes of the first two diodes are respectively connected to the source of the first NMOS transistor MN and the drain of the first NMOS transistor MN.
In this embodiment, the second NMOS transistor MN0The substrate BULK is connected with the anodes of the two diodes of the second group, and the cathodes of the two diodes of the second group are respectively connected with the second NMOS tube MN0Source electrode and second NMOS transistor MN0Of the substrate.
In this embodiment, the third NMOS transistor MN1Substrate BULK and the anodes of the two diodes of the third groupAre all connected, the cathodes of the two diodes of the third group are respectively connected with a third NMOS tube MN1Source electrode and third NMOS transistor MN1Of the substrate.
In this embodiment, the fourth NMOS transistor MN2The substrate BULK is connected with the positive electrodes of the fourth two diodes, and the negative electrodes of the fourth two diodes are respectively connected with the fourth NMOS tube MN2Source electrode and fourth NMOS transistor MN2Of the substrate.
In this embodiment, the fifth NMOS transistor MN3The substrate BULK is connected with the anodes of the two diodes of the fifth group, and the cathodes of the two diodes of the fifth group are respectively connected with the fifth NMOS tube MN3Source electrode and fifth NMOS transistor MN3Of the substrate.
Please refer to fig. 2, which is a cross-sectional view illustrating an internal structure of a first NMOS transistor and a second NMOS transistor according to an embodiment of the present invention.
In this embodiment, the left side of the figure shows a cross-sectional view of the internal structure of the first NMOS transistor MN, and the right side of the figure shows the second NMOS transistor MN0The third NMOS transistor MN1And a fourth NMOS transistor MN2And a fifth NMOS transistor MN3Has an internal structure similar to that of the second NMOS transistor MN0The internal structures of the three-phase MOS transistor are the same, in the figure, HVP represents a high-voltage P well, PW and NW respectively represent a P well and an N well, DN represents a deep N well, and the withstand voltage between DN and GND is high, so that the high-voltage requirement from GND to VM can be ensured, and the positive connection and reverse connection of a battery and a charger can be applied.
In this embodiment, the first NMOS transistor MN includes a deep N well DN disposed at the bottom layer, a high voltage P well HVP stacked on the deep N well DN and spaced from each other, two N wells NW, and a P well PW spaced apart from the deep N well DN, the high voltage P well HVP is stacked at a middle position on the deep N well DN, the two N wells NW are respectively located at two sides of the high voltage P well HVP and stacked at edge positions on the deep N well DN, the P well PW is adjacent to one of the N wells NW and spaced from each other, and the P well PW is grounded to GND.
In this embodiment, the high-voltage P-well HVP includes a P-type substrate (P +) and two doped regions (N +) located at two sides of the P-type substrate, the P-type substrate is used as a substrate B of the first NMOS transistor MN, the two doped regions (N +) are used as a source S of the first NMOS transistor MN, the two N-wells NW are used as a drain D of the first NMOS transistor MN, the doped regions of the N-well and the doped regions of the high-voltage P-well HVP are used as a gate G of the first NMOS transistor MN, and the P-well far from the deep N-well PW DN is grounded GND.
In this embodiment, the second NMOS transistor MN0And a third NMOS transistor MN1And a fourth NMOS transistor MN2And a fifth NMOS transistor MN3The inner structure of any NMOS tube comprises a deep N well DN arranged at the bottom layer, a P well PW, two N wells NW and a P well PW, wherein the P well PW, the two N wells NW and the P well PW are stacked on the deep N well DN and are close to each other, the P well PW is far away from the deep N well DN, the P well PW stacked on the deep N well DN is located in the middle position of the deep N well DN, and the two N wells NW are located at the edge positions of the deep N well DN respectively.
In this embodiment, the P-well PW stacked on the deep N-well DN includes two P-type substrates (P +) and two doped regions (N +), the two P-type substrates (P +) jointly serve as a substrate B of the second NMOS, the two doped regions (N +) respectively serve as a source S and a drain D of the second NMOS, a gate G of the second NMOS is disposed between the two doped regions (N +), the P-well far from the deep N-well is grounded GND, and the two N-wells NW are connected to the deep N-well DN.
In this embodiment, the operation principle of the single power NMOS high voltage lithium battery negative protection circuit of the present invention is described below with reference to fig. 1 and 2 when the power supply voltage VM protects the IC from the ground GND voltage range of-10V to + 5V:
1. the first NMOS transistor MN is started, the VM voltage is lower than GND, and at the moment, the second NMOS transistor MN is started0Open, MN1～MN3Disconnecting, selecting VM by BULK potential, and charging a lithium battery if the VM is disconnected;
2. the first NMOS transistor MN is started, the VM voltage is higher than GND, at the moment, the second NMOS transistor MN0 is disconnected, and MN is connected1～MN3Starting, selecting GND by BULK potential, and discharging the lithium battery;
3. the first NMOS transistor MN is disconnected, the VM voltage is lower than GND, if the substrate selection circuit still works normally, the second NMOS transistor MN0 is turned on at the moment, and MN is connected with the first NMOS transistor MN1～MN3Disconnecting, and selecting VM by BULK potential; if the substrate selection circuitry is not operational, MN0～MN3Cut off when a momentary negative high voltage (e.g., -10V) appears in VMThe GND to VM can discharge charges through the second resistor R2, the first resistor R1 and the transistor QN; at this time D0、D3Positive bias, D1、D2Reverse bias, D0V with voltage at two ends equal to QN of triodebeVoltage, due to the larger size of the first NMOS transistor MN, the BULK voltage will approach VM, D1And D2The reverse voltage across is represented by:
Figure BDA0002704599260000071
Figure BDA0002704599260000072
by R1And R2The partial pressure of VM can prevent the instantaneous high voltage breakdown D of VM1And D2(ii) a While the path current from GND to VM is from R1And R2This state does not damage the IC;
4. the first NMOS transistor MN is disconnected, the VM voltage is higher than GND, and if the substrate selection circuit still works normally, the second NMOS transistor MN0 is disconnected at the moment, and MN is connected1～MN3Starting, and selecting GND by BULK potential; if the substrate selection circuitry is not operational, MN0～MN3Disconnecting, when the VM has instantaneous positive voltage (such as +5V), the path from the VM to GND is D0、R1And R2Or QN, R1And R2Due to D0Reverse bias, no current in the path, resistance R1And R2Has a voltage drop of 0V and a BULK potential equal to GND, D0The voltage at two ends is equal to the voltage difference from VM to GND, and the state can be protected from damaging the IC;
by last, the utility model discloses a circuit can be fine protection lithium cell and IC itself under various application conditions, reduce the chip cost, simultaneously the utility model discloses a there is parasitic triode QN in power tube MN, has higher surge current protect function.
In addition, the utility model discloses still provide another single power NMOS's higher voltage lithium cell negative pole protection circuit, like fig. 3 to this withstand voltage demand that satisfies the VM end difference.
Power tubes MN and MN in FIG. 30～MNN+1The cross section of the NMOS transistor MN is shown in FIG. 2, and the withstand voltage of the power transistor MN is required to meet the negative pressure requirement of VM, if the maximum voltage of VM is-30V, the withstand voltage of each ground diode of MN is required to be more than 30V, and the second NMOS transistor MN is required to be connected with the ground diode of the power transistor MN0The diodes to ground also need to be above 30V.
The circuit of fig. 3, like the circuit principle of the previous protection circuit, can protect the battery when high voltage occurs at the moment of plugging and unplugging the charger, while preventing IC damage in various applications. The voltage range that the circuit of fig. 3 can satisfy VM is: -N × 5V to +5V, if N × 4, the variation range of VM can be-20V to +5V, and at the same time, 4 resistors are needed to divide the voltage of VM, so that a negative voltage appears at VM end, and MN are present0～MNN+1All are turned off, the resistance R is increased1～RNCan divide the voltage at VM end to prevent body diode D1～DNIs punctured by the VM.
Positive pressure (+5V) occurs at VM side, and MN0～MNN+1All closed, the path from VM to GND is D0、R1～RNOr QN, R1～RN. Due to D0Reverse bias, resistance R1～RNIs 0V and the BULK potential is equal to GND. This state also does not damage the IC.
In fig. 3, the parasitic triode QN exists in the power transistor MN, which can also absorb the surge current well, thereby playing a role in protecting the lithium battery and the IC itself.
The utility model provides a technical scheme has following advantage: by changing the structure of the single-power NMOS substrate selection circuit, the single-power NMOS can meet the application requirement of high voltage at the moment of plugging and unplugging the charger; meanwhile, the IC is protected in the application of positive connection and negative connection of the charger and the battery, the design cost of the battery protection integrated circuit can be reduced, and the safety and the reliability of the protection circuit are improved.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims (11)

1. The negative electrode protection circuit of the lithium battery is characterized by comprising a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a triode, a first resistor and a second resistor, wherein the second NMOS tube, the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected in series and then connected in parallel with the first NMOS tube, the source electrode of the first NMOS tube is connected with a power supply, the drain electrode of the first NMOS tube is grounded, the emitter electrode of the triode is connected with the source electrode of the first NMOS tube and connected with the power supply together, the collector electrode of the triode is connected with the drain electrode of the first NMOS tube and connected with the ground together, the first resistor is connected in parallel with the third NMOS tube, and the fourth NMOS tube and the fifth NMOS tube are connected in series and then connected with the second resistor in parallel.
2. The lithium battery cathode protection circuit as claimed in claim 1, wherein the substrate of the first NMOS transistor is connected to the anodes of the first two diodes, and the cathodes of the first two diodes are respectively connected to the source of the first NMOS transistor and the drain of the first NMOS transistor.
3. The lithium battery negative electrode protection circuit of claim 1, wherein a source electrode of the second NMOS transistor is connected to the power supply, a drain electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, a drain electrode of the third NMOS transistor is connected to a source electrode of the fourth NMOS transistor, a drain electrode of the fourth NMOS transistor is connected to a source electrode of the fifth NMOS transistor, a drain electrode of the fifth NMOS transistor is connected to a drain electrode of the first NMOS transistor and commonly grounded, two ends of the first resistor are respectively connected to a source electrode and a drain electrode of the third NMOS transistor, two ends of the second resistor are respectively connected to a source electrode of the fourth NMOS transistor and a drain electrode of the fifth NMOS transistor, and a base electrode of the triode is connected to a source electrode of the third NMOS transistor.
4. The lithium battery negative electrode protection circuit as claimed in claim 1, wherein the substrate of the second NMOS transistor is connected to the anodes of the second two diodes, and the cathodes of the second two diodes are respectively connected to the source of the second NMOS transistor and the drain of the second NMOS transistor.
5. The lithium battery negative electrode protection circuit of claim 1, wherein the substrate of the third NMOS transistor is connected to anodes of a third group of two diodes, and cathodes of the third group of two diodes are respectively connected to a source of the third NMOS transistor and a drain of the third NMOS transistor.
6. The lithium battery negative electrode protection circuit as claimed in claim 1, wherein the substrate of the fourth NMOS transistor is connected to anodes of a fourth set of two diodes, and cathodes of the fourth set of two diodes are respectively connected to a source of the fourth NMOS transistor and a drain of the fourth NMOS transistor.
7. The lithium battery negative electrode protection circuit according to claim 1, wherein the substrate of the fifth NMOS transistor is connected to anodes of two diodes of a fifth group, and cathodes of two diodes of the fifth group are respectively connected to a source of the fifth NMOS transistor and a drain of the fifth NMOS transistor.
8. The lithium battery negative protection circuit of claim 1, wherein the first NMOS transistor internal structure comprises a deep N-well disposed at the bottom layer, a high voltage P-well and two N-wells stacked on the deep N-well and spaced from each other, and a P-well far from the deep N-well, wherein the high voltage P-well is stacked at a middle position on the deep N-well, the two N-wells are respectively located at two sides of the high voltage P-well and are respectively stacked at an edge position on the deep N-well, and the P-well is adjacent to one of the N-wells.
9. The lithium battery negative electrode protection circuit of claim 8, wherein the high voltage P-well includes a P-type substrate and two doped regions located at two sides of the P-type substrate, the P-type substrate is used as a substrate of the first NMOS transistor, the two doped regions are used as a source of the first NMOS transistor, the two N-wells are used as a drain of the first NMOS transistor, the doped region of the N-well and the doped region of the high voltage P-well are used as a gate of the first NMOS transistor, and the P-well far from the deep N-well is grounded.
10. The lithium battery negative electrode protection circuit of claim 1, wherein the internal structure of any one of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor comprises a deep N-well disposed at the bottom layer, a P-well and two N-wells stacked on the deep N-well and abutting against each other, and a P-well far from the deep N-well, wherein the P-well stacked on the deep N-well is located at a middle position on the deep N-well, and the two N-wells are respectively located at edge positions on the deep N-well.
11. The lithium battery negative electrode protection circuit according to claim 10, wherein the P-well stacked on the deep N-well includes two P-type substrates and two doped regions, the two P-type substrates are used together as a substrate of the second NMOS transistor, the two doped regions are used as a source and a drain of the second NMOS transistor, respectively, a gate of the second NMOS transistor is disposed between the two doped regions, and the P-well far away from the deep N-well is grounded.
CN202022166686.5U 2020-09-27 2020-09-27 Lithium battery cathode protection circuit Active CN213602424U (en)

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