CN213583770U - Semiconductor discrete device packaging structure - Google Patents
Semiconductor discrete device packaging structure Download PDFInfo
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- CN213583770U CN213583770U CN202021610638.4U CN202021610638U CN213583770U CN 213583770 U CN213583770 U CN 213583770U CN 202021610638 U CN202021610638 U CN 202021610638U CN 213583770 U CN213583770 U CN 213583770U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
- H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model provides a discrete device packaging structure of semiconductor, include: the packaging structure comprises a packaging substrate, a chip placing region and a pin placing region are arranged on the upper surface of the packaging substrate; the semiconductor chip is correspondingly arranged in the chip placing area, and the upper surface of the semiconductor chip is provided with a bonding area; one end of the electrode pin is correspondingly arranged in the pin placing area; the bonding wire is connected with the semiconductor chip through the bonding area; and the plastic package shell wraps the periphery of the discrete device, and the lower surface of the package substrate is exposed. The utility model discloses can avoid using insulating piece and insulating grain to can effectively simplify production assembling process, in order to reach the purpose that reduces the technology degree of difficulty and material cost, in addition, can also effectively reduce thermal resistance and thermal stress, thereby can improve the thermal cycle ability, in order to reach the purpose of guaranteeing power cycle stability and increase of service life.
Description
Technical Field
The utility model relates to a discrete device technical field, concretely relates to discrete device packaging structure of semiconductor.
Background
At present, the packaging of the existing high-power discrete device generally adopts the following three insulation modes, namely a non-insulation structure, an outer insulation structure and an inner insulation structure, but the three insulation modes have obvious defects and shortcomings.
The first non-insulation structure is generally to expose the back of the copper frame to facilitate heat dissipation, but the installation of the heat dissipation substrate needs to ensure insulation, and the common method is to attach an insulation sheet and insulation particles to a radiator. However, the insulating sheet and the insulating particles in this manner may cause extra material, management and production costs, and especially, the insulating particles in this manner are prone to aging and deformation when the discrete semiconductor device is operated at high temperature, which may eventually lead to loosening of the discrete semiconductor device and the heat sink, decrease in heat dissipation effect, decrease in insulating performance, and in extreme cases, insulation failure may occur. In addition, the insulating particles in this manner are also easily damaged during production and assembly, such as cracking or deformation, and finally, the heat dissipation effect of the semiconductor discrete device is reduced, and the insulating performance is reduced.
The two external insulation structures are generally insulated by welding copper-clad ceramic sheets on the back surfaces of packaged non-insulation discrete devices. However, in this method, a back-side bonding process is added after the discrete device packaging process is completed, which increases the production cost and material cost.
In the three-internal insulation structure, a copper-clad ceramic wafer is generally welded on the back of a copper frame and is plastically packaged in an epoxy plastic packaging material along with the copper frame, and only the copper-clad on the back of the ceramic wafer is exposed for welding a radiator on the back of a discrete device. However, this method increases two welding processes and increases the production control cost. In addition, this approach also increases process difficulties and material costs.
SUMMERY OF THE UTILITY MODEL
The present invention aims at solving at least one of the technical problems in the above-mentioned technology to a certain extent. Therefore, the utility model aims to provide a discrete semiconductor device packaging structure can avoid using insulating piece and insulating grain to can effectively simplify production assembling process, in order to reach the purpose that reduces the technology degree of difficulty and material cost, in addition, can also effectively reduce thermal resistance and thermal stress, thereby can improve the thermal cycle ability, in order to reach the purpose of guaranteeing power cycle stability and increase of service life.
In order to achieve the above object, an embodiment of the present invention provides a semiconductor discrete device package structure, including: the packaging structure comprises a packaging substrate, a chip placing region and a pin placing region are arranged on the upper surface of the packaging substrate; the semiconductor chip is correspondingly arranged in the chip placing area, and the upper surface of the semiconductor chip is provided with a bonding area; one end of the electrode pin is correspondingly arranged in the pin placing area; the bonding wire is connected with the semiconductor chip through the bonding region; and the plastic package shell wraps the periphery of the discrete device, and the lower surface of the package substrate is exposed.
According to the semiconductor discrete device package structure provided by the embodiment of the utility model, by arranging the package substrate, the semiconductor chip, the electrode pins, the bonding wires and the plastic package shell, wherein, the upper surface of the packaging substrate is provided with a chip placing area and a pin placing area, the semiconductor chip is correspondingly arranged in the chip placing area, one end of the electrode pin is correspondingly arranged in the pin placing area, the bonding wire is connected with the semiconductor chip through the bonding area, the plastic packaging shell wraps the periphery of the discrete device, and the lower surface of the packaging substrate is exposed, thereby avoiding the use of insulating sheets and insulating particles, thereby effectively simplifying the production and assembly process, achieving the purpose of reducing the process difficulty and the material cost, and in addition, effectively reducing the thermal resistance and the thermal stress, therefore, the heat circulation capacity can be improved, and the purposes of ensuring the power circulation stability and prolonging the service life are achieved.
In addition, the semiconductor discrete device package structure provided by the above embodiments of the present invention may further have the following additional technical features:
according to the utility model discloses an embodiment, the encapsulation basement includes base plate layer, insulating layer and circuit layer, wherein, the base plate layer the insulating layer with the circuit layer stacks gradually the setting from bottom to top.
According to the utility model discloses an embodiment, the encapsulation base is the insulated metal base plate, the insulated metal base plate includes copper-based layer, insulating resin layer and copper coating, wherein, the copper-based layer the insulating resin layer with the copper coating stacks gradually the setting from bottom to top.
According to the utility model discloses an embodiment, the encapsulation basement includes base plate layer, insulating layer and circuit layer, wherein, the insulating layer the base plate layer with the circuit layer stacks gradually the setting from bottom to top.
According to the utility model discloses an embodiment, the encapsulation base is the insulating metal base plate, the insulating metal base plate includes aluminium basic unit, aluminium oxide layer and copper coating, wherein, the aluminium oxide layer aluminium basic unit with the copper coating stacks gradually the setting from bottom to top.
According to an embodiment of the present invention, the package substrate is an insulating metal substrate.
According to the utility model discloses an embodiment, the chip place the region with the region is placed to the pin all is equipped with the soldering tin layer, wherein, semiconductor chip place the regional soldering tin layer of intra-area through corresponding the chip with the encapsulation basement links to each other, the electrode pin place the regional intra-area soldering tin layer through corresponding the pin with the encapsulation basement links to each other.
According to an embodiment of the invention, the bonding wire is an aluminum wire.
According to the utility model discloses an embodiment, the plastic envelope shell is the casing that the epoxy plastic envelope material constitutes.
Drawings
Fig. 1 is a front view of a discrete semiconductor device package structure according to an embodiment of the present invention;
fig. 2 is a front view of a discrete semiconductor device package structure according to another embodiment of the present invention;
fig. 3 is an axial view of a discrete semiconductor device package structure according to an embodiment of the present invention;
fig. 4 is a schematic distribution diagram of a chip placement region and a pin placement region on an upper surface of a package substrate according to an embodiment of the present invention;
fig. 5 is a schematic view showing the distribution of solder layers according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Fig. 1 is a front view of a semiconductor discrete device package structure according to an embodiment of the present invention.
As shown in fig. 1, the semiconductor discrete device package structure according to the embodiment of the present invention includes a package substrate 10, a semiconductor chip 20, electrode pins 30, bonding wires 40, and a plastic package housing 50. Wherein, the upper surface of the package substrate 10 is provided with a chip placing region and a pin placing region; the semiconductor chip 20 is correspondingly arranged in the chip placing area; one end of the electrode pin 30 is correspondingly arranged in the pin placing area; the bonding wire 40 is connected to the semiconductor chip 20 through a bonding region; the plastic package housing 50 wraps the periphery of the discrete device, and the lower surface of the package substrate 10 is exposed.
In an embodiment of the present invention, as shown in fig. 1, the package substrate 10 may include a substrate layer 101, an insulating layer 102 and a circuit layer 103, wherein the substrate layer 101, the insulating layer 102 and the circuit layer 103 may be stacked from bottom to top in sequence, and the substrate layer 101 and the insulating layer 102 have the same shape and size, and the circuit layer 103 has the same shape and different size as the substrate layer 101 and the insulating layer 102.
In an embodiment of the present invention, as shown in fig. 1, the package substrate 10 may be an insulated metal substrate, the substrate layer 101 may be a copper base layer, the insulating layer 102 may be an insulating resin layer, and the circuit layer 103 may be a copper plating layer, wherein the insulating resin layer is the same as the shape and size of the overlooking plane of the copper base layer, and the insulating resin layer is stacked on the upper surface of the copper base layer, the copper plating layer is the same as the shape and size of the overlooking plane of the insulating resin layer and the copper base layer, and the copper plating layer is stacked on the upper surface of the insulating resin layer. Through setting up insulating metal substrate, can have better compressive property to can improve the quality of product.
In another embodiment of the present invention, as shown in fig. 2, the package substrate 10 may include a substrate layer 101, an insulating layer 102 and a circuit layer 103, wherein the insulating layer 102, the substrate layer 101 and the circuit layer 103 may be stacked in sequence from bottom to top, and the insulating layer 102, the substrate layer 101 and the circuit layer 103 have the same shape and size.
In another embodiment of the present invention, as shown in fig. 2, the package substrate 10 may be an insulating metal substrate, the substrate layer 101 may be an aluminum-based layer, the insulating layer 102 may be an aluminum oxide layer, and the circuit layer 103 may be a copper-plated layer, wherein the aluminum oxide layer, the aluminum-based layer and the copper-plated layer have the same shape and size in a plan view, and the upper surface of the aluminum-based layer may be plated to form a thick copper-plated layer, the lower surface thereof may be anodized to form a dense aluminum oxide film, i.e., an aluminum oxide layer, and the thickness of the aluminum oxide film, i.e., the aluminum oxide layer, may be 60 to 200 micrometers. The aluminum oxide film, namely the aluminum oxide layer, can play a good insulating effect, and in addition, the thick copper plating layer is electroplated on the upper surface of the aluminum base layer, so that the heat capacity of the device can be increased, the heat dissipation of the device can be improved, the power cycle of the device can be improved, and the service life of the device can be prolonged.
It should be noted that other structures corresponding to the package substrate 10 shown in fig. 1 and the package substrate 10 shown in fig. 2 are the same, and in order to avoid repeated descriptions, the package substrate 10 shown in fig. 1 is taken as an example to illustrate other structures in the semiconductor discrete device package structure of the present invention.
In an embodiment of the present invention, as shown in fig. 3, 4 and 5, the upper surface of the package substrate 10, i.e. the chip placing region and the pin placing region of the upper surface of the circuit layer 103, are all provided with solder layers, for example, the first chip placing region a, the second chip placing region b and the pin placing region c are respectively provided with a first solder layer 601, a second solder layer 602 and a third solder layer 603. Wherein the first semiconductor chip 201 can be connected to the circuit layer 103, e.g. a copper plating, via the first solder layer 601, i.e. can be soldered to the circuit layer 103, e.g. the first chip placement area a in the copper plating, via the first solder layer 601; the second semiconductor chip 202 may be connected to the circuit layer 103 via the second solder layer 602, e.g., a copper plating, i.e., may be soldered to the circuit layer 103 via the second solder layer 602, e.g., in the second chip placement area b in the copper plating; the second electrode pin 302 can be connected to the circuit layer 103 via a third solder layer 603, e.g., a copper plating, or can be soldered to the circuit layer 103 via the third solder layer 603, e.g., at a pin placement area c in the copper plating.
Further, as shown in fig. 3, the first electrode pin 301 may be suspended and connected to an emitter on the upper surface of the second semiconductor chip 202 through bonding wires 401, 402, 403, and 404, and the third electrode pin 303 may also be suspended and connected to a gate on the upper surface of the second semiconductor chip 202 through a bonding wire 405, where the bonding wires 401, 402, 403, and 404 may all be aluminum wires.
Furthermore, as shown in fig. 3, bonding connection between the first semiconductor chip 201 and the second semiconductor chip 202 may also be achieved through bonding wires 401, 402, 403, and 404.
It should be noted that the first semiconductor chip 201 and the second semiconductor chip 202 in the above embodiments may be an FWD chip and an IGBT chip, respectively, and in other embodiments of the present invention, the semiconductor chip in the semiconductor discrete device package structure may also be of other types, for example, the semiconductor chip may also be an MOS chip or a diode chip.
In an embodiment of the present invention, the plastic package housing 50 can be a housing made of epoxy plastic package material, and can be used to wrap the above structure, for example, as shown in fig. 1, the plastic package housing 50 can wrap the insulated metal substrate, the semiconductor chip 20, the bonding aluminum wire and the electrode pins 30, wherein the lower surface of the insulated metal substrate, i.e., the lower surface of the copper base layer, is exposed, and the other end of each electrode pin 30 also extends out of the plastic package housing 50 for external connection. The lower surface of the insulating metal substrate is exposed, so that the insulating metal substrate can be safely connected to the surface of the radiating fin, and the radiating fin and other devices are guaranteed not to be affected when sharing the radiator, so that the insulating problem of sharing one radiating fin is solved.
It should be further noted that the structure type adopted in the above embodiments is only a preferred example and is not limited to this structure type, for example, in other embodiments of the present invention, the substrate layer 101 may also be other types of substrate layers, such as an aluminum substrate layer; the bond wires 40 may also be other types of bond wires, such as copper wires; the plastic housing 50 may also be other types of housings, such as a housing made of silicone.
Can constitute based on above-mentioned structure the utility model discloses discrete semiconductor device packaging structure of embodiment will combine above-mentioned structure to explain below the utility model discloses discrete semiconductor device packaging structure's preparation flow is provided.
The utility model discloses discrete semiconductor device packaging structure's preparation flow specifically as follows: 1, welding a semiconductor chip, namely welding the semiconductor chip on a chip placement area corresponding to the upper surface of a packaging substrate by adopting soldering tin; 2, welding the electrode pins, namely welding the electrode pins on the corresponding electrode pin placement area on the upper surface of the packaging substrate by adopting soldering tin; 3, aluminum wire bonding, namely bonding the semiconductor chip and the electrode pin by adopting an aluminum wire; 4, plastic packaging, namely packaging the structure by using epoxy plastic packaging material, and exposing the lower surface of the packaging substrate; 5, testing; and 6, packaging.
According to the semiconductor discrete device package structure provided by the embodiment of the utility model, by arranging the package substrate, the semiconductor chip, the electrode pins, the bonding wires and the plastic package shell, wherein, the upper surface of the packaging substrate is provided with a chip placing area and a pin placing area, the semiconductor chip is correspondingly arranged in the chip placing area, one end of the electrode pin is correspondingly arranged in the pin placing area, the bonding wire is connected with the semiconductor chip through the bonding area, the plastic packaging shell wraps the periphery of the discrete device, and the lower surface of the packaging substrate is exposed, thereby avoiding the use of insulating sheets and insulating particles, thereby effectively simplifying the production and assembly process, achieving the purpose of reducing the process difficulty and the material cost, and in addition, effectively reducing the thermal resistance and the thermal stress, therefore, the heat circulation capacity can be improved, and the purposes of ensuring the power circulation stability and prolonging the service life are achieved.
In the present invention, unless otherwise expressly stated or limited, the term "connected" is to be understood in a broad sense, e.g. fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A semiconductor discrete device package structure, comprising:
the packaging structure comprises a packaging substrate, a chip placing region and a pin placing region are arranged on the upper surface of the packaging substrate;
the semiconductor chip is correspondingly arranged in the chip placing area, and the upper surface of the semiconductor chip is provided with a bonding area;
one end of the electrode pin is correspondingly arranged in the pin placing area;
the bonding wire is connected with the semiconductor chip through the bonding region;
and the plastic package shell wraps the periphery of the discrete device, and the lower surface of the package substrate is exposed.
2. The semiconductor discrete device package structure of claim 1, wherein the package substrate comprises a substrate layer, an insulating layer, and a circuit layer, wherein the substrate layer, the insulating layer, and the circuit layer are stacked in sequence from bottom to top.
3. The semiconductor discrete device package structure according to claim 2, wherein the package base is an insulated metal substrate including a copper-based layer, an insulating resin layer, and a copper plating layer, wherein the copper-based layer, the insulating resin layer, and the copper plating layer are sequentially stacked from bottom to top.
4. The semiconductor discrete device package structure of claim 1, wherein the package substrate comprises a substrate layer, an insulating layer, and a circuit layer, wherein the insulating layer, the substrate layer, and the circuit layer are stacked in sequence from bottom to top.
5. The semiconductor discrete device package structure according to claim 4, wherein the package substrate is an insulated metal substrate comprising an aluminum base layer, an aluminum oxide layer, and a copper plating layer, wherein the aluminum oxide layer, the aluminum base layer, and the copper plating layer are sequentially stacked from bottom to top.
6. The semiconductor discrete device package structure as claimed in claim 1, wherein a solder layer is disposed in each of the die attach area and the pin attach area, wherein the semiconductor die is connected to the package substrate through the solder layer in the corresponding die attach area, and the electrode pins are connected to the package substrate through the solder layer in the corresponding pin attach area.
7. The semiconductor discrete device package structure of claim 6, wherein the bonding wire is an aluminum wire.
8. The semiconductor discrete device package structure of claim 7, wherein the plastic package housing is a housing made of epoxy plastic.
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| CN202021610638.4U CN213583770U (en) | 2020-08-06 | 2020-08-06 | Semiconductor discrete device packaging structure |
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| CN202021610638.4U CN213583770U (en) | 2020-08-06 | 2020-08-06 | Semiconductor discrete device packaging structure |
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| CN213583770U true CN213583770U (en) | 2021-06-29 |
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