CN213518243U - PCIe fiber card - Google Patents
PCIe fiber card Download PDFInfo
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- CN213518243U CN213518243U CN202021667986.5U CN202021667986U CN213518243U CN 213518243 U CN213518243 U CN 213518243U CN 202021667986 U CN202021667986 U CN 202021667986U CN 213518243 U CN213518243 U CN 213518243U
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Abstract
The utility model provides a PCIe fiber card, which comprises 4 paths of fiber interfaces, 4 paths of reserved fiber interfaces, an FPGA, a board card and DDR 4; the 4 paths of optical fiber interfaces and the reserved 4 paths of optical fiber interfaces are fixed on the board card; the FPGA is connected with the golden finger and the 4 paths of optical fiber interfaces, and 4 paths of interface links are reserved; the effective data bandwidth between the board card and the FPGA is 8 GB/s; the number of the DDR4 is two, and the DDR4 is fixed on the board card and then is respectively connected with the 4-path optical fiber interface and the FPGA. The utility model discloses a 4 provide up to 40Gbps data flow interface, support integrated circuit board data flow extension, improve high-speed storage server's performance, support multiple agreement, the wide application in all kinds of optical fiber communication equipment and high-speed protocol conversion switch, improve equipment performance reduces the manufacturing cost of whole equipment, practices thrift the maintenance.
Description
Technical Field
The utility model relates to a server data access technical equipment field specifically is a PCIe fiber card.
Background
At present, De-emphasis (De-emphasis) technology is used in the generation 1 and the generation 2 of PCI-E, that is, a transmitting end (TX) of a signal increases the amplitude of a hopping bit (representing a high-frequency component in the signal) when transmitting the signal, so that the attenuation of the high-frequency component by a transmission line can be partially compensated, and a better eye diagram can be obtained. In the PCI-E1 generation-3.5 db de-emphasis was used, and in the PCI-E2 generation-3.5 db and-6 db de-emphasis was used. For 3 generations, because the signal rate is higher, a more complex de-emphasis technique needs to be adopted, so except that the amplitude of the hopping bit is increased to transmit than that of the non-hopping bit, the amplitude of the first 1 bit of the hopping bit is also increased to transmit, and the increased amplitude is generally called Preshoot.
The PCI-E3 generation can achieve 1 times higher data transmission rate than 5Gbps of the 2 generation with a transmission rate of 8 Gbps. In practical application, data is still encoded on the PCI-E3 bus, but the encoding of 128b/130b is adopted, the encoding efficiency is high, and therefore the loss of the bus effective bandwidth is much smaller than that of 8b/10b encoding.
However, the problem is far from complete, and even if the data rate is only 8Gbps, new problems need to be solved to realize reliable transmission on the original cheap PCB and connector. The biggest problem is signal loss, the FR4 board has great attenuation to high-frequency components of the signal, and the higher the signal speed, the more the high-frequency components are, so the attenuation is more
SUMMERY OF THE UTILITY MODEL
The utility model provides a PCIe fiber card mainly solves the slower technical problem of data transmission that meets in high-speed server's work, adopts 4 to provide up to 40Gbps data flow interface, supports integrated circuit board data flow extension to improve high-speed storage server's performance, supports multiple agreement, and the wide application is in all kinds of optical communication equipment and high-speed protocol conversion switch, improve equipment performance, reduces the manufacturing cost of whole equipment, practices thrift the maintenance.
The utility model provides a PCIe fiber card, which comprises an integrated circuit, a 4-channel QSFP28 fiber interface, an FPGA, a board card and a DDR 4; each interface connected with the integrated circuit on the 4-channel QSFP28 optical fiber interface fixed board card can support 40Gbps data flow at most; the FPGA is connected with a card golden finger and a 4-path QSFP28 optical fiber interface to realize SRIO, AURORA and gigabit network high-speed protocols, and the FPGA adopts an InteStratix 10FPGA and is used for AI acceleration; the effective data bandwidth between the board card and a CPU (memory) is 8 GB/s; the number of the DDR4 is two, and the DDR4 is fixed on a board card and then is respectively connected with a 4-path QSFP28 optical fiber interface and an FPGA.
Optionally, the 4-way QSFP28 optical fiber interface includes a 4-way QSFP28 optical fiber interface and a reserved 4-way QSFP28 optical fiber interface, and each interface connected with the integrated circuit on the 4-way QSFP28 optical fiber interface fixed board card can support a maximum data traffic of 40 Gbps; and 4 QSFP28 interfaces are reserved, and board card data stream (or cascade) expansion can be carried out for the high-speed protocol conversion switch.
Optionally, the FPGA is connected with the card golden finger and the 4-way QSFP28 optical fiber interface to implement SRIO, AURORA, and gigabit network high-speed protocols, and the FPGA adopts an Intel Stratix10 FPGA for AI acceleration.
Optionally, the card board includes a gold finger on the card board, the effective data bandwidth between the card board and the CPU (memory) is 8GB/s, and the gold finger is located at the edge of the card board.
Optionally, the number of the DDRs 4 is two, and the two DDRs 4 are fixed on the board card and then are respectively connected with the 4-way QSFP28 optical fiber interface and the FPGA.
Optionally, each QSFP28 supports 40Gbps data rate transmission (single Line rate of 10Gbps), error-free, PCI Express Gen3 x16 throughput of not less than 8 GB/s.
Optional, structural and electrical properties: the PCIe standard specification is met, and 2U server insertion is supported;
the board card can independently supply power to work.
Optionally, on-board 2 group 4GB 72bit wide DDR4 SODIMM;
1Gb Quad SPI Flash。
optionally, 4x28Gbps QSFP28 optical cages are used for data access;
optionally, 4x28Gbps QSFP28 optical cages are used for data concatenation or data output;
1 PCI Express Gen3 x16 endpoint finger, interfacing with the server.
The embodiment of the utility model provides a beneficial effect that technical scheme brought is, adopts 4 to provide up to 40Gbps data flow interface, supports integrated circuit board data flow extension, improves high-speed storage server's performance greatly, can also support multiple agreement simultaneously, can wide application in all kinds of optical fiber communication equipment and high-speed protocol conversion switch, has high suitability and flexibility, improve equipment performance, reduces the manufacturing cost of whole equipment, practices thrift the maintenance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description may be used for obtaining other drawings according to some embodiments of the present invention without creative efforts for those skilled in the art;
fig. 1 is a schematic diagram of a PCIe fiber card provided by the present invention.
Detailed Description
For the purpose of implementing the present invention, the technical solution is more clear, and the following description will be combined with the accompanying drawings in the embodiments of the present invention, to make clear the technical solution in the embodiments of the present invention, and to describe it completely, it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person having ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
At present, data coding still exists on the PCI-E3 generation bus in practical application that the PCI-E3 generation can realize the data transmission rate 1 times higher than the 5Gbps of the 2 generation by using the transmission rate of 8Gbps, but the coding efficiency is very high by adopting the coding of 128b/130b, so that the effective bandwidth of the bus lost is much smaller than that of 8b/10b coding.
In the prior art, the data rate is only 8Gbps, and new problems need to be solved for realizing reliable transmission on the original cheap PCB and the connector. The biggest problem is signal loss, and the FR4 board has great attenuation to high-frequency components of the signal, and the higher the signal speed, the more high-frequency components are, so the attenuation is more. After the signals with different rates are transmitted through the PCB of FR4 board material with 10 inches, we can see that the 8Gbps signals can not see the eye pattern basically at the receiving end, let alone effective data reception.
In view of this, the utility model discloses a 4 provide up to 40Gbps data flow interface, support integrated circuit board data flow extension, improve high-speed storage server's performance greatly, can also support multiple agreement simultaneously, can wide application in all kinds of optical fiber communication equipment and high-speed protocol conversion switch, have high suitability have with the flexibility, thereby solve among the prior art high-speed storage server's the work, the data transmission that meets is slower, switching problems such as high-speed protocol conversion and exchange, and how to accelerate and cascade the linear processing technique problem of flowing water to the AI.
As shown in fig. 1, an embodiment of the present invention provides a PCIe fiber card, which includes a 4-way QSFP28 fiber interface, an FPGA, an integrated circuit, a board card, and a DDR 4; each interface connected with the integrated circuit on the 4-channel QSFP28 optical fiber interface fixed board card can maximally support 40Gbps data flow; the FPGA is connected with a card golden finger and a 4-path QSFP28 optical fiber interface to realize SRIO, AURORA and gigabit network high-speed protocols, and the FPGA is connected with an integrated circuit by adopting an Intel Stratix10 FPGA and used for AI acceleration; the effective data bandwidth between the board card and the CPU (memory) is 8 GB/s; the number of the DDR4 is two, and the DDR4 is connected with a 4-channel QSFP28 optical fiber interface and an FPGA respectively after being fixed on a board card.
Specifically, the 4-path QSFP28 optical fiber interface comprises a 4-path QSFP28 optical fiber interface and a reserved 4-path QSFP28 optical fiber interface, and each interface on the 4-path QSFP28 optical fiber interface fixed board card can support 40Gbps data flow at most; and 4 QSFP28 interfaces are reserved, and board card data stream (or cascade) expansion can be carried out for the high-speed protocol conversion switch.
Specifically, the PCIe fiber card is of a standard size that can meet the PCIe3.0x16 specification of a 2U server.
Specifically, the FPGA is connected with a card golden finger and a 4-path QSFP28 optical fiber interface to realize SRIO and AURORA gigabit network high-speed cooperation.
Specifically, the FPGA is connected to the integrated circuit by an Intel stratx 10FPGA for AI acceleration.
Specifically, the card board comprises a golden finger on the card board, the effective data bandwidth between the card board and a CPU (memory) is 8GB/s, and the golden finger is located at the edge of the card board.
Specifically, the number of the DDR4 is two, the DDR4 is connected with the 4-channel QSFP28 optical fiber interface and the FPGA respectively after being fixed on the board card, and the server data storage is carried out by adopting an inserted storage card.
Specifically, each QSFP28 supports 40Gbps data rate transmission (single Line rate is 10Gbps) without bit errors;
pCI Express Gen3 x16 throughput is not less than 8 GB/s.
Specifically, the structural and electrical characteristics: the PCIe standard specification is met, and 2U server insertion is supported;
the board card can independently supply power to work.
Specifically, on-board 2 group 4GB 72bit wide DDR4 SODIMM;
1Gb Quad SPI Flash。
specifically, 4x28Gbps QSFP28 optical cages are used for data access;
4x28Gbps QSFP28 optical cages are used for data cascade or data output;
1 PCI Express Gen3 x16 endpoint finger, interfacing with the server.
The above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; these modifications and substitutions do not make the essence of the corresponding technical solution depart from the scope of the technical solution of the embodiments of the present invention, and the above mentioned is only the preferred embodiments of the present invention, and the present invention is not limited to the embodiments of the present invention.
Claims (5)
1. A PCIe fiber card is characterized by comprising an integrated circuit, 4 paths of fiber interfaces, a reserved 4 paths of fiber interfaces, an FPGA and a DDR4, wherein the integrated circuit, the 4 paths of fiber interfaces, the reserved 4 paths of fiber interfaces and the DDR4 are arranged on a board card; the 4-path optical fiber interface and the reserved 4-path optical fiber interface are fixed on the board card and connected with an integrated circuit; the FPGA is connected with the golden finger, the 4 paths of optical fiber interfaces and the reserved 4 paths of interfaces; the number of the DDR4 is two, and the DDR4 is fixed on the board card and then is respectively connected with the 4-path optical fiber interface and the FPGA.
2. The fiber optic card of claim 1, wherein the FPGA is wired to the integrated circuit using Intel stratx 10.
3. The fiber optic card of claim 1, wherein the size of the card is the pcie.ox16 specification for 2u servers.
4. The fiber optic card of claim 1, wherein the gold finger is connected to the FPGA using 16 terminals.
5. The fiber optic card of claim 1, wherein the fiber optic interface employs a QSFP28 optical module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021667986.5U CN213518243U (en) | 2020-08-12 | 2020-08-12 | PCIe fiber card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021667986.5U CN213518243U (en) | 2020-08-12 | 2020-08-12 | PCIe fiber card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213518243U true CN213518243U (en) | 2021-06-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021667986.5U Expired - Fee Related CN213518243U (en) | 2020-08-12 | 2020-08-12 | PCIe fiber card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213518243U (en) |
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2020
- 2020-08-12 CN CN202021667986.5U patent/CN213518243U/en not_active Expired - Fee Related
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Granted publication date: 20210622 |