CN213243976U - Communication signal level conversion circuit - Google Patents
Communication signal level conversion circuit Download PDFInfo
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- CN213243976U CN213243976U CN202021725114.XU CN202021725114U CN213243976U CN 213243976 U CN213243976 U CN 213243976U CN 202021725114 U CN202021725114 U CN 202021725114U CN 213243976 U CN213243976 U CN 213243976U
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Abstract
The utility model discloses a communication signal level conversion circuit, its technical scheme is: the system comprises a communication interface S1 and an integrated circuit interface S2, wherein a communication power supply VCC S1 is connected between the communication interface S1 and the integrated circuit interface S2 in parallel, and a conversion circuit is connected between the communication interface S1 and the integrated circuit interface S2 in series; conversion circuit includes first MOS pipe and MOS array, the MOS array is being connected to first MOS pipe output, integrated circuit interface S2 is being connected to the MOS array output, integrated circuit power VCC S2 is being connected between MOS array and the integrated circuit interface S2, the beneficial effects of the utility model are that: through setting up MOS pipe and MOS array, can steadily orderly realize the conversion with the communication signal level, through with the parallel MOS array that becomes of second MOS pipe, make its signal conversion efficiency more stable, conversion efficiency is higher.
Description
Technical Field
The utility model relates to a level shift circuit field, concretely relates to communication signal level shift circuit.
Background
The microprocessor is widely applied to the control circuit, the power supply voltage is different (3.3V or 5V) according to different manufacturers, the power supply voltage of the communication integrated circuit is generally 5V, and the situation that the power supply voltage of the microprocessor is inconsistent with the power supply voltage of the communication integrated circuit can be met. Whether the level signals match in the circuit is directly related to the stability of the microprocessor and the reliability of the communication signals.
The prior art has the following defects: the existing communication signal level conversion circuit is not stable enough in voltage conversion, the overall sensitivity of the circuit is not high, and sometimes the voltage which is actually required cannot be reached, so that the use is not smooth.
Therefore, it is necessary to invent a communication signal level conversion circuit.
SUMMERY OF THE UTILITY MODEL
Therefore, the utility model provides a communication signal level conversion circuit, through setting up MOS pipe and MOS array, can be steady orderly realize the conversion with the communication signal level, through with MOS pipe parallel connection MOS array, make its signal conversion efficiency more stable, conversion efficiency is higher to solve the problem in the background art.
In order to achieve the above object, the present invention provides the following technical solutions: a communication signal level conversion circuit comprises a communication interface S1 and an integrated circuit interface S2, a communication power supply VCC S1 is connected between the communication interface S1 and the integrated circuit interface S2 in parallel, and a conversion circuit is connected between the communication interface S1 and the integrated circuit interface S2 in series;
the conversion circuit comprises a first MOS tube and an MOS array, wherein the output end of the first MOS tube is connected with the MOS array, the output end of the MOS array is connected with an integrated circuit interface S2, and an integrated circuit power VCC S2 is connected between the MOS array and the integrated circuit interface S2.
Preferably, one end of the output end of the communication power source VCC S1 is connected to the G pole of the first MOS transistor, and the other end is connected to the output line of the communication interface S1.
Preferably, the communication interface S1 is connected to the S pole of the first MOS transistor.
Preferably, a resistor R1 is disposed between the communication power source VCC S1 and the first MOS transistor.
Preferably, a resistor R2 is disposed between the communication interface S1 and the first MOS transistor.
Preferably, the MOS array comprises a plurality of second MOS transistors.
Preferably, a resistor R3 is disposed between the integrated circuit interface S2 line and the integrated circuit power source VCC S2.
The utility model has the advantages that:
the utility model discloses a set up first MOS pipe and MOS array, can be steady orderly realize the conversion with the communication signal level, the conduction reduction of first MOS pipe (field effect transistor), on-resistance is little, and the grid drive does not need the electric current, and the loss is little, and drive circuit is simple, from taking the protection diode, and the thermal resistance characteristic is good, is fit for high-power parallelly connected, through parallelly connected the MOS array with the second MOS pipe, makes its signal conversion efficiency more stable, and conversion efficiency is higher.
Drawings
Fig. 1 is a schematic circuit diagram provided by the present invention;
in the figure: the device comprises a first MOS tube 1, a conversion circuit 2, a MOS array 3 and a second MOS tube 3-1.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are presented herein only to illustrate and explain the present invention, and not to limit the present invention.
the conversion circuit 2 comprises a first MOS tube 1 and an MOS array 3, wherein the output end of the first MOS tube 1 is connected with the MOS array 3, the output end of the MOS array 3 is connected with an integrated circuit interface S2, and an integrated circuit power supply VCC S2 is connected between the MOS array 3 and the integrated circuit interface S2;
furthermore, one end of the output end of the communication power supply VCC S1 is connected to the G pole of the first MOS transistor 1, and the other end is connected to the output line of the communication interface S1;
further, the communication interface S1 is connected to the S pole of the first MOS transistor 1;
further, a resistor R1 is arranged between the communication power supply VCC S1 and the first MOS transistor 1;
further, a resistor R2 is arranged between the communication interface S1 and the first MOS transistor 1;
further, the MOS array 3 includes a plurality of second MOS transistors 3-1.
Further, a resistor R3 is arranged between the integrated circuit interface S2 line and the integrated circuit power supply VCC S2.
The utility model discloses a use as follows:
when the communication power VCC S1 is 0V, the first MOS transistor 1 is turned on, and the MOS array 3 is also turned on, so that when the communication power VCC S1 is 0V, the level of the integrated circuit power VCC S2 is lowered to 0V;
when the communication power VCC S1 is 3.3V, the first MOS transistor 1 is in a closed state, and the MOS array 3 is also in a closed state, so that the level of the integrated circuit power VCC S2 is pulled up to 5V;
when the integrated circuit power supply VCC S2 is 0V, since the diode inside the first MOS transistor 1 pulls the communication power supply VCC S1 low, and Vgs is greater than the threshold voltage of the first MOS transistor 1, so that the first MOS transistor 1 is turned on, once turned on, the communication power supply VCC S1 will be at the same level as the integrated circuit power supply VCC S2, i.e., at low level, so the communication power supply VCC S1 is 0V;
when the integrated circuit power source VCC S2 is 5V, and the first MOS transistor 1 is in a closed state, the communication power source VCC S1 will be pulled up to 3.3V.
The above description is only a preferred embodiment of the present invention, and any person skilled in the art may modify the present invention or modify it into an equivalent technical solution by using the technical solutions described above. Therefore, any simple modifications or equivalent replacements made according to the technical solution of the present invention belong to the scope of the claimed invention as far as possible.
Claims (7)
1. A communication signal level conversion circuit comprising a communication interface S1 and an integrated circuit interface S2, characterized in that: a communication power supply VCC S1 is connected in parallel between the communication interface S1 and the integrated circuit interface S2, and a conversion circuit (2) is connected in series between the communication interface S1 and the integrated circuit interface S2;
the conversion circuit (2) comprises a first MOS tube (1) and an MOS array (3), the output end of the first MOS tube (1) is connected with the MOS array (3), the output end of the MOS array (3) is connected with an integrated circuit interface S2, and an integrated circuit power VCC S2 is connected between the MOS array (3) and the integrated circuit interface S2.
2. A communication signal level conversion circuit according to claim 1, wherein: one end of the output end of the communication power supply VCC S1 is connected to the G pole of the first MOS tube (1), and the other end is connected to the output line of the communication interface S1.
3. A communication signal level conversion circuit according to claim 1, wherein: the communication interface S1 is connected to the S pole of the first MOS transistor.
4. A communication signal level conversion circuit according to claim 1, wherein: a resistor R1 is arranged between the communication power supply VCC S1 and the first MOS tube (1).
5. A communication signal level conversion circuit according to claim 1, wherein: a resistor R2 is arranged between the communication interface S1 and the first MOS tube (1).
6. A communication signal level conversion circuit according to claim 1, wherein: the MOS array (3) comprises a plurality of second MOS tubes (3-1).
7. A communication signal level conversion circuit according to claim 1, wherein: a resistor R3 is arranged between the integrated circuit interface S2 line and the integrated circuit power supply VCC S2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021725114.XU CN213243976U (en) | 2020-08-18 | 2020-08-18 | Communication signal level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021725114.XU CN213243976U (en) | 2020-08-18 | 2020-08-18 | Communication signal level conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213243976U true CN213243976U (en) | 2021-05-18 |
Family
ID=75895694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021725114.XU Active CN213243976U (en) | 2020-08-18 | 2020-08-18 | Communication signal level conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213243976U (en) |
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2020
- 2020-08-18 CN CN202021725114.XU patent/CN213243976U/en active Active
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