CN213242543U - Lead frame packaging structure for increasing chip area - Google Patents
Lead frame packaging structure for increasing chip area Download PDFInfo
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- CN213242543U CN213242543U CN202020956232.5U CN202020956232U CN213242543U CN 213242543 U CN213242543 U CN 213242543U CN 202020956232 U CN202020956232 U CN 202020956232U CN 213242543 U CN213242543 U CN 213242543U
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- conductive
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- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses an increase chip area's lead frame packaging structure belongs to semiconductor package technical field, lead frame packaging structure includes the plastic-sealed body and embeds first type in the plastic-sealed body leads electrical pillar and second type and leads electrical pillar, the surface invagination at the plastic-sealed body is provided with two first base plates and the second base plates that are not contact each other, the one end that first type leads electrical pillar is connected to first base plate, the one end that second type leads electrical pillar is connected to the second base plate, first type leads electrical pillar other end and connects and be equipped with the chip, the other end that second type led electrical pillar is connected and is equipped with the current conducting plate, the front and the first type of electrical pillar of chip are connected, the back and the current conducting plate of chip are connected, the current conducting plate leads electrical pillar through second type and is connected with the second base plate, the slope setting of second. The utility model discloses can be in limited encapsulation volume, the area of chip does not receive the restriction of base plate size, has increased chip area and has improved the performance and the heat-sinking capability of product.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to an increase chip area's lead frame packaging structure.
Background
The semiconductor is a material with electric conductivity between the conductor and the insulator at normal temperature, and has wide application in radio, television and temperature measurement, for example, the diode is a device made of semiconductor. Semiconductors are of great importance, both from a technological and economic point of view.
In the semiconductor manufacturing process, a semiconductor is usually integrated on a lead frame, and the lead frame is used as a chip carrier of an integrated circuit to form an electrical circuit, which serves as a bridge connected to an external wire.
When facing a chip package structure with a DFN0603 chip package form, a conventional package form is as shown in fig. 1, and includes a first substrate 1, a second substrate 2, a chip 3, a plastic package body 7 and a bonding wire 8, where the chip 3 is a chip 3 with a vertical structure, a back surface of the chip 3 is connected with the first substrate 1 by a conductive adhesive or eutectic die bonding, and a front surface of the chip 3 is connected with the second substrate 2 by the bonding wire 8. The conventional packaging method has the disadvantages that the size of the chip 3 is influenced by the area of the first substrate 1, and the area of the chip 3 cannot be large, so that the performance of the chip is influenced.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned not enough of present DFN0603 lead frame packaging structure existence, the utility model provides an increase chip area's lead frame packaging structure, this packaging structure makes the chip not receive the restriction of the base plate size of traditional encapsulation, and furthest's increase chip's area can improve the property ability of the same type encapsulation, and this encapsulation is through leading electrical pillar and current conducting plate combination heat dissipation, and the radiating effect is better, the effectual reliability that has improved the encapsulation.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a lead frame packaging structure for increasing the chip area comprises a plastic package body and a plurality of conductive columns which are not in contact with each other and are embedded in the plastic package body, wherein the conductive columns comprise a first type of conductive column and a second type of conductive column, two first substrates and two second substrates which are not in contact with each other are arranged on one surface of the plastic package body in an invagination manner, the first substrates are connected with one ends of the first type of conductive columns, the second substrates are connected with one ends of the second type of conductive columns, the other ends of the first type of conductive columns are connected with a chip, the other ends of the second type of conductive columns are connected with a conductive plate, the front surface of the chip is connected with the first type of conductive columns, the back surface of the chip is connected with the conductive plate, the conductive plate is connected with the second substrate through the second type of conductive columns, and the number of the first type of conductive columns, the second type of conductive column is obliquely arranged between the conductive plate and the second substrate.
According to an aspect of the invention, the area of the conductive plate is larger than the area of the chip.
According to an aspect of the present invention, the conductive plate, the chip, the first conductive column and the second conductive column are located inside the plastic package body.
According to an aspect of the present invention, the one end of the second conductive column connecting the conductive plate is inclined outward.
In accordance with an aspect of the present invention, the conductive plate is a copper plate.
According to an aspect of the present invention, the conductive post is a copper post.
According to one aspect of the present invention, the plastic package body is made of an insulating material.
The utility model discloses the advantage of implementing: the lead frame packaging structure for increasing the chip area comprises a plastic packaging body and a plurality of conductive columns which are not in contact with each other and are embedded in the plastic packaging body, wherein the conductive columns comprise a first type conductive column and a second type conductive column, a first substrate and a second substrate which are not in contact with each other are arranged on one surface of the plastic package body in a sunken way, the first substrate is connected with one end of the first conductive column, the second substrate is connected with one end of the second conductive column, the other end of the first type of conductive column is connected with a chip, the other end of the second type of conductive column is connected with a conductive plate, the front surface of the chip is connected with the first conductive columns, the back surface of the chip is connected with the conductive plate, the conducting plate is connected with the second substrate through the second type of conducting columns, the quantity of the first type of conducting columns is larger than or equal to 1, and the second type of conducting columns are obliquely arranged between the conducting plate and the second substrate. The utility model provides an increase chip area's lead frame packaging structure can make the chip not receive the restriction of the base plate size of traditional encapsulation, furthest's increase chip's area, and the area increase of chip makes TVS's IPP performance improve, and this packaging structure has improved the property ability of the same type encapsulation, and this encapsulation is through leading electrical pillar and current conducting plate combination heat dissipation, and the radiating effect is better, the effectual reliability that improves the encapsulation.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional DFN0603 lead frame package structure;
fig. 2 is a schematic structural diagram of a lead frame package structure for increasing chip area according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
As shown in fig. 2, the lead frame package structure for increasing the chip area includes a plastic package body 7 and a plurality of conductive pillars that are not in contact with each other and are embedded in the plastic package body, the conductive pillars include a first type conductive pillar 4 and a second type conductive pillar 6, two first substrates 1 and two second substrates 2 that are not in contact with each other are recessed in one surface of the plastic package body 7, the first substrate 1 is connected to one end of the first type conductive pillar 4, the second substrate 2 is connected to one end of the second type conductive pillar 6, the other end of the first type conductive pillar 4 is connected to a chip 3, the other end of the second type conductive pillar 6 is connected to a conductive plate 5, the front surface of the chip 3 is connected to the first type conductive pillar 4, the back surface of the chip 3 is connected to the conductive plate 5, the conductive plate 5 is connected to the second substrate 2 through the second type conductive pillar 6, the number of the first type conductive posts 4 is greater than or equal to 1, and the second type conductive posts 6 are obliquely arranged between the conductive plate 5 and the second substrate 2. Through above-mentioned technical scheme, can make the chip not receive the restriction of the base plate size of traditional encapsulation, furthest's increase chip's area, the area increase of chip makes TVS's IPP performance improve, this packaging structure has improved the product property ability of the encapsulation of the same type, this encapsulation is through leading electrical pillar and current conducting plate combination heat dissipation, and the radiating effect is better, the effectual reliability that improves the encapsulation.
Wherein the area of the conductive plate 5 is larger than the area of the chip 3.
The conductive plate 5, the chip 3, the first conductive column 4 and the second conductive column 6 are all located inside the plastic package body 7.
Wherein, the second type conductive column 6 is connected with one end of the conductive plate 5 and inclines outwards.
Wherein the conductive plate 5 is a copper sheet.
Wherein, the conductive pillar is a copper pillar.
Wherein, the plastic package body 7 is made of an insulating material.
The front surface of the chip 3 is connected with the first substrate 1 through the first type of conductive column 4, the back surface of the chip is connected with the conductive plate 5, and the conductive plate 5 is connected with the second substrate 2 through the second type of conductive column 6. The number of the first conductive pillars 4 can be one, two or more, and can be flexibly adjusted according to the first substrate of the chip 3. Because the area of the second substrate 2 is also fixed and limited, the second conductive pillars 6 are obliquely arranged between the conductive plate 5 and the second substrate 2, and one end of the second conductive pillars 6 connected with the conductive plate 5 is outwardly inclined, so that the area of the conductive plate 5 can be reserved to the maximum extent for placing the chip 3, and the area of the core 3 is increased to the maximum extent. The area of the chip 3 is increased, and the maximum reverse pulse peak current (IPP) performance of the transient diode (TVS) manufactured by the packaging method is improved along with the increase of the area of the chip.
The utility model discloses the advantage of implementing: the lead frame packaging structure for increasing the chip area comprises a plastic package body 7 and a plurality of conductive columns which are not in contact with each other and are embedded in the plastic package body, wherein the conductive columns comprise a first type conductive column 4 and a second type conductive column 6, two first base plates 1 and two second base plates 2 which are not in contact with each other are arranged in an inwards sunken mode on one surface of the plastic package body 7, the first base plates 1 are connected with one ends of the first type conductive columns 4, the second base plates 2 are connected with one ends of the second type conductive columns 6, the other ends of the first type conductive columns 4 are connected with a chip 3, the other ends of the second type conductive columns 6 are connected with a conductive plate 5, the front surface of the chip 3 is connected with the first type conductive columns 4, the back surface of the chip 3 is connected with the conductive plate 5, the conductive plate 5 is connected with the second base plates 2 through the second type conductive columns 6, the number of the first, the second conductive column 6 is obliquely arranged between the conductive plate 5 and the second substrate 2. The utility model provides an increase chip area's lead frame packaging structure, this packaging structure make chip 3 not receive the restriction of the base plate size of traditional encapsulation, furthest's increase chip 3's area can improve the product property ability of the same type encapsulation, and this encapsulation is through leading electrical pillar and 5 combination heat dissipations of current conducting plate, and the radiating effect is better, the effectual reliability that improves the encapsulation.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are all covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. The lead frame packaging structure for increasing the chip area is characterized by comprising a plastic packaging body and a plurality of conductive columns which are not in contact with each other and are embedded in the plastic packaging body, wherein the conductive columns comprise a first conductive column and a second conductive column, two first base plates and two second base plates which are not in contact with each other are arranged on one surface of the plastic packaging body in an invagination mode, the first base plates are connected with one ends of the first conductive columns, the second base plates are connected with one ends of the second conductive columns, the other ends of the first conductive columns are connected with a chip, the other ends of the second conductive columns are connected with a conductive plate, the front surface of the chip is connected with the first conductive columns, the back surface of the chip is connected with the conductive plate, the conductive plate is connected with the second base plate through the second conductive columns, the number of the first conductive columns is more than or equal to 1, the second type of conductive column is obliquely arranged between the conductive plate and the second substrate.
2. The lead frame package structure of claim 1, wherein the conductive plate has an area larger than an area of the chip.
3. The lead frame package structure with an increased chip area according to claim 2, wherein the conductive plate, the chip, the first conductive pillars and the second conductive pillars are located inside the plastic package body.
4. The lead frame package structure with increased chip area according to claim 3, wherein one end of the second conductive pillar connecting the conductive plate is inclined outward.
5. The lead frame package structure with increased chip area according to claim 3, wherein the conductive plate is a copper sheet.
6. The lead frame package structure with an increased chip area according to claim 3, wherein the conductive pillars are copper pillars.
7. The lead frame package structure with an increased chip area according to claim 3, wherein the molding compound is made of an insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020956232.5U CN213242543U (en) | 2020-05-31 | 2020-05-31 | Lead frame packaging structure for increasing chip area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020956232.5U CN213242543U (en) | 2020-05-31 | 2020-05-31 | Lead frame packaging structure for increasing chip area |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213242543U true CN213242543U (en) | 2021-05-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020956232.5U Active CN213242543U (en) | 2020-05-31 | 2020-05-31 | Lead frame packaging structure for increasing chip area |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213242543U (en) |
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2020
- 2020-05-31 CN CN202020956232.5U patent/CN213242543U/en active Active
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