CN213183603U

CN213183603U - Semiconductor memory

Info

Publication number: CN213183603U
Application number: CN202022019711.7U
Authority: CN
Inventors: 冀康灵; 李红文
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2021-05-11
Anticipated expiration: 2030-09-14

Abstract

The embodiment of the application relates to a semiconductor memory, comprising: a plurality of storage arrays; the system comprises at least one checking module, a plurality of storage arrays and a plurality of data buses, wherein each checking module corresponds to the plurality of storage arrays and is used for checking whether data information of the corresponding storage arrays is wrong or not; and the gating circuits are respectively connected with the storage array and the global data bus and are used for controlling the connection and disconnection of a data transmission path between the connected global data bus and the storage array. The verification module of the embodiment of the application only needs to verify the data information of the verification module which is read in real time, so that the semiconductor memory of the embodiment of the application can ensure that the data information is effectively verified every time when the verification module with a small number is adopted, and the semiconductor memory with a small space occupied by the verification module is provided.

Description

Semiconductor memory

Technical Field

The embodiment of the application relates to the technical field of memory devices, in particular to a semiconductor memory.

Background

A semiconductor Memory is a Memory accessed by using a semiconductor circuit, and among them, a Dynamic Random Access Memory (DRAM) is widely used in various fields with its fast Memory speed and high integration.

In order to obtain higher data read/write reliability, it is necessary to provide a verification module in the semiconductor memory so as to verify whether the read data is accurate. Currently, the verification module needs to occupy a large amount of space in the semiconductor memory, so that the volume of the memory cannot be further reduced.

SUMMERY OF THE UTILITY MODEL

In view of this, it is necessary to provide a semiconductor memory in order to solve the problem of the conventional memory that the space occupied by the check module is large.

A semiconductor memory, comprising:

a plurality of storage arrays;

the system comprises at least one checking module, a plurality of storage arrays and a plurality of data buses, wherein each checking module corresponds to the plurality of storage arrays and is used for checking whether data information of the corresponding storage arrays has errors or not;

the gating circuits are respectively connected with the storage array and the global data bus and are used for controlling the connection and disconnection of a data transmission path between the connected global data bus and the storage array.

In one embodiment, the semiconductor memory includes two memory arrays and one check module, the memory arrays correspond to the gating circuits in a one-to-one manner, and the memory arrays are connected to the check module through the corresponding gating circuits and the global data bus.

In one embodiment, the semiconductor memory includes three memory arrays and one check module, the memory arrays correspond to the gating circuits in a one-to-one manner, and the memory arrays are connected to the check module through the corresponding gating circuits and the global data bus.

In one embodiment, the semiconductor memory includes three storage arrays and two verification modules, the three storage arrays include a first array, a second array and a third array, the second array is connected with two second gating circuits, and the second gating circuits are connected with the global data bus in a one-to-one correspondence manner.

In one embodiment, the second array includes a first bit line connected to one of the two second gates and a second bit line connected to the other of the two second gates.

In one embodiment, two first gating circuits are connected to the first array, and the first gating circuits are connected with the global data buses in a one-to-one correspondence manner;

the third array is connected with two third gating circuits, and the third gating circuits are connected with the global data bus in a one-to-one correspondence manner;

the first gating circuit, the second gating circuit and the first gating circuit which are connected to the same global data bus are conducted in a time sharing mode.

In one embodiment, the verification module comprises:

the encoding unit is connected with the storage array and used for receiving input data information, encoding the data information to generate write-in check information and sending the data information and the write-in check information to the storage array;

and the error detection unit is connected with the storage array and used for synchronously reading the data information and the write-in verification information from the storage array and verifying whether the read data information has errors or not according to the write-in verification information.

In one embodiment, the error detection unit is further connected to the encoding unit, and the encoding unit is further configured to encode the read data information to generate read check information and send the read check information to the error detection unit;

the error detection unit is configured to obtain the write verification information and the read verification information, and compare the write verification information and the read verification information to determine whether an error occurs in the read data information.

In one embodiment, the check module further includes an error correction unit connected to the error detection unit, and configured to receive the read data information and comparison result information of the error detection unit, and update the data information according to the comparison result information.

In one embodiment, the semiconductor memory further comprises a strobe control module for generating a plurality of strobe signals;

the gating circuit comprises a switching tube, a control end of the switching tube is connected with the gating control module, a first end of the switching tube is connected with the global data bus, a second end of the switching tube is connected with the storage array, and the switching tube is used for selectively switching on or off a data transmission path between the first end and the second end under the control of the gating signal.

In one embodiment, the switch tube is a high-voltage switch tube.

In one embodiment, the switch tube is turned on at a high level.

In one embodiment, the semiconductor memory further includes at least one byte data port, connected in one-to-one correspondence with the check module, for receiving the externally input data information or outputting the read data information to the outside.

In one embodiment, the semiconductor memory further includes a read/write control module, which is respectively connected to the verification module and the global data bus, and is configured to receive a read/write enable signal and select a data transmission direction between the verification module and the corresponding global data bus under the control of the read/write enable signal.

The semiconductor memory device includes: a plurality of storage arrays; the system comprises at least one checking module, a plurality of storage arrays and a plurality of data buses, wherein each checking module corresponds to the plurality of storage arrays and is used for checking whether data information of the corresponding storage arrays has errors or not; the gating circuits are respectively connected with the storage array and the global data bus and are used for controlling the connection and disconnection of a data transmission path between the connected global data bus and the storage array. According to the embodiment of the application, the gating circuit is controlled, so that the on-off of the data transmission path between the global data bus and each storage array can be controlled, the data information of a plurality of storage arrays connected with the same checking module can be read in a time-sharing mode, and the checking module only needs to check the data information of the checking module which is read in real time. Therefore, the semiconductor memory according to the embodiment of the application can ensure that effective verification is performed every time data information is read under the condition that a smaller number of verification modules are adopted, so that the semiconductor memory with a smaller space occupied by the verification modules is provided.

Drawings

FIG. 1 is a schematic diagram of a semiconductor memory with a half-bank structure according to an embodiment;

FIG. 2 is a schematic diagram of a semiconductor memory with a half-bank structure according to another embodiment;

FIG. 3 is a schematic diagram of a semiconductor memory with a half-bank structure according to yet another embodiment;

FIG. 4 is a block diagram of a semiconductor memory device with a complete memory block structure according to an embodiment;

FIG. 5 is a schematic diagram of a semiconductor memory of a complete memory block structure according to another embodiment;

FIG. 6 is a schematic diagram of a semiconductor memory of a complete memory block structure according to yet another embodiment;

FIG. 7 is a block diagram of a verification module in a semiconductor memory according to an embodiment.

Element number description:

a storage block: 10; storage array: 100, respectively; a first array: 110; a second array: 120 of a solvent; a third array: 130, 130; word line: 140 of a solvent; a first word line: 141, a solvent; a second word line: 142; bit line: 150; a first bit line: 151, and (b); a second bit line: 152; column selection lines: 160; a checking module: 200 of a carrier; an encoding unit: 210; an error detection unit: 220, 220; an error correction unit: 230; a gating circuit: 300, respectively; a first gating circuit: 310; a second gating circuit: 320, a first step of mixing; a third gating circuit: 330; a gating control module: 400, respectively; the read-write control module: 500, a step of; byte data port: 600, preparing a mixture; first byte data port: 610; second byte data port: 620; global data bus: 700

Detailed Description

To facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application belong. The terminology used herein in the description of the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Fig. 1 is a schematic structural diagram of a semiconductor memory having a half-bank structure according to an embodiment, and referring to fig. 1, in the embodiment, the semiconductor memory includes a plurality of memory arrays 100, at least one verification module 200, and a plurality of gating circuits 300.

The plurality of memory arrays 100 are used to store data, thereby implementing a memory function of the semiconductor memory. Specifically, the memory array 100 includes a word line, a bit line and a memory cell, and the memory cell further includes a storage capacitor and a transistor, a control terminal of the transistor is connected to the word line, a first terminal of the transistor is connected to the storage capacitor, and a second terminal of the transistor is connected to the bit line. When the word line control transistor is conducted, the storage capacitor is conducted with the bit line, so that data information is read and written, namely, when the data information is read, the storage capacitor transmits the stored data information to the bit line; when data information is written, the bit line sends the data information to be written to the storage capacitor.

Each verification module 200 corresponds to a plurality of storage arrays 100, the verification module 200 is configured to verify whether data information of the corresponding storage array 100 is in error, that is, each verification module 200 is configured to verify data information of the plurality of storage arrays 100, so as to optimize the number of the verification modules 200, each verification module 200 is connected to a group of global data buses 700, and the verification module 200 realizes transmission and reception of the data information through the global data buses 700.

The gating circuit 300 is respectively connected with the memory array 100 and the global data bus 700, and the gating circuit 300 is used for controlling the connection and disconnection of a data transmission path between the connected global data bus 700 and the memory array 100. Specifically, at the same time, the gating circuit 300 controls the global data bus 700 to be conductive to at most one of the plurality of memory arrays 100. Since the global data bus 700 is connected to the verification module 200 in this embodiment, the on/off state of the data transmission path between the global data bus 700 and the memory array 100, that is, the on/off state of the data transmission path between the verification module 200 and the memory array 100. Therefore, when the gating circuit 300 is turned on, the data transmission path between the global data bus 700 and the memory array 100 is turned on, and accordingly, the data transmission path between the check module 200 and the memory array 100 is turned on; when the power-on circuit 300 is turned off, the data transmission path between the global data bus 700 and the memory array 100 is turned off, and accordingly, the data transmission path between the check module 200 and the memory array 100 is turned off.

In the present embodiment, the semiconductor memory includes: a plurality of memory arrays 100; at least one check module 200, each check module 200 corresponds to a plurality of storage arrays 100, the check module 200 is configured to check whether data information of the corresponding storage array 100 is in error, and each check module 200 is connected to a group of global data buses 700; a plurality of gating circuits 300, wherein the gating circuits 300 are respectively connected with the memory array 100 and the global data bus 700, and the gating circuits 300 are used for controlling the connection and disconnection of the data transmission path between the connected global data bus 700 and the memory array 100. In this embodiment, the gating circuit 300 is controlled to control the on/off of the data transmission path between the global data bus 700 and each storage array 100, so that the data information of a plurality of storage arrays 100 connected to the same verification module 200 can be read in a time-sharing manner, and the verification module 200 only needs to verify the data information of the verification module 200 that is read in real time. Therefore, the semiconductor memory of the present embodiment can ensure effective verification every time data information is read with a smaller number of verification modules 200, thereby providing a semiconductor memory in which the verification modules 200 occupy a smaller space.

Further, with continued reference to fig. 1, the semiconductor memory further includes at least one byte data port 600, the byte data port 600 is connected to the check module 200 in a one-to-one correspondence, and the byte data port 600 is used for receiving externally input data information or outputting read data information to the outside. Fig. 1 shows two byte data ports 600 and two storage blocks 10, where the two byte data ports 600 specifically include a first byte data port 610 and a second byte data port 620, each storage block 10 includes a plurality of storage arrays 100, and the byte data ports 600 and the check modules 200 are connected to the storage blocks 10 in a one-to-one correspondence manner, that is, the plurality of storage arrays 100 in each storage block 10 are all connected to the same check module 200, and then connected to the same byte data port 600 via the check module 200. It should be noted that the byte data port 600 and the check module 200 are only used for illustration, the embodiment of the present invention is not limited thereto, and in other embodiments, the byte data port 600 may not correspond to the check module 200 one to one, for example, a plurality of byte data ports 600 correspond to one check module 200, and a person skilled in the art may select the ports according to needs, and the memory block 10 in this embodiment may be a complete memory bank (bank), or a half of the memory bank (bank), or another, which is not limited in this embodiment.

Each byte data port 600 may be used to transfer 8 bits of input data, i.e., the first byte data port 610 is used to transfer DQ <0:7>, the first byte data port 610 is used to transfer DQ <8:15>, and the semiconductor memory may choose to use a half-block structure for data information storage according to the performance of the external device. Taking the first byte data port 610 as an example, when data information is written, the external device sends out 8-bit data to be written, and transmits the data to one of the two storage arrays 100 connected to the external device through the first byte data port 610; when reading of data information is performed, 8 bits of data are read from one of the two memory arrays 100 connected to the first byte data port 610 and transmitted to an external device via the first byte data port 610. The data transmission mode of the second byte data port 620 is the same as that of the first byte data port 610, and is not described herein again. It should be noted that, due to the design of the prefetch (or burst) function of the present memory, 8-bit data may be transmitted multiple times in each communication between the external device and each byte data port of the memory, which is not limited to this embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a semiconductor memory with a half-bank structure according to another embodiment, and it should be noted that, since connection manners of the check module 200 and the memory array 100 corresponding to different byte data ports 600 are the same in this embodiment, in order to simplify the drawing, only the check module 200 and the memory array 100 connected to one byte data port 600 are shown in fig. 2 and described, connection manners of other byte data ports 600 may refer to fig. 2, the same simplification is also performed in the drawings of the embodiments of other half-bank structures, and details in other embodiments will not be repeated.

Referring to fig. 2, in the present embodiment, the semiconductor memory includes two memory arrays 100 and one verify block 200, the memory arrays 100 are in one-to-one correspondence with the gating circuits 300, and the memory arrays 100 are connected to the verify block 200 through the corresponding gating circuits 300 and the global data bus 700. The two memory arrays 100 are a first array 110 and a second array 120, respectively, the first array 110 is connected to the global data bus 700 through a first gating circuit 310, and the second array 120 is connected to the global data bus 700 through a second gating circuit 320. The check module 200 is connected to the byte data port 600 through a plurality of data transmission lines, and only 3 data transmission lines are shown in fig. 2, but it is understood that the number of the data transmission lines may not be limited to 3, and may be, for example, 1, 8, and so on.

Specifically, at most one of the first gating circuit 310 and the second gating circuit 320 is turned on at the same time. That is, when the byte data port 600 corresponding to the check module 200 of fig. 2 performs data transmission, data information is transmitted between the byte data port 600 and the check module 200 through the data transmission line, the check module 200 is turned on, and one of the first strobe circuit 310 and the second strobe circuit 320 is turned on, so that the first array 110 or the second array 120 performs data information reading and writing; when the corresponding byte data port 600 does not perform data transmission, the data transmission line is not used for transmitting data information, the verification module 200 is turned off, and both the first gating circuit 310 and the second gating circuit 320 are turned off, so that the first array 110 or the second array 120 is in a standby state and does not perform data information reading and writing.

In this embodiment, the gating circuit 300 selects to turn on one of the verification module 200 and the two storage arrays 100, so as to read and write data information of different storage arrays 100, and when any one of the storage arrays 100 reads and writes data, the data is verified through the same verification module 200 connected thereto, so that the number of the verification modules 200 to be set is reduced by improving the utilization rate of the verification module 200, the space occupied by the verification modules 200 in the semiconductor memory is reduced, and the semiconductor memory with higher integration level and smaller size can be realized.

With continued reference to fig. 2, in one embodiment, the semiconductor memory further comprises a strobe control module 400, the strobe control module 400 being configured to generate a plurality of strobe signals; the gating circuit 300 includes a switching tube, a control terminal of the switching tube is connected to the gating control module 400, a first terminal of the switching tube is connected to the global data bus 700, a second terminal of the switching tube is connected to the memory array 100, and the switching tube is configured to selectively turn on or off a data transmission path between the first terminal and the second terminal under the control of a gating signal. For convenience of illustration, the first gating circuit 310 is defined to include a first switching tube, and the second gating circuit 320 includes a second switching tube.

For example, the first switch tube and the second switch tube may have the same conduction characteristics, for example, both the switch tubes are turned on at a high level, if the gating control module 400 outputs a high level signal to the first switch tube and outputs a low level signal to the second switch tube, the data transmission path between the first array 110 and the verification module 200 is turned on, and the data transmission path between the second array 120 and the verification module 200 is turned off, so that the first array 110 reads and writes data information, and the verification module 200 verifies the data information read and written by the first array 110. This example provides a switch tube arrangement mode, so that the control logic of the switch tube is simple, and when it is necessary to continue to add the memory array 100 in the memory block 10, the switch tube arrangement mode can be correspondingly expanded according to the existing switch tube arrangement mode.

For example, the first switch tube and the second switch tube may have different conduction characteristics, for example, the first switch tube is turned on at a high level, the second switch tube is turned on at a low level, if the gating control module 400 outputs a high level signal to the first switch tube and the second switch tube at the same time, the data transmission path between the first array 110 and the verification module 200 is turned on, and the data transmission path between the second array 120 and the verification module 200 is turned off, so that the first array 110 reads and writes data information, and the verification module 200 verifies the data information read and written by the first array 110. Compared with the previous example, the arrangement mode of the present example is suitable for the case that each memory block 10 includes two memory arrays 100, and can omit one path of strobe signals, thereby simplifying the wiring between the verification module 200 and the memory arrays 100.

In one embodiment, the switch tube is a high voltage switch tube. Specifically, the transistors with relatively higher voltage in the chip may be, generally, a thicker gate oxide layer and/or a higher threshold voltage, etc., but the embodiments of the present invention are not limited thereto, and the high voltage switch tube is only a concept opposite to other transistors in the chip.

In the memory array 100, a plurality of memory cells are included, and each memory array 100 is connected with a plurality of word lines 140 (WL in the figure), a plurality of bit lines 150 (BL in the figure), and a plurality of column selection lines 160 (CS in the figure), the word lines 140 are connected with the plurality of memory cells in the row direction, the bit lines 150 are connected with the plurality of memory cells in the column direction, and when the word lines 140 corresponding to the memory cells are turned on, the memory cells can read and write data, that is, the memory cells can obtain data to be written from the corresponding bit lines 150 or send stored data to the corresponding bit lines 150. It should be noted that the word lines 140, the column selection lines 160, and the bit lines 150 shown in fig. 2 are only schematic and do not represent the connection relationship between the two, and the relationship between the three can refer to the conventional arrangement in the memory.

In one embodiment, the semiconductor memory further includes a read/write control module 500, which is respectively connected to the check module 200 and the global data bus 700, and the read/write control module 500 is configured to receive the read/write enable signals (the read enable signal RdEn and the write enable signal WrEn) and select a data transmission direction between the check module 200 and the corresponding global data bus 700 under the control of the read/write enable signal. Specifically, the read/write control module 500 may include a plurality of read/write control units, the number of the read/write control units matches with the number of bits of the data information to be read/written, for example, each check module 200 may be correspondingly connected with 8 read/write control units.

Further, the read/write control unit may be a bidirectional driver, the data flow direction of the verification module 200 to the global data bus 700 is a write direction, and the data flow direction of the global data bus 700 to the verification module 200 is a read direction. The output transmission path in the writing direction is provided with a writing control unit, the output transmission path in the reading direction is provided with a reading control unit, and the writing control unit and the reading control unit are not opened at the same time. The write control unit receives the write enable signal WrEn and conducts the data transmission path in the write direction under the control of the write enable signal WrEn, so that the verification module 200 sends data information to be written to the global data bus 700; the read control unit receives the read enable signal RdEn and turns on the data transmission path in the read direction under the control of the read enable signal RdEn, so that the verification module 200 obtains the read data information from the global data bus 700.

Fig. 3 is a schematic structural diagram of a semiconductor memory having a half-bank structure according to yet another embodiment, and referring to fig. 3, in this embodiment, the semiconductor memory includes three memory arrays 100 and one verify module 200, the memory arrays 100 are in one-to-one correspondence with the gating circuits 300, and the memory arrays 100 are connected to the verify module 200 through the corresponding gating circuits 300 and the global data bus 700. The three memory arrays 100 are the first array 110, the second array 120 and the third array 130, respectively, and the three gating circuits 300 are the first gating circuit 310, the second gating circuit 320 and the third gating circuit 330, respectively.

Specifically, at most one of the first gate circuit 310, the second gate circuit 320, and the third gate circuit 330 is turned on at the same time. That is, when the byte data port 600 corresponding to the verification module 200 in fig. 3 performs data transmission, data information is transmitted between the byte data port 600 and the verification module 200 through the data transmission line, the verification module 200 is turned on, and one of the first strobe circuit 310, the second strobe circuit 320 and the third strobe circuit 330 is turned on, so that the memory array 100 corresponding to the turned-on strobe circuit 300 performs data information reading and writing; when the corresponding byte data port 600 does not perform data transmission, the data transmission line is not used for transmitting data information, the verification module 200 is turned off, and the first gating circuit 310, the second gating circuit 320 and the third gating circuit 330 are all turned off, so that the three storage arrays 100 are all in a standby state and do not perform data information reading and writing.

In this embodiment, three storage arrays 100 are disposed in each storage block 10, so as to obtain more optimized storage performance, and one of the verification module 200 and the three storage arrays 100 is selectively turned on by the gating circuit 300, so as to implement reading and writing of data information of different storage arrays 100, and when any one of the storage arrays 100 reads and writes data, verification is performed through the same connected verification module 200, so that the number of the verification modules 200 that need to be disposed is reduced in a manner of improving the utilization rate of the verification module 200, the space occupied by the verification module 200 in the semiconductor memory is reduced, and further, a semiconductor memory with higher integration level and smaller size can be implemented.

Fig. 4 is a schematic structural diagram of a semiconductor memory with a complete memory block structure according to an embodiment, in which fig. 4 illustrates two byte data ports 600 and one memory block 10, the two byte data ports 600 specifically include a first byte data port 610 and a second byte data port 620, each memory block 10 includes a plurality of memory arrays 100, and at least some of the memory arrays 100 are respectively connected to two verification modules 200 through corresponding gating circuits 300. That is, in the semiconductor memory having the complete memory block structure, each memory block 10 may correspond to two byte data ports 600, for example, if each byte data port 600 can transmit 8-bit data, each memory block 10 may synchronously read and write 16-bit data information, thereby achieving better memory performance.

Fig. 5 is a schematic structural diagram of a semiconductor memory having a complete memory block structure according to another embodiment, and referring to fig. 5, in this embodiment, the semiconductor memory includes three memory arrays 100 and two verification modules 200, the three memory arrays 100 include a first array 110, a second array 120 and a third array 130, the second array 120 is connected to two second gating circuits 320, and the second gating circuits 320 are connected to a global data bus 700 in a one-to-one correspondence manner.

A global data bus 700 is connected to each of the verification modules 200, and the second array 120 includes a first bit line 151 and a second bit line 152, the first bit line 151 being connected to one of the two second strobes 320, and the second bit line 152 being connected to the other of the two second strobes 320. It should be noted that the connection between the first bit line 151 and the second gate 320 may be a direct connection, that is, the first bit line 151 and the second gate 320 are connected via a trace, or may be an indirect connection, for example, another control device or processing device may be added between the first bit line 151 and the second gate 320, and the first bit line 151 and the second gate 320 are connected via the added device, so as to implement a richer control function or signal processing function. Similarly, the connection between the second bit line 152 and the second gating circuit 320 may be a direct connection or an indirect connection, which is not described herein.

The second array 120 also includes column select lines 160, first word lines 141, and second word lines 142. When data is written, the verification module 200 synchronously transmits data information to the corresponding global data bus 700; during data reading, the two check modules 200 synchronously acquire data information from the corresponding global data bus 700. For example, in the embodiment shown in fig. 5, the word line 140 and the column selection line 160 of the first array 110 are enabled, the word line 140 and the column selection line 160 of the third array 130 are enabled, and none of the first word line 141, the second word line 142, and the column selection line 160 of the second array 120 are enabled (as shown by dotted lines), so that a data transmission path between one of the verification modules 200 and the first array 110 is turned on, a data transmission path between the other of the verification modules 200 and the third array 130 is turned on, and each of the memory arrays 100 can read and write 8-bit data information, so that each of the memory blocks 10 can synchronously read and write 16-bit data information, thereby achieving better performance.

Fig. 6 is a schematic structural diagram of a semiconductor memory of a complete memory block structure according to yet another embodiment, and referring to fig. 6, in this embodiment, in one embodiment, two first gating circuits 310 are connected to the first array 110, and the first gating circuits 310 are connected to the global data bus 700 in a one-to-one correspondence; the third array 130 is connected with two third gating circuits 330, and the third gating circuits 330 are connected with the global data bus 700 in a one-to-one correspondence manner; the first gating circuit 310, the second gating circuit 320 and the first gating circuit 310 connected to the same global data bus 700 are turned on in a time-sharing manner.

Specifically, each memory array 100 has a respective first word line 141, second word line 142, first bit line 151, second bit line 152, and column select line 160, the first bit line 151 being connected to one global data bus 700 through one gating circuit 300, and the second bit line 152 being connected to another global data bus 700 through another gating circuit 300. In each data reading and writing process, each verification module 200 may transmit data information with one of the three storage arrays 100, and two verification modules 200 may transmit data information with the same storage array 100 synchronously. For example, in the embodiment shown in fig. 6, the first word line 141, the second word line 142, and the column selection line 160 of the first array 110 are enabled, none of the first word line 141, the second word line 142, and the column selection line 160 of the second array 120 are enabled (as shown by the dotted line), and none of the first word line 141, the second word line 142, and the column selection line 160 of the third array 130 are enabled, so that the data transmission path between each of the two verification modules 200 and the first array 110 is turned on, thereby implementing the transmission of data information. As can be seen from the figure, the same set of column selection signals CS may be used for different byte data ports, and if word lines corresponding to different byte data ports are all turned on, when the column selection signals CS are turned on, data corresponding to each word line may be respectively connected to global data buses corresponding to different byte data ports, so that the number of turned-on column selection signals CS is saved by sharing the same set of column selection signals CS, and power consumption caused by turning on the column selection signals CS is saved.

Fig. 7 is a schematic structural diagram of a verification module 200 in a semiconductor memory according to an embodiment, as shown in fig. 7, in which the verification module 200 includes an encoding unit 210 and an error detection unit 220.

The encoding unit 210 is connected to the storage array 100, and is configured to receive input data information, encode the data information to generate write check information, and send the data information and the write check information to the storage array 100;

the error detection unit 220 is connected to the memory array 100, and is configured to synchronously read data information and write parity information from the memory array 100, and verify whether an error occurs in the read data information according to the write parity information.

It can be understood that, the encoding unit 210 encodes the data information according to a preset rule, so that the generated write verification information is in one-to-one correspondence with the data information, and if the read data information is found not to match the write verification information when data reading is performed, it indicates that a change of the data information occurs in the read-write process of the data information, thereby causing a data information error. Therefore, the present embodiment can accurately find whether an error occurs in the read data information through the encoding unit 210 and the error detection unit 220, thereby improving the accuracy of the read data information.

With continued reference to fig. 7, the error detection unit 220 is further connected to the encoding unit 210, and the encoding unit 210 is further configured to encode the read data information to generate read check information, and send the read check information to the error detection unit 220; the error detection unit 220 is configured to obtain the write check information and the read check information, and compare the write check information and the read check information to determine whether the read data information is in error.

In one embodiment, the checking module 200 further includes an error correction unit 230, and the error correction unit 230 is connected to the error detection unit 220, and configured to receive the read data information and the comparison result information of the error detection unit 220, and update the data information according to the comparison result information.

Specifically, the comparison result information includes whether the read data information is the same as the written data information, and when the read data information is different from the written data information, the comparison result information further includes a specific error data bit, for example, if the written data information is 10000000 and the read data information is 11000000, the error data bit is the 2 nd bit. The error correction unit 230 is configured to receive the comparison result information and directly perform error correction according to the comparison result information. For example, if the read data information is 11000000 and the 2 nd bit in the comparison result information is an error data bit, the written data information is 10000000 inevitably, and the error correction unit 230 can update the data information to complete error correction. The error correction unit 230 is provided in the present embodiment, so that the read error data information can be corrected, and correct read data information can be output.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above embodiments only express a few embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the appended claims.

Claims

1. A semiconductor memory, comprising:

a plurality of storage arrays;

2. The semiconductor memory according to claim 1, wherein the semiconductor memory comprises two of the memory arrays and one of the check modules, the memory arrays are in one-to-one correspondence with the gating circuits, and the memory arrays are connected to the check modules through the corresponding gating circuits and the global data bus.

3. The semiconductor memory according to claim 1, wherein the semiconductor memory comprises three memory arrays and one check module, the memory arrays are in one-to-one correspondence with the gating circuits, and the memory arrays are connected to the check module through the corresponding gating circuits and the global data bus.

4. The semiconductor memory according to claim 1, wherein the semiconductor memory includes three memory arrays and two check modules, the three memory arrays include a first array, a second array and a third array, the second array is connected with two second gating circuits, and the second gating circuits are connected with the global data bus in a one-to-one correspondence manner.

5. The semiconductor memory according to claim 4, wherein the second array includes a first bit line and a second bit line, the first bit line being connected to one of the two second gates, the second bit line being connected to the other of the two second gates.

6. The semiconductor memory according to claim 4, wherein two first gating circuits are connected to the first array, the first gating circuits being connected in one-to-one correspondence with the global data buses;

7. The semiconductor memory according to claim 1, wherein the verification module comprises:

8. The semiconductor memory according to claim 7, wherein the error detection unit is further connected to the encoding unit, the encoding unit is further configured to encode the read data information to generate read check information, and send the read check information to the error detection unit;

9. The semiconductor memory according to claim 8, wherein the check module further comprises an error correction unit connected to the error detection unit for receiving the read data information and the comparison result information of the error detection unit and updating the data information according to the comparison result information.

10. The semiconductor memory according to claim 1, further comprising a strobe control module for generating a plurality of strobe signals;

11. The semiconductor memory according to claim 10, wherein the switching tube is a high voltage switching tube.

12. The semiconductor memory according to claim 10, wherein the switching transistor is turned on at a high level.

13. The semiconductor memory according to claim 1, further comprising at least one byte data port connected to the check module in a one-to-one correspondence, for receiving the externally input data information or outputting the read data information to the outside.

14. The semiconductor memory according to claim 1, further comprising a read/write control module respectively connected to the verification module and the global data bus, wherein the read/write control module is configured to receive a read/write enable signal and select a data transmission direction between the verification module and the corresponding global data bus under the control of the read/write enable signal.