CN213149022U - Integrated circuit power chip test interface board - Google Patents
Integrated circuit power chip test interface board Download PDFInfo
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- CN213149022U CN213149022U CN202022078431.3U CN202022078431U CN213149022U CN 213149022 U CN213149022 U CN 213149022U CN 202022078431 U CN202022078431 U CN 202022078431U CN 213149022 U CN213149022 U CN 213149022U
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Abstract
The utility model belongs to the technical field of integrated circuit, especially, be an integrated circuit power chip test interface board, including test equipment, test equipment's bottom is provided with the base, test equipment's surface is provided with power source, test equipment's surface is provided with the pilot lamp, test equipment's top is provided with the test interface board, the inside of test interface board is provided with the heat dissipation fan, the top of test interface board is provided with the spring, the one end of spring is provided with the clamp plate. The JTAG interface, the AS interface, the expansion interface, the secondary expansion interface and the USB interface are arranged on the surface of the test interface board, so that various integrated circuit power supply chips can be tested, the practicability of the test interface board is improved, the heat dissipation fan is arranged in the test interface board and matched with the heat dissipation holes on the surface of the pressing plate, heat can be dissipated to the interface board and the chips during testing, and the interface board and the chips are prevented from being damaged due to overhigh temperature.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit, concretely relates to integrated circuit power chip test interface board.
Background
An integrated circuit is a microelectronic device or component. The transistor, the resistor, the capacitor, the inductor and other elements and wires required in a circuit are interconnected together by adopting a certain process, are manufactured on a small or a plurality of small semiconductor wafers or medium substrates, and are then packaged in a tube shell to form a micro structure with the required circuit function; all the elements are structurally integrated, so that the electronic elements are greatly miniaturized, low in power consumption, intelligent and high in reliability. It is denoted by the letter "IC" in the circuit. Most applications in the semiconductor industry today are silicon-based integrated circuits. The integrated circuit chip comprises an electronic element formed by mixing a silicon substrate, a circuit, a fixed seal ring and a grounding ring with at least one group of guard rings.
However, the conventional ic power chip test interface board cannot provide multiple interfaces, and cannot test the ic power chips with multiple interfaces, so that the test interface board has limitations, and generates heat during testing, and cannot dissipate heat from the chip and the interface board, which causes inconvenience in use.
SUMMERY OF THE UTILITY MODEL
To solve the problems set forth in the background art described above. The utility model provides an integrated circuit power chip test interface board has solved awkward problem.
In order to achieve the above object, the utility model provides a following technical scheme: a kind of integrated circuit power chip tests the interface board, including the test equipment, the bottom of the said test equipment has bases, the surface of the said test equipment has power interfaces, the surface of the said test equipment has pilot lamps, the top of the said test equipment has test interface boards, the inside of the said test interface boards has heat-dissipating fans, the top of the said test interface boards has springs, one end of the said springs has pressing plates, the bottom of the said pressing plates has insulating pads, the surface of the said pressing plates has heat-dissipating holes, the bottom of the said pressing plates has glue columns, one end of the said glue columns has glue plates, the surface of the said test interface boards has JTAG interfaces, the surface of the said test interface boards has AS interfaces, the surface of the said test interface boards has expansion interfaces, the surface of the said test interface boards has sub-expansion interfaces, the surface of the test interface board is provided with a USB interface, the inside of the test equipment is provided with a circuit module, and the inside of the test equipment is provided with an expansion module.
Preferably, the number of the USB interfaces is multiple, and the USB interfaces are arranged on the surface of the test interface board in a linear arrangement.
Preferably, the number of the glue columns is two, and the number of the glue plates is consistent with that of the glue columns.
Preferably, the insulating pads are arranged on two sides of the spring, and the test interface board is connected with the pressure plate through the spring.
Preferably, the heat dissipation holes are linearly arranged on the surface of the pressing plate, and the heat dissipation fan corresponds to the heat dissipation holes.
Compared with the prior art, the beneficial effects of the utility model are that:
the JTAG interface, the AS interface, the expansion interface, the secondary expansion interface and the USB interface are arranged on the surface of the test interface board, so that various integrated circuit power supply chips can be tested, the practicability of the test interface board is improved, the heat dissipation fan is arranged in the test interface board and matched with the heat dissipation holes on the surface of the pressing plate, heat can be dissipated to the interface board and the chips during testing, and the interface board and the chips are prevented from being damaged due to overhigh temperature.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a complete structural schematic diagram of the present invention;
FIG. 2 is a front view of the structure of the present invention;
FIG. 3 is a diagram of an interface board structure according to the present invention;
fig. 4 is a top view cross-sectional structure of the present invention.
In the figure: 1, testing equipment; 2, a power interface; 3 an indicator light; 4, testing the interface board; 5, a heat dissipation fan; 6, a spring; 7, pressing a plate; 8, an insulating pad; 9 heat dissipation holes; 10, glue columns; 11, gluing a rubber plate; 12JTAG interface; 13AS interface; 14 an expansion interface; 15 times of expansion interface; 16USB interface; 17 a circuit module; 18 an expansion module; 19, a base.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-4, the present invention provides the following technical solutions: a test interface board of an integrated circuit power chip comprises a test device 1, a base 19 is arranged at the bottom of the test device 1, a power interface 2 is arranged on the surface of the test device 1, an indicator lamp 3 is arranged on the surface of the test device 1, a test interface board 4 is arranged at the top of the test device 1, a heat dissipation fan 5 is arranged inside the test interface board 4, a spring 6 is arranged at the top of the test interface board 4, a pressing plate 7 is arranged at one end of the spring 6, an insulating pad 8 is arranged at the bottom of the pressing plate 7, a heat dissipation hole 9 is arranged on the surface of the pressing plate 7, a glue column 10 is arranged at the bottom of the pressing plate 7, a glue plate 11 is arranged at one end of the glue column 10, a JTAG interface 12 is arranged on the surface of the test interface board 4, an AS interface 13 is arranged on the surface of the, the surface of the test interface board 4 is provided with a USB interface 16, the interior of the test equipment 1 is provided with a circuit module 17, and the interior of the test equipment 1 is provided with an expansion module 18.
In this embodiment, by arranging multiple interfaces of JTAG interface 12, AS interface 13, expansion interface 14, secondary expansion interface 15 and USB interface 16 on the surface of the test interface board 4, various integrated circuit power chips can be tested, the practicability of the test interface board 4 is improved, by arranging the heat dissipation fan 5 inside the test interface board 4 and matching with the heat dissipation hole 9 on the surface of the pressing plate 7, during testing, the test interface board 4 and the chips can be cooled to prevent the test interface board 4 and the chips from being damaged due to overhigh temperature, the test interface board 4 is arranged on two sides of the spring 6 through the insulating pad 8, the test interface board 4 is connected with the pressing plate 7 through the spring 6, the end surface of the pressing plate 4 is fixed to the connection between the chips and the interfaces through the insulating pad 8, the number of the rubber columns 10 is two, the number of the rubber plates 11 is the same AS the number of the rubber columns 10, and the auxiliary pressing plate 7 presses the end surface of the test, prevent to collide the chip in careless interval, make chip and interface connection not hard up, influence the test result, through setting up testing arrangement 1, cooperate circuit module 17 and expansion module 18, can test the chip, through setting up pilot lamp 3, can show the test result, through setting up base 19, increased test equipment 1's steadiness.
Specifically, the number of the USB interfaces 16 is plural, the USB interfaces 16 are linearly arranged on the surface of the test interface board 4, and the USB interfaces 16 are linearly arranged on the surface of the test interface board 4 through the plural USB interfaces 16, so that the USB type integrated circuit power chip interface can be tested.
Specifically, the number of the glue columns 10 is two, the number of the glue plates 11 is the same as the number of the glue columns 10, and the auxiliary pressure plate 7 presses and holds the end face of the test interface board 4 to prevent the chip from being collided accidentally, so that the chip and the interface are not connected tightly, and the test result is influenced.
Specifically, the insulating pads 8 are arranged on two sides of the spring 6, the test interface board 4 is connected with the pressing plate 7 through the spring 6, and the end face of the pressing plate 4 is used for insulating, pressing and fixing the joint between the chip and the interface through the insulating pads 8.
Specifically, the heat dissipation holes 9 are linearly arranged on the surface of the pressing plate 7, the heat dissipation fan 5 corresponds to the heat dissipation holes 9, and heat can be generated at the joint between the chip and the interface during testing, so that heat dissipation can be facilitated at the joint between the chip and the interface.
The utility model discloses a theory of operation and use flow: after the utility model is installed, when in use, the utility model is electrically connected with an external power supply through the power interface 2, the JTAG interface 12, the AS interface 13, the expansion interface 14, the sub-expansion connector 15 and the USB interface 16 are arranged on the surface of the test interface board 4, so AS to test various integrated circuit power supply chips, the heat radiation fan 5 is arranged inside the test interface board 4, the heat radiation effect on the connection part between the test interface board 4 and the chip is realized through the heat radiation holes 9 on the surface of the matching pressing plate 7, the insulating pads 8 are arranged on the two sides of the spring 6, so AS to realize the insulating, pressing and fixing effects on the connection part between the chip and the interface, the quantity of the rubber plates 11 is consistent with that of the rubber columns 10, the effect of pressing and holding the end surface of the test interface board 4 by the auxiliary pressing plate 7 is realized, through the arrangement of the testing device 1, the circuit module 17 is matched with the expansion module 18, the effect to the chip test has been played, through setting up pilot lamp 3, has played the effect that shows the test result, and the test is through being green, and the test is not through being red, through setting up base 19, has played the effect of firm test equipment 1.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. The utility model provides an integrated circuit power chip test interface board, includes test equipment (1), the bottom of test equipment (1) is provided with base (19), its characterized in that: the surface of the test equipment (1) is provided with a power interface (2), the surface of the test equipment (1) is provided with an indicator lamp (3), the top of the test equipment (1) is provided with a test interface board (4), the inside of the test interface board (4) is provided with a heat dissipation fan (5), the top of the test interface board (4) is provided with a spring (6), one end of the spring (6) is provided with a pressing plate (7), the bottom of the pressing plate (7) is provided with an insulating pad (8), the surface of the pressing plate (7) is provided with a heat dissipation hole (9), the bottom of the pressing plate (7) is provided with a glue column (10), one end of the glue column (10) is provided with a glue plate (11), the surface of the test interface board (4) is provided with a JTAG interface (12), the surface of the test interface board (4, the surface of the test interface board (4) is provided with an expansion interface (14), the surface of the test interface board (4) is provided with a secondary expansion interface (15), the surface of the test interface board (4) is provided with a USB interface (16), the inside of the test equipment (1) is provided with a circuit module (17), and the inside of the test equipment (1) is provided with an expansion module (18).
2. The integrated circuit power chip test interface board of claim 1, wherein: the number of the USB interfaces (16) is multiple, and the USB interfaces (16) are linearly arranged on the surface of the test interface board (4).
3. The integrated circuit power chip test interface board of claim 1, wherein: the number of the rubber columns (10) is two, and the number of the rubber plates (11) is consistent with that of the rubber columns (10).
4. The integrated circuit power chip test interface board of claim 1, wherein: the insulation pads (8) are arranged on two sides of the spring (6), and the test interface board (4) is connected with the pressing plate (7) through the spring (6).
5. The integrated circuit power chip test interface board of claim 1, wherein: the heat dissipation holes (9) are linearly arranged on the surface of the pressing plate (7), and the heat dissipation fan (5) corresponds to the heat dissipation holes (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022078431.3U CN213149022U (en) | 2020-09-21 | 2020-09-21 | Integrated circuit power chip test interface board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022078431.3U CN213149022U (en) | 2020-09-21 | 2020-09-21 | Integrated circuit power chip test interface board |
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| Publication Number | Publication Date |
|---|---|
| CN213149022U true CN213149022U (en) | 2021-05-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022078431.3U Active CN213149022U (en) | 2020-09-21 | 2020-09-21 | Integrated circuit power chip test interface board |
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| CN (1) | CN213149022U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113810834A (en) * | 2021-10-27 | 2021-12-17 | 安徽井利电子有限公司 | Adjustable loudspeaker with sound equipment arranged in belt type and debugging method thereof |
-
2020
- 2020-09-21 CN CN202022078431.3U patent/CN213149022U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113810834A (en) * | 2021-10-27 | 2021-12-17 | 安徽井利电子有限公司 | Adjustable loudspeaker with sound equipment arranged in belt type and debugging method thereof |
| CN113810834B (en) * | 2021-10-27 | 2023-05-12 | 安徽井利电子有限公司 | Adjustable loudspeaker with belt-type arrangement inside sound equipment and debugging method thereof |
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