CN212965302U

CN212965302U - High-density addressable test chip capable of expanding parallel test

Info

Publication number: CN212965302U
Application number: CN202022023149.5U
Authority: CN
Inventors: 杨璐丹; 潘伟伟
Original assignee: Hangzhou Guangli Microelectronics Co ltd
Current assignee: Hangzhou Guangli Microelectronics Co ltd
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2021-04-13
Anticipated expiration: 2030-09-16

Abstract

The utility model provides a high-density addressable test chip capable of expanding parallel test, which comprises a counter, an addressing circuit, a plurality of devices to be tested, a parallel group and a plurality of bonding pads; the counter is used for generating an address signal; the device to be tested parallel group comprises a switch circuit and a plurality of device blocks to be tested, each device block to be tested consists of a plurality of devices to be tested, and each device to be tested is connected to a test signal wire through the switch circuit; the output end of the addressing circuit is connected to the control end of the switch circuit, and the on-off of a switch in the switch circuit is controlled, so that the corresponding device to be tested in the parallel group of the devices to be tested is selected to be communicated with the test signal line, and parallel test is carried out. Preferably, in the parallel group of the devices to be tested, each device to be tested is connected to four test signal lines through four switches, so that kelvin four-terminal test can be performed. The testing efficiency is improved, the utilization rate of the chip area is increased, and the necessary accuracy is guaranteed.

Description

High-density addressable test chip capable of expanding parallel test

Technical Field

The utility model belongs to test chip design and test field, concretely relates to can expand high density addressable test chip of parallel test.

Background

As the design scale of integrated circuits continues to expand, the density of electronic devices on a single chip increases, and the feature size of electronic devices decreases. Meanwhile, the integrated circuit process flow includes many complex process steps, each of which has a specific process deviation, resulting in a reduction in the yield of integrated circuit chips. In the background of manufacturability design, in order to improve the yield of integrated circuit products and shorten the yield maturation period, a test method based on a specially designed test chip is commonly used in the industry, and data necessary for improving the manufacturing process and the design yield is acquired through testing the test chip.

Short-range test chips and addressable test chips are two types of test chips often used in the manufacturing process of integrated circuit chips. The short-range test chip is widely applied due to short production period, flexible test and high test precision. However, in the conventional short-range test chip, each terminal of each device under test needs to be connected to a terminal pad separately, so each device under test needs to be connected to two or more pads, and these devices under test and pads may be placed on the same layer, or the connection terminals of the devices under test may be connected to the pads on the pad layer through a contact hole in a one-to-one correspondence manner, which results in a particularly low area utilization rate.

The addressable test chip utilizes the decoder and the switch selection circuit to achieve the purpose that a plurality of test structures share the bonding pad. Based on the requirement of advanced semiconductor technology, peripheral circuits in the addressable test chip are fully utilized in the semiconductor manufacturing link after being optimized. However, the magnitude of the device that can be measured by the common addressable circuit is 'one', and the measurement must be performed by scanning one by one, which does not meet the requirement of rapid measurement of high-density devices in advanced technology.

On the other hand, the scribing groove is a space reserved on the wafer for cutting the chip, and the test chip is placed in the scribing groove, so that the position of the chip can not be occupied, a semiconductor manufacturer does not need to bear expensive mask cost, and a large amount of cost is saved. But the dicing groove area is limited, and how to reduce the area of the high-density test chip is also a great challenge.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a problem based on above-mentioned prior art and going on, aim at provides a can expand parallel test's high density addressable test chip, supports parallel test, accomplishes the test of a plurality of devices that await measuring simultaneously, improves test speed by a wide margin, realizes the rapid survey to further reduce test chip's required area, satisfy the demand that the scribing inslot used.

The utility model provides a high-density addressable test chip capable of expanding parallel test, which comprises a counter, an addressing circuit, a plurality of devices to be tested, a parallel group and a plurality of bonding pads; the device to be tested parallel group comprises a switch circuit and a plurality of device blocks to be tested, each device block to be tested consists of a plurality of devices to be tested, and each device to be tested is connected to a test signal wire through the switch circuit; the output end of the addressing circuit is connected to the control end of the switch circuit of the parallel group of the device to be tested and is used for transmitting an address signal to the switch circuit of the parallel group of the device to be tested, so that the on-off of a switch in the switch circuit is controlled, and the corresponding device to be tested in the parallel group of the device to be tested is selected to be communicated with the test signal line for parallel test; the bonding pads comprise a power supply access bonding pad, a clock signal bonding pad, a reset signal bonding pad and a plurality of test signal bonding pads; the power supply access pad is used for supplying power to the counter, the addressing circuit and the switch circuit; the test signal bonding pad is connected with a test signal wire; the input end of the counter is connected with the clock signal bonding pad and the reset signal bonding pad, the output end of the counter is connected with the input end of the addressing circuit, and the counter is used for generating address signals.

In the design, parallel testing can be performed by arranging a plurality of devices to be tested in parallel, so that the testing efficiency is improved.

Specifically, in the parallel group of the devices to be tested, each device to be tested is connected to four test signal lines through four switches, and kelvin four-terminal testing can be performed.

The advantage of the kelvin four-terminal test is that the measurement is more accurate and the interference of the wiring impedance is eliminated. In the design, each device to be tested is connected to four test signal lines through four switches, 4 test ends can perform Kelvin four-end test, and the measurement is more accurate.

Preferably, in the parallel group of the devices to be tested, two switches are shared between adjacent devices to be tested. That is, if two switches are set as a group, for example, for 64 devices under test, only 65 groups of switches need to be set. The method is favorable for reducing the number of switches and simplifying the circuit on the premise of realizing Kelvin four-terminal test.

In another specific implementation, each device under test parallel group is connected to an independent group of test signal lines, that is, the plurality of device under test parallel groups are provided with N groups, correspondingly, the test signal pads are provided with N groups, and the test signal lines are also provided with N groups. Specifically, when the high-density addressable test chip capable of expanding parallel testing is provided with N groups of devices to be tested in parallel, N groups of test signal pads are correspondingly arranged and connected to N groups of test signal lines. When the test signal pads are added to the N +1 group, a parallel group of the devices to be tested is expanded, namely the parallel group of the N +1 devices to be tested is expanded.

In a possible implementation scheme, at least two empty address bits are arranged in each device block to be tested and used for background leakage current detection, address verification and continuous addressing in the device block to be tested; the empty address bit is provided with a switch, and the corresponding device to be tested is not placed in the address bit selected by the switch circuit.

In another possible embodiment, the addressing circuit is implemented using two stages of decoders, namely a row decoder and a column decoder; the row decoder is used for selecting the device blocks to be tested in the parallel group of the devices to be tested, and the column decoder is used for selecting the devices to be tested in the device blocks to be tested. Therefore, background leakage current can be reduced, and one device to be tested in the parallel group of the devices to be tested is selected for testing.

In an advantageous embodiment, the switching circuit comprises a number of switches and a number of two-input and gates.

In another advantageous embodiment, the counter is an asynchronous counter.

In a preferred embodiment, the counter comprises positive edge flip-flops and buffers, and the number of the positive edge flip-flops is matched with the number of address bits required by the addressing circuit, i.e. the number of the positive edge flip-flops is equal to the number of address bits required by the addressing circuit. The Qn end of each positive edge trigger is connected to the D end through a buffer, and the buffer is used for keeping time; the reset end of each positive edge trigger is connected to a reset signal pad and used for low-level reset; the Q end of each positive edge trigger is an output end and is connected with the addressing circuit, and each positive edge trigger outputs a bit address; the positive edge triggers are in a continuous queue, the input end of the positive edge trigger positioned at the head of the queue is connected to the clock signal bonding pad, and the input ends of the other positive edge triggers are connected to the Qn end of the positive edge trigger positioned at the front bit of the queue.

In a further preferred practice, the pads further include an output signal pad, and the output signal pad is connected to the Q terminal of the positive edge flip-flop at the head of the queue in the counter, and is used for performing least significant bit address verification.

In addition, in a preferred embodiment, the power supply access pads are provided with at least two pairs, wherein one pair is used for independently supplying power to the counter, and the other pair is used for supplying power to other circuits except the counter. The counter is independently powered in the scheme, so that the working stability of the counter can be guaranteed.

The utility model discloses following beneficial effect has: according to the high-density addressable test chip capable of expanding parallel tests, the parallel group comprising a plurality of devices to be tested can carry out parallel tests, so that the rapid test is realized; the number of parallel tests can be increased by increasing the number of the test signal pads according to a specific application scene; the devices to be tested in different layers can be overlapped, meanwhile, the counter is used for generating address signals, the size requirement of being placed in the scribing groove can be still met on the basis of further expanding the testing amount of the devices, and the number of required bonding pads is reduced. The Kelvin connection of the two excitation ports and the two induction ports is adopted for the device to be tested, so that the electrical characteristics of the selected device to be tested can be accurately measured; the necessary accuracy is also maintained while the efficiency of the test is improved.

Drawings

Fig. 1 is a schematic structural diagram of a high-density addressable test chip capable of expanding parallel tests according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a counter in an embodiment of the invention.

Fig. 3 is a schematic diagram of a pad configuration in a pad area when 4 parallel groups of devices under test are set according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a clock signal, a reset signal, and address bit signals of a counter according to an embodiment of the present invention.

Detailed Description

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings. In the drawings, not all illustrated parts are necessarily marked with the associated reference numerals throughout the figures for clarity of illustration.

A high-density addressable test chip capable of expanding parallel test comprises a counter, an addressing circuit, a plurality of devices to be tested, a parallel group and a plurality of bonding pads, wherein the overall structure of the high-density addressable test chip is schematically shown in figure 1, and a test control circuit in figure 1 is used for illustrating the counter and the addressing circuit.

In this embodiment, the to-be-tested device parallel group includes a Switch circuit and a plurality of to-be-tested device blocks, each to-be-tested device Block is composed of a plurality of to-be-tested devices DUT, each Switch circuit includes a plurality of switches and a plurality of two-input and gates, and in this embodiment, each Switch may be an NMOS, a PMOS, or a transmission gate; each DUT is connected to the test signal line VPIN1, the test signal line IPIN1, the test signal line VPIN2, and the test signal line IPIN2 through 4 switches, respectively, so as to perform kelvin four-terminal testing, and in practical applications, each DUT is connected in parallel to an independent set of test signal lines (i.e., 4 test signal lines VPIN1, test signal line IPIN1, test signal line VPIN2, and test signal line IPIN 2). Sharing two switches between adjacent devices to be tested (DUTs); that is, if two switches are set as a group, only 65 groups of switches need to be set for 64 devices under test. In this embodiment, each parallel group of devices to be tested is composed of 8 parallel groups of devices to be tested, as shown in fig. 1, when the high-density addressable test chip capable of expanding parallel tests is provided with N parallel groups of devices to be tested, that is, the device blocks to be tested in one parallel group of devices to be tested are Block1i, Block2i, Block3i, Block4i, Block5i, Block6i, Block7i, Block8i, i ∈ [1, N ]. In the ith parallel group of devices under test, each device under test DUT is connected to the test signal line VPIN1i, the test signal line IPIN1i, the test signal line VPIN2i, and the test signal line IPIN2i, respectively, through four switches. That is, kelvin connections of two excitation ports and two sensing ports are adopted for the device under test DUT, specifically, a circuit between the test signal line VPIN1i and the test signal line VPIN2i may be used as an excitation circuit, and a circuit between the test signal line IPIN1i and the test signal line IPIN2i may be used as a sensing circuit, which is only an example and not a limitation of this embodiment.

In each device Block to be tested, at least two empty address bits are also arranged and are designed to be empty: background leakage current detection, address verification and continuous addressing in a limited device block to be tested. In this embodiment, each device Block to be tested is provided with 64 address bits, the first 60 of which are available addresses for placing the device under test DUT, and the last 4 of which are empty address bits, and only the switch circuit is provided without placing the device under test DUT.

The output end of the addressing circuit is connected to the control end of the Switch circuit of each parallel group of the devices to be tested, and is used for transmitting an address signal to the Switch circuit of each parallel group of the devices to be tested, so that the on-off of the Switch in the Switch circuit is controlled, the corresponding device to be tested DUT in each parallel group of the devices to be tested is selected to be communicated with the test signal line, and parallel test is carried out. In this embodiment, the addressing circuit is implemented by two stages of decoders, which are a row decoder and a column decoder, and can effectively reduce background leakage current. The row decoder is used for selecting a device Block to be tested in the parallel group of the devices to be tested, and the column decoder is used for selecting a device DUT to be tested in the device Block to be tested. In this embodiment, the row decoder is a 3-8 decoder, and the column decoder is a 6-64 decoder.

The input end of the counter is connected with a clock signal CLK bonding pad and a reset signal RN bonding pad, the output end of the counter is connected with the input end of the addressing circuit, and the counter is used for generating address signals. The counter in this embodiment is an asynchronous counter, and is implemented by using positive edge flip-flops and reset signals, and the number of required address bits can be output by adjusting the number of the positive edge flip-flops. In the counter, as shown in fig. 2, the positive edge flip-flops are in a continuous queue, the input terminal of the positive edge flip-flop at the head of the queue is connected to the clock signal CLK pad, the input terminals of the remaining positive edge flip-flops are respectively connected to the Qn terminal of the positive edge flip-flop at the head of the queue, and the Qn terminal of each positive edge flip-flop is connected to the D terminal thereof through a buffer, which is used for holding time; the reset end of each positive edge trigger is connected to a reset signal RN bonding pad and used for low-level reset; the Q end of each positive edge trigger is an output end and is connected with the addressing circuit, and each positive edge trigger outputs a bit address.

As shown in fig. 2, the counter in the present embodiment generates 9-bit addresses, ADDR8, ADDR7, ADDR6 are inputs of 3-8 decoders for selecting a device under test block, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1, ADDR0 are inputs of 6-64 decoders for device under test selection; fig. 4 is a diagram of the clock signal CLK, the reset signal RN, and the address bit signals of the counter.

In this embodiment, the pads include a power access pad, a clock signal CLK pad, a reset signal RN pad, and each test signal pad of the device under test DUT. Fig. 3 is a schematic diagram of a pad configuration when 4 parallel groups of dut are set according to this embodiment, which is described in detail below.

For address generation: a clock signal CLK pad, a reset signal RN pad, an output signal SO pad, a VDD1 pad, and a VSS1 pad; the output signal SO bonding pad is connected to the Q end of a first positive edge trigger in a queue in the counter and used for carrying out least significant bit address verification; the VDD1 pad and VSS1 pad are used to independently power the counter.

For providing 4 sets of parallel excitation/induction signals: VPIN11, IPIN11, VPIN21, IPIN21 pads; VPIN12, IPIN12, VPIN22, IPIN22 pads; VPIN13, IPIN13, VPIN23, IPIN23 pads; VPIN14 pads, IPIN14 pads, VPIN24 pads, IPIN24 pads. The 4 groups of test signal pads correspond to 4 parallel groups of devices to be tested, namely 4 parallel excitation/induction paths, and each path corresponds to 8 device blocks to be tested. For the sake of simplicity, only one group of test signal pads (one group for/sense group) is specifically labeled in fig. 3: VPIN11 pads, IPIN11 pads, VPIN21 pads, IPIN21 pads.

For providing the remaining power: VDD2 pad and VSS2 pad for powering the addressing circuitry and switching circuitry.

In the high-density addressable test chip capable of expanding parallel test in the embodiment, the number of parallel groups of devices to be tested and the number of device blocks to be tested depend on the number of bonding pads; the number of the devices to be tested DUT in one device Block to be tested largely depends on the pad pitch and the size of the pad area, i.e. the size of each device Block to be tested also depends on the pad pitch and the size of the pad area. In the present embodiment, the size of a single pad is 50 μm × 50 μm, and the pad pitch is 100 μm; the pad area one-way width (Y size) was 70 μm, and the size of each device-under-test block was 4.0 μm × 5.9 μm. Setting 7 fixed bonding pads, and every 4 additional bonding pads can expand 1 group of parallel groups of devices to be tested (8 device blocks to be tested), so that the relationship between the number of the parallel groups of the devices to be tested and the number of the bonding pads in this embodiment can refer to the following table.

Number of pads	19	23	27
				Number of parallel groups of devices to be tested	3	4	5
Number of device blocks to be tested	24	32	40
				Number of devices to be tested (maximum)	1440	1920	2400

In this embodiment, the Mx Testable of the high-density addressable test chip is Testable M5, i.e. the Testable layer is not less than M5. For the measurement accuracy: when R = [1, 1Meg ], the measurement error is < 1%; for the leakage current measurement: typically about 1E-9A, freq =10 KHz.

The above embodiments are preferred examples of the present invention, and are not intended to limit the scope of the present invention. It should be understood that the details of these implementations should not be used to limit the invention. In addition, for simplicity of illustration, some structures and components are shown in the drawings in a simplified schematic manner, which is merely schematic and does not limit the design possibilities.

Furthermore, descriptions in the present application as to "first," "previous," "next," etc. are for descriptive purposes only and not for purposes of limitation, and are not to be construed as indicating or implying relative importance or implicit ly indicating a number of the indicated technical features.

The technical solutions can be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or can not be realized, the combination of the technical solutions should be considered to be absent, and is not within the protection scope of the present invention.

Claims

1. A high-density addressable test chip capable of expanding parallel tests is characterized in that: the device comprises a counter, an addressing circuit, a plurality of to-be-tested device parallel groups and a plurality of bonding pads;

the device to be tested parallel group comprises a switch circuit and a plurality of device blocks to be tested, each device block to be tested consists of a plurality of devices to be tested, and each device to be tested is connected to a test signal wire through the switch circuit;

the output end of the addressing circuit is connected to the control end of the switch circuit of the parallel group of the device to be tested and is used for transmitting an address signal to the switch circuit of the parallel group of the device to be tested so as to control the on-off of a switch in the switch circuit, so that the corresponding device to be tested in the parallel group of the device to be tested is selected to be communicated with the test signal line for parallel test;

the bonding pads comprise a power supply access bonding pad, a clock signal bonding pad, a reset signal bonding pad and a plurality of test signal bonding pads; the power supply access pad is used for supplying power to the counter, the addressing circuit and the switch circuit; the test signal bonding pad is connected with a test signal wire;

the input end of the counter is connected with the clock signal bonding pad and the reset signal bonding pad, the output end of the counter is connected with the input end of the addressing circuit, and the counter is used for generating address signals.

2. The high-density addressable test chip capable of expanding parallel tests according to claim 1, wherein: in the parallel group of the devices to be tested, each device to be tested is connected to four test signal lines through four switches respectively, and Kelvin four-end test can be carried out.

3. The high-density addressable test chip capable of expanding parallel tests according to claim 2, wherein: in the parallel group of the devices to be tested, two switches are shared between adjacent devices to be tested.

4. A high-density addressable test chip capable of extended parallel testing according to any of claims 1-3, characterized in that: each device to be tested is connected to an independent group of test signal lines in parallel, namely the parallel groups of the devices to be tested are provided with N groups, correspondingly, the test signal pads are provided with N groups, and the test signal lines are also provided with N groups.

5. The high-density addressable test chip capable of expanding parallel tests according to claim 1, wherein: each device block to be tested is provided with at least two empty address bits for background leakage current detection, address verification and continuous addressing in the device block to be tested; the empty address bit is provided with a switch, and the corresponding device to be tested is not placed in the address bit selected by the switch circuit.

6. The high-density addressable test chip capable of expanding parallel tests according to claim 1, wherein: the addressing circuit is realized by adopting two stages of decoders, namely a row decoder and a column decoder; the row decoder is used for selecting the device blocks to be tested in the parallel group of the devices to be tested, and the column decoder is used for selecting the devices to be tested in the device blocks to be tested.

7. The high-density addressable test chip capable of expanding parallel tests according to claim 1, wherein: the counter is an asynchronous counter.

8. The high-density addressable test chip capable of expanding parallel tests according to claim 7, wherein: the counter comprises a plurality of positive edge triggers and a plurality of buffers, and the number of the positive edge triggers is matched with the number of address bits required by the addressing circuit;

the Qn end of each positive edge trigger is connected to the D end through a buffer; the reset end of each positive edge trigger is connected to a reset signal pad and used for low-level reset; the Q end of each positive edge trigger is an output end and is connected with the addressing circuit, and each positive edge trigger outputs a bit address;

the positive edge triggers are in a continuous queue, the input end of the positive edge trigger positioned at the head of the queue is connected to the clock signal bonding pad, and the input ends of the other positive edge triggers are connected to the Qn end of the positive edge trigger positioned at the front bit of the queue.

9. The high-density addressable test chip capable of expanding parallel tests according to claim 8, wherein: the pads further comprise an output signal pad, and the output signal pad is connected to the Q end of the positive edge trigger positioned at the head of the queue in the counter and used for verifying the least significant bit address.

10. The high-density addressable test chip capable of expanding parallel tests according to claim 1, wherein: the power supply access welding pads are at least provided with two pairs, wherein one pair is used for independently supplying power to the counter, and the other pair is used for supplying power to other circuits except the counter.