CN212784190U

CN212784190U - Monolithic integrated VCSEL chip

Info

Publication number: CN212784190U
Application number: CN202021910589.6U
Authority: CN
Inventors: 郭铭浩; 林珊珊; 王立; 李念宜
Original assignee: Ningbo Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co.,Ltd.
Priority date: 2020-09-04
Filing date: 2020-09-04
Publication date: 2021-03-23
Anticipated expiration: 2030-09-04

Abstract

The present application relates to a monolithically integrated VCSEL chip comprising a first VCSEL chiplet comprising a plurality of first VCSEL units arranged in a first array; and a second VCSEL chiplet monolithically integrated with the first VCSEL chiplet, the second VCSEL chiplet including a plurality of second VCSEL units arranged in a second array; wherein the first VCSEL chiplet and the second VCSEL chiplet structurally share an N-DBR structure. In this way, the monolithically integrated VCSEL chip enables a monolithic integration of multiple VCSEL chips on a wafer level, so that it is able to combine the respective advantages of different VCSEL chips and has a relatively small overall size.

Description

Monolithic integrated VCSEL chip

Technical Field

The present application relates to the field of VCSELs, and more particularly, to a monolithically integrated VCSEL chip, wherein the monolithically integrated VCSEL chip integrates two or more VCSEL sub-chips at a wafer level.

Background

With the development of VCSEL (Vertical-Cavity Surface-Emitting Laser) technology, VCSEL chips adapted to different application scenarios, such as TOF (Time of Flight) VCSEL chips, structured light VCSEL chips, etc., are gradually emerging in the market.

Different types of VCSEL chips have different performance characteristics, and the structured light VCSEL chip has the advantages of high light transmittance and low energy consumption, is easily influenced by the environment and is only suitable for short-distance application scenes; the TOFVCSEL chip has the advantages of small influence on environment and the like, but the measurement accuracy is poor and the power consumption is high.

It is a current trend to integrate different types of VCSEL chips with terminal devices, for example, different types of VCSEL chips are placed on different sides of a smart phone to serve as a front VCSEL chip of a front camera module and a rear VCSEL chip of a rear camera module to achieve different functional configurations.

Therefore, how to integrally configure two or more VCSEL chips has become a very important technical issue.

Disclosure of Invention

An advantage of the present application is to provide a monolithically integrated VCSEL chip, wherein the monolithically integrated VCSEL chip enables integration of two or more VCSEL sub-chips on the same single wafer at the wafer level.

Another advantage of the present application is to provide a monolithically integrated VCSEL chip, wherein the monolithically integrated VCSEL chip is capable of integrating at least two VCSEL chips of different types, such that the monolithically integrated VCSEL chip combines characteristics of the different types of VCSEL chips at the same time.

Another advantage of the present application is to provide a monolithically integrated VCSEL chip, functional red, having a relatively small thickness dimension overall.

Another advantage of the present application is to provide a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip can selectively activate different types of chips to operate based on different application scenarios to expand application scenario compatibility of the monolithic integrated VCSEL chip.

Another advantage of the present application is to provide a monolithically integrated VCSEL chip wherein at least two VCSEL sub-chips are monolithically integrated at the wafer level by means of a common N-DBR layer.

To achieve at least one of the above technical advantages, there is provided a monolithically integrated VCSEL chip comprising:

a first VCSEL chiplet including a plurality of first VCSEL units arranged in a first array; and

a second VCSEL chiplet monolithically integrated with the first VCSEL chiplet, the second VCSEL chiplet including a plurality of second VCSEL units arranged in a second array;

wherein laser light generated by each of the first VCSEL units in the first VCSEL chiplet exits a first side of the VCSEL chip and laser light generated by each of the second VCSEL units in the second VCSEL chiplet exits a second side of the VCSE chip opposite to the first side;

wherein the first VCSEL chiplet and the second VCSEL chiplet structurally share an N-DBR structure.

In a monolithically integrated VCSEL chip according to the present application, the first VCSEL unit and the second VCSEL unit each comprise: the semiconductor device comprises a substrate, an N-DBR layer formed on the substrate, an active region located above the N-DBR layer, an oxidation limiting layer used for limiting a light emitting aperture, a P-DBR layer located above the active region, and a positive electrode and a negative electrode used for conducting the active region, wherein an electric isolation region is arranged between each first VCSEL unit and each second VCSEL unit, the N-DBR layer of each first VCSEL unit and the N-DBR layer of each second VCSEL unit are coupled with each other to form the N-DBR structure shared by a first VCSEL sub-chip and a second VCSEL sub-chip.

In a monolithically integrated VCSEL chip according to the present application, the first VCSEL units of the first VCSEL chiplet and the second VCSEL units of the second VCSEL chiplet are formed on the opposite first and second sides of the VCSEL chip in an alternating manner with each other.

In a monolithically integrated VCSEL chip according to the present application, the first VCSEL units of the first VCSEL chiplet and the second VCSEL units of the second VCSEL chiplet are symmetrically formed on the opposite first and second sides of the VCSEL chip.

In a monolithically integrated VCSEL chip according to the present application, the second VCSEL units of the second chiplet are formed consecutively between the first VCSEL units of the first chiplet and the first VCSEL units of the first VCSEL chiplet and the second VCSEL units of the second VCSEL chiplet are formed on the opposite first and second sides of the VCSEL chip.

In the monolithically integrated VCSEL chip according to the present application, in each of the first VCSEL units, a reflectivity of the N-DBR layer is higher than a reflectivity of the P-DBR layer such that laser light generated by the first VCSEL unit exits from a first side of the VCSEL chip, and in each of the second VCSEL units, the reflectivity of the N-DBR layer is lower than the reflectivity of the P-DBR layer such that laser light generated by the first VCSEL unit exits from a second side of the VCSEL chip opposite to the first side.

In the monolithically integrated VCSEL chip according to the present application, in each of the first VCSEL units, the number of layers of the P-DBR layer is greater than the number of layers of the N-DBR; in each of the second VCSEL units, the number of layers of the P-DBR layer is smaller than the number of layers of the N-DBR.

In the monolithically integrated VCSEL chip according to the present application, in each of the first VCSEL units, the number of layers of the P-DBR layer ranges from 15 layers to 45 layers, and the number of layers of the N-DBR layer ranges from 15 layers to 45 layers; in each of the second VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR layer ranges from 15 to 45 layers.

In the monolithically integrated VCSEL chip according to the present application, in each of the first VCSEL units, the reflectivity of the N-DBR layer is higher than the reflectivity of the P-DBR layer such that laser light generated by the first VCSEL unit exits from a first side of the VCSEL chip, and in each of the second VCSEL units, the reflectivity of the N-DBR layer is higher than the reflectivity of the P-DBR layer such that laser light generated by the first VCSEL unit exits from a second side of the VCSEL chip opposite to the first side.

In the monolithically integrated VCSEL chip according to the present application, in each of the first VCSEL units, the number of layers of the N-DBR layer is greater than the number of layers of the P-DBR layer; in each of the second VCSEL units, the number of N-DBR layers is greater than the number of P-DBR layers.

In the monolithically integrated VCSEL chip according to the present application, a negative electrode of each of the first VCSEL units and a negative electrode of each of the second VCSEL units are coupled to each other to form a negative electrode conductive layer.

In the monolithically integrated VCSEL chip according to the present application, the negative conductive layer is formed within the N-DBR structure.

In a monolithically integrated VCSEL chip according to the present application, a positive electrode of each of the first VCSEL unit and each of the second VCSEL unit is formed at the first side of the VCSEL unit.

In a monolithically integrated VCSEL chip according to the present application, a positive electrode of each of the first VCSEL unit and each of the second VCSEL unit is formed at the first side of the VCSEL unit; the negative pole of each of the first VCSEL unit and each of the second VCSEL unit is formed on the second side of the VCSEL chip.

In the monolithically integrated VCSEL chip according to the present application, the cathodes of the second VCSEL units are arranged alternately, and the laser light emitted from each of the second VCSEL units is suitable for being emitted from a gap formed by two adjacent cathodes.

In the monolithically integrated VCSEL chip according to the present application, the cathode of each second VCSEL unit is made of a light permeable, electrically conductive material.

In a monolithically integrated VCSEL chip according to the present application, the cathodes of at least part of the second VCSEL units are coupled to each other to form a cathode conductive layer.

In the monolithically integrated VCSEL chip according to the present application, the first VCSEL sub-chip and the second VCSEL sub-chip are selected from any one of a TOFVCSEL chip and a structured light VCSEL chip.

In the monolithically integrated VCSEL chip according to the present application, the first VCSEL chiplet and the second VCSEL chiplet are of the same type of VCSEL chip and have different optical powers.

In the monolithically integrated VCSEL chip according to the present application, the width of the electrical isolation region ranges from 1nm to 5 mm.

In a monolithically integrated VCSEL chip according to the present application, the electrically isolated region has a width in the range of 1um to 10 um.

Further advantages and advantages of the present application will become apparent from an understanding of the ensuing description and drawings.

These and other advantages, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the claims.

Drawings

Fig. 1 illustrates a conventional schematic diagram of two VCSEL chips applied to a terminal device.

Fig. 2 illustrates another schematic diagram of a conventional application of two VCSEL chips to a terminal device.

Figure 3 illustrates a cross-sectional schematic view of a monolithically integrated VCSEL chip in accordance with an embodiment of the present application.

Figure 4 illustrates a schematic diagram of individual VCSEL units in the monolithically integrated VCSEL chip in accordance with an embodiment of the present application.

Figure 5 illustrates a cross-sectional view of another example of the integrated VCSEL chip in accordance with an embodiment of the present application.

Figure 6 illustrates a cross-sectional view of yet another example of the integrated VCSEL chip in accordance with an embodiment of the present application.

Figure 7 illustrates a cross-sectional view of yet another example of the integrated VCSEL chip in accordance with an embodiment of the present application.

Figure 8 illustrates a cross-sectional view of yet another example of the integrated VCSEL chip in accordance with an embodiment of the present application.

Detailed Description

The following description is presented to disclose the application and to enable any person skilled in the art to practice the application. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The underlying principles of the application, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the application.

It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or components must be in a particular orientation, constructed and operated in a particular orientation, and thus the above terms are not to be considered limiting of the present application.

It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.

Summary of the application

As described above, it is a current trend to integrate different types of VCSEL chips with a terminal device, and therefore, how to combine the advantages of different types of VCSEL chips and optimize the respective defects of different VCSEL chips has become a very important technical problem.

There are various technical solutions for combining different VCSEL chips, which commonly include: the two-side light emitting method comprises two types of light emitting from the front side and the back side and light emitting from the same side, wherein the two VCSEL chips are arranged in a back-to-back mode, and the laser emitting directions of the two VCSEL chips are opposite. Fig. 1 and 2 illustrate two examples of such an arrangement.

As shown in fig. 1, in this solution, two VCSEL chips are placed in a staggered and back-to-back manner, and although this solution can integrate the advantages of two VCSEL chips to a certain extent, this solution occupies too large area, i.e. occupies large volume of the terminal device, which is not in line with the current trend of miniaturization and thinning of the terminal device. As shown in fig. 2, in this solution, two VCSEL chips are aligned and arranged back to back, and although this solution can integrate the advantages of two VCSEL chips to a certain extent, the thickness dimension of this solution is still large, i.e. the occupied volume of the terminal device is still large, which is not in line with the current trend of miniaturization and thinning of the terminal device.

The term "emitting light from the same side" refers to arranging the light emitting surfaces of the two VCSEL chips on the same plane, for example, arranging the two VCSEL chips in parallel (not shown), which occupies a large area and is not in line with the current trend of miniaturization and thinning of the terminal device.

Moreover, through the existing technical schemes of 'light emitting from the same side' and 'light emitting from the front side and the rear side', the following can be found: no matter the scheme is the "same-side light-emitting" scheme or the "front-back two-side light-emitting" scheme, there is no structural association between different VCSEL chips, that is, in the existing integrated application scheme of VCSEL chips, different VCSEL chips are only placed at different positions of the terminal device, but they are still operated and controlled independently in nature.

In view of the above technical problems, the basic idea of the present application is to realize monolithic integration of multiple VCSEL chips on a wafer level, so that the finally formed monolithic integrated VCSEL chips can combine the respective advantages of different VCSEL chips and have a relatively small overall size.

In view of this, the present application provides a monolithically integrated VCSEL chip comprising a first VCSEL chiplet comprising a plurality of first VCSEL units arranged in a first array; and a second VCSEL chiplet monolithically integrated with the first VCSEL chiplet, the second VCSEL chiplet including a plurality of second VCSEL units arranged in a second array; wherein laser light generated by each of the first VCSEL units in the first VCSEL chiplet exits a first side of the VCSEL chip and laser light generated by each of the second VCSEL units in the second VCSEL chiplet exits a second side of the VCSE chip opposite to the first side; wherein the first VCSEL chiplet and the second VCSEL chiplet structurally share an N-DBR structure. In this way, the monolithically integrated VCSEL chip enables a monolithic integration of multiple VCSEL chips on a wafer level, so that it is able to combine the respective advantages of different VCSEL chips and has a relatively small overall size.

Having described the general principles of the present application, various non-limiting embodiments of the present application will now be described with reference to the accompanying drawings.

Example 1

The inventor of the application researches the consistency of different VCSEL chips on a wafer level structure, and conceives the technical scheme of carrying out single-chip integration on the VCSEL chips of different models on the wafer level, so that the formed single-chip integrated VCSEL chip can have the advantages of different VCSEL chips, has smaller overall thickness and size, and meets the development trend of thinning of current terminal equipment. Here, in the embodiments of the present application, different VCSEL chips are different types of chips, which include chips of the same type but different parameters (e.g., the same type but different power) and different types of chips, and the types of VCSEL chips include, but are not limited to, TOFVCSEL chips and structured light VCSEL chips.

The monolithic integrated VCSEL chip of the embodiment of the present application is described below with the monolithic integrated VCSEL chip monolithically integrating a first VCSEL sub-chip and a second VCSEL sub-chip, that is, with the monolithic integrated VCSEL chip integrating two different types of sub-chips as an example.

Figure 3 illustrates a cross-sectional schematic view of a monolithically integrated VCSEL chip in accordance with an embodiment of the present application. As shown in fig. 3, the monolithically integrated VCSEL chip includes a first VCSEL sub-chip 10 and a second VCSEL sub-chip 20 monolithically integrated with the first VCSEL sub-chip 10, wherein the first VCSEL sub-chip 10 includes a plurality of first VCSEL units 100 arranged in a first array, the second VCSEL sub-chip 20 includes a plurality of second VCSEL units 200 arranged in a second array, and an electrical isolation area 300 is disposed between each of the first VCSEL units 100 and each of the second VCSEL units 200. In the embodiment of the present application, the laser emitting direction of the first VCSEL sub-chip 10 is opposite to the laser emitting direction of the second VCSEL sub-chip 20, for example, in a specific example of the present application, the laser generated by each first VCSEL unit 100 in the first VCSEL sub-chip 10 is emitted from a first side a of the VCSEL chip, and the laser generated by each second VCSEL unit 200 in the second VCSEL sub-chip 20 is emitted from a second side B of the VCSE chip opposite to the first side a.

In particular, in the embodiment of the present application, as shown in fig. 3, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 structurally share the N-DBR structure 120, and in this way, the monolithically integrated VCSEL chip realizes that the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 are monolithically integrated on a wafer level, so that the monolithically integrated VCSEL sub-chip can combine the advantages of the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20, and has a relatively small overall size.

To illustrate how the first VCSEL sub-chip 10 and the second VCSEL are monolithically integrated at the wafer level, the first VCSEL unit 100 and the second VCSEL unit 200 and the light extraction principle thereof are explained.

Figure 4 illustrates a schematic diagram of individual VCSEL units in the monolithically integrated VCSEL chip in accordance with an embodiment of the present application. As shown in fig. 4, each of the first and second VCSEL units 100 and 200 (the first VCSEL unit 100 and the second VCSEL unit 200 have the same structural configuration) includes a substrate 11 (in some embodiments, the VCSEL unit may not be provided with the substrate 11), an N-DBR layer 12 formed on the substrate 11, an active region 13 located above the N-DBR layer 12, an oxidation limiting layer 14 for limiting a light emission aperture, a P-DBR layer 15 located above the active region 13, and an anode 16 and a cathode 17 for conducting the active region 13, wherein the active region 13 is sandwiched between the P-DBR layer 15 and the N-DBR layer 12 to form a resonant cavity between the P-DBR layer 15 and the N-DBR layer 12.

In operation, the first and second VCSEL units 100,200 can achieve laser excitation by satisfying the following two conditions: (1) particle number inversion process: in the case that the population inversion exists in the active region 13, so that the gain provided by the laser medium is enough to exceed the loss, when current is injected through the cathode 17 and the anode 16, the light intensity will continuously increase, and when electrons at the bottom of the conduction band of the high energy state transition to be in the low energy band, the amplification process is repeated as light with a specific wavelength is reflected back and forth between the P-DBR layer 15 and the N-DBR layer 12, so as to form laser light; (2) a resonant cavity: the composition of the P-DBR layer 15 and the N-DBR layer 12 and the gain medium is one of the main conditions for generating laser light, and the main role of the resonant cavity is to form multiple optical energy feedbacks to form laser oscillation when light generated in the active region 13 is reflected back and forth between the P-DBR 06 and the N-DBR 03. Finally, the laser light projected by the first and second VCSEL units 100,200 generates a set of interference fringes in space.

It should be noted that in the embodiments of the present application, the selection of the materials of the layers of the first and second VCSEL units 100,200 is not limited to the present application, for example, the substrate 11 may include, but is not limited to, a silicon substrate 11, a sapphire substrate 11, a potassium arsenide substrate 11, etc.; the materials of the P-DBR layer 15 and the N-DBR layer 12 include, but are not limited to: InGaAsP/InP, AlGaInAs/AlInAs, AlGaAsSb/AlAsSb, GaAs/AlGaAs, Si/MgO, and Si/Al2O3, etc.

In particular, as shown in fig. 3, in the embodiment of the present application, the N-DBR layer 12 of each of the first VCSEL units 100 and the N-DBR layer 12 of each of the second VCSEL units 200 are coupled to each other to form the N-DBR structure 120 common to the first VCSEL sub-chip and the second VCSEL sub-chip 20. That is, the N-DBR layer 12 of each of the first VCSEL units 100 and the N-DBR layer 12 of each of the second VCSEL units 200 are coupled to each other at a wafer-level structural layer to form a layer structure, i.e., the N-DBR structure 120. Alternatively, the N-DBR structure 120 is not etched or etched without being cut during the fabrication of the monolithically integrated VCSEL chip, so that the N-DBR structure 120 layers remain as a complete layer structure after the monolithically integrated VCSEL chip is formed.

Further, as shown in fig. 3, in the embodiment of the present application, the first VCSEL unit 100 of the first VCSEL sub-chip 10 and the second VCSEL unit 200 of the second VCSEL sub-chip 20 are symmetrically formed on the opposite first side a and second side B of the VCSEL chip. Thus, when the monolithically integrated VCSEL chip is turned on, the first VCSEL chiplet 10 and the second VCSEL chiplet 20 are capable of lasing from a first side a and a second side B, i.e. the monolithically integrated VCSEL chip is capable of lasing from its opposite first and second sides a, B simultaneously.

In particular, in the embodiment of the present application, in each of the first VCSEL units 100, the reflectivity of the N-DBR layer 12 is higher than the reflectivity of the P-DBR layer 15, so that the laser light generated from the first VCSEL unit 100 exits from the first side a of the VCSEL chip, and in each of the second VCSEL units 200, the reflectivity of the N-DBR layer 12 is higher than the reflectivity of the P-DBR layer, so that the laser light generated from the first VCSEL unit 100 exits from the second side B of the VCSEL chip opposite to the first side a.

It should be understood that the reflectivities of the N-DBR layer 12 and the P-DBR layer 15 of the first VCSEL unit 100 and the second VCSEL unit 200 are determined by the number of layers of the N-DBR layer 12 and the P-DBR layer 15. Specifically, in the present embodiment, in each of the first VCSEL units 100, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR; in each of the second VCSEL units 200, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR.

In the embodiment of the present application, in each of the first VCSEL units 100, the number of layers of the P-DBR layer 15 ranges from 15 to 45, and the number of layers of the N-DBR layer ranges from 15 to 45; in each of the second VCSEL units 200, the number of layers of the P-DBR layer 15 ranges from 15 to 45, and the number of layers of the N-DBR layer ranges from 15 to 45. Here, one P-DBR structure is composed of a pair of high-aluminum material and low-aluminum material, and one N-DBR structure is composed of a pair of high-aluminum material and low-aluminum material.

Further, as shown in fig. 3 and 4, in the embodiment of the present application, the positive electrodes 16 of the first VCSEL units 100 of the first VCSEL sub-chip 10 are respectively formed on the surface of the first side a of the monolithically integrated VCSEL chip; the anodes 16 of the second VCSEL units 200 of the second VCSEL chiplet 20 are formed over the surface of the second side B of the monolithically integrated VCSEL chip, respectively. That is, in the embodiment of the present application, the anodes of the monolithically integrated VCSEL chips are formed on the upper and lower side surfaces thereof, respectively. Further, as shown in fig. 3 and 4, in the present embodiment, the negative electrode 17 of each first VCSEL unit 100 of the first VCSEL sub-chip 10 and the negative electrode 17 of each second VCSEL unit 200 of the second VCSEL sub-chip 20 are coupled to each other to form a negative conductive layer 170, that is, in the present embodiment, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share the negative conductive layer 170, or the monolithically integrated VCSEL chips share a cathode.

In particular, in the present embodiment, the negative conductive layer 170 is formed within the N-DBR structure 120. Also, as shown in fig. 3, in the embodiment of the present application, the negative conductive layer 170 is located at the middle of the monolithic integrated VCSEL chip, i.e., the cathode of the monolithic integrated VCSEL chip is located at the middle thereof.

It should be noted that, in the embodiment of the present application, the anodes 16 of the first VCSEL units 100 of at least a part of the first VCSEL sub-chip 10 can be electrically connected to each other to form a conductive layer of the anode 16, and in this way, the first VCSEL sub-chip 10 is controlled to perform the divisional lighting, wherein the arrangement of the divisional lighting is determined by the pattern configuration of the conductive layer of the anode 16. Similarly, in the embodiment of the present application, the anodes 16 of the second VCSEL units 200 of at least a part of the second VCSEL sub-chips 20 can be electrically connected to each other to form a positive conductive layer, and in this way, the second VCSEL sub-chips 20 are controlled to perform the divisional lighting, wherein the arrangement of the divisional lighting is determined by the pattern configuration of the positive conductive layer.

It should be understood that, in the embodiment of the present application, by properly arranging the positive electrode 16 and the negative electrode 17 of the first VCSEL sub-chip 10 and the positive electrode 16 and the negative electrode 17 of the second VCSEL sub-chip 20, the monolithic integrated VCSEL chip can realize different lighting modes, so as to expand the application possibilities of the monolithic integrated VCSEL chip.

Further, in the present embodiment, the first VCSEL sub-chip 10 is implemented as a TOFVCSEL chip, which includes a plurality of first VCSEL units 100 arranged in a regular array; the second VCSEL sub-chip 20 is implemented as a structured light VCSEL chip comprising a plurality of second VCSEL units 200 arranged in an array in a specific coding. That is, in the example illustrated in fig. 3, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 are different types of VCSEL chips, so the monolithic integrated VCSEL chip can selectively activate the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 based on the requirements of different application scenarios, for example, in an application scenario requiring higher measurement accuracy, the second VCSEL sub-chip 20 can be activated and the first VCSEL sub-chip 10 can be deactivated; when the measuring distance is long, the first VCSEL chiplet 10 can be turned on and the second VCSEL chiplet 20 can be turned off.

That is, the monolithically integrated VCSEL chip can combine performance advantages of different types of VCSEL chips, and since the first sub-chip and the second sub-chip are monolithically integrated at a wafer level, the monolithically integrated VCSEL chip has advantages in both an overall height dimension and a horizontal dimension thereof, that is, the overall height dimension is small and an occupied area in the horizontal direction is relatively small.

It should be noted that, in the embodiment of the present application, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 may also be implemented as VCSEL chips of the same type but with different parameters (e.g., different optical powers), and thus, the present application is not limited thereto.

In summary, the monolithically integrated VCSEL chip according to the embodiments of the present application is illustrated, which implements a monolithic integration of multiple VCSEL chips on a wafer level, so that it can combine the advantages of different VCSEL chips and has a relatively small overall size.

Also, the monolithically integrated VCSEL chip as described above may be fabricated through a fabrication scheme as described below.

First, an epitaxial structure including a substrate 11 structure, an N-DBR layer 12, an active region 13 structure, and a P-DRB structure is formed through an MOCVD process (Metal-organic Chemical Vapor Deposition process) or other Metal growth processes; then, processing the epitaxial structure through photoetching or other etching processes to form a mesa structure; next, an oxidation process is performed to form an oxidation limiting layer 14 and fill the gap between the mesa structures with a transparent non-conductive material to form the electrical isolation region 300, specifically, in the embodiment of the present application, the width of the electrical isolation region 300 ranges from 1nm to 5mm, and preferably, the width of the electrical isolation region 300 ranges from 1um to 10 um; then, forming a positive electrode 16 on the mesa structure by an evaporation process to form the first VCSEL sub-chip 10; then, an epitaxial structure is formed on the N-DBR structure 120 of the first VCSEL sub-chip 10 by a Metal-organic Chemical Vapor Deposition (MOCVD) process or other Metal growth processes; next, the second VCSEL sub-chip 20 is fabricated by the process as described above; the negative conductive layer 170 is then formed in the N-DBR structure 120 to form the monolithically integrated VCSEL chip.

Example 2

As shown in fig. 5, in this example, the monolithically integrated VCSEL chip comprises a first VCSEL sub-chip 10 and a second VCSEL sub-chip 20 monolithically integrated with the first VCSEL sub-chip 10, the first VCSEL sub-chip 10 comprising a plurality of first VCSEL units 100 arranged in a first array, and the second VCSEL sub-chip 20 comprising a plurality of second VCSEL units 200 arranged in a second array. In particular, the first VCSEL chiplet 10 and the second VCSEL chiplet 20 structurally share an N-DBR structure 120.

In this example, the laser light generated by each of the first VCSEL units 100 in the first VCSEL chiplet 10 exits from a first side a of the VCSEL chip, and the laser light generated by each of the second VCSEL units 200 in the second VCSEL chiplet 20 exits from a second side B of the VCSE chip opposite to the first side a.

In contrast to the above embodiment 1, in the embodiment of the present application, the first VCSEL units 100 of the first VCSEL sub-chip 10 and the second VCSEL units 200 of the second VCSEL sub-chip 20 are formed on the first side a and the second side B of the VCSEL chip, which are opposite to each other, in an alternating manner. Specifically, as shown in fig. 5, in this example, the first VCSEL sub-chip 10 is formed on a first side a of the monolithically integrated VCSEL chip, and the second VCSEL sub-chip 20 is formed on a second side B of the monolithically integrated VCSEL chip, wherein one second VCSEL unit 200 is sandwiched between every two first VCSEL units 100, and one first VCSEL unit 100 is sandwiched between every two second VCSEL units 200, in such a way that the first VCSEL units 100 of the first VCSEL sub-chip 10 and the second VCSEL units 200 of the second VCSEL sub-chip 20 are formed on the first side a and the second side B of the VCSEL chip in an alternating manner. Thus, when the monolithically integrated VCSEL chip is turned on, the first VCSEL chiplet 10 and the second VCSEL chiplet 20 are capable of lasing from a first side a and a second side B, i.e. the monolithically integrated VCSEL chip is capable of lasing from its opposite first and second sides a, B simultaneously.

Further, as shown in fig. 4 and 5, in this embodiment, the N-DBR layer 12 of each of the first VCSEL units 100 is coupled to have a first layer structure, the N-DBR layer 12 of each of the second VCSEL units 200 has a second layer structure, and the first layer structure and the second layer structure are the same layer structure (i.e., the N-DBR structure 120), that is, in this example, the N-DBR layer 12 of each of the first VCSEL units 100 and the N-DBR layer 12 of each of the second VCSEL units 200 share the N-DBR structure 120 at a wafer level of structure. Alternatively, the N-DBR structure 120 is not etched or etched without being cut during the fabrication of the monolithically integrated VCSEL chip, so that the N-DBR structure 120 layers remain as a complete layer structure after the monolithically integrated VCSEL chip is formed.

In particular, in the embodiment of the present application, as shown in fig. 4, in each of the first VCSEL units 100, the reflectivity of the N-DBR layer 12 is higher than the reflectivity of the P-DBR layer 15, so that the laser light generated by the first VCSEL unit 100 is emitted from a first side a of the VCSEL chip (as shown in fig. 5), and in each of the second VCSEL units 200, the reflectivity of the N-DBR layer 12 is lower than the reflectivity of the P-DBR layer, so that the laser light generated by the first VCSEL unit 100 is emitted from a second side B of the VCSEL chip opposite to the first side a (as shown in fig. 5).

It should be understood that the reflectivities of the N-DBR layer 12 and the P-DBR layer 15 of the first VCSEL unit 100 and the second VCSEL unit 200 are determined by the number of layers of the N-DBR layer 12 and the P-DBR layer 15. Specifically, in the present embodiment, in each of the first VCSEL units 100, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR; in each of the second VCSEL units 200, the number of layers of the N-DBR layer 12 is smaller than the number of layers of the P-DBR.

Further, as shown in fig. 4 and 5, in this example, the positive electrodes 16 of the first VCSEL units 100 of the first VCSEL chiplet 10 are formed on the surface of the first side a of the monolithically integrated VCSEL chip, respectively; the anodes 16 of the second VCSEL units 200 of the second VCSEL chiplet 20 are formed over the surface of the first side a of the monolithically integrated VCSEL chip. That is, in the embodiment of the present application, the anode of the monolithically integrated VCSEL chip is formed on one side surface thereof. Further, as shown in fig. 4 and 5, in the present embodiment, the negative electrode 17 of each first VCSEL unit 100 of the first VCSEL sub-chip 10 and the negative electrode 17 of each second VCSEL unit 200 of the second VCSEL sub-chip 20 are coupled to form a negative conductive layer 170, that is, in the present embodiment, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share the negative conductive layer 170, or the monolithically integrated VCSEL chips share a cathode.

As shown in fig. 5, in this example, the negative conductive layer 170 is formed within the N-DBR structure 120. More specifically, the negative conductive layer 170 is located in the middle of the monolithically integrated VCSEL chip, i.e., the cathode of the monolithically integrated VCSEL chip is located in the middle thereof.

Further, in this example, the first VCSEL chiplet 10 and the second VCSEL chiplet 20 are different types of VCSEL chiplets; alternatively, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 may be implemented as VCSEL chips of the same type but with different parameters (e.g., different optical powers), which is not limited in this application.

First, an epitaxial structure including a substrate 11 structure, an N-DBR layer 12, an active region 13 structure, and a P-DRB structure is formed through an MOCVD process (Metal-organic Chemical Vapor Deposition process) or other Metal growth processes; then, processing the epitaxial structure through photoetching or other etching processes to form a mesa structure; next, an oxidation process is performed to form an oxidation limiting layer 14 and fill the gap between the mesa structures with a transparent non-conductive material to form the electrical isolation region 300, specifically, in the embodiment of the present application, the width of the electrical isolation region 300 ranges from 1nm to 5mm, and preferably, the width of the electrical isolation region 300 ranges from 1um to 10 um; then, the N-DBR structure 120 of the epitaxial structure is further processed by photolithography or other etching process to partially reduce the number of layers of the N-DBR structure 120 at specific locations, and the etched regions of the N-DBR structure 120 are also filled with a transparent non-conductive material to form the electrically isolated region 300; then, forming a positive electrode 16 on the mesa structure by an evaporation process; next, the negative conductive layer 170 is formed in the N-DBR structure 120 to fabricate the monolithically integrated VCSEL chip.

Example 3

As shown in fig. 6, in this example, the monolithically integrated VCSEL chip comprises a first VCSEL sub-chip 10 and a second VCSEL sub-chip 20 monolithically integrated with the first VCSEL sub-chip 10, the first VCSEL sub-chip 10 comprising a plurality of first VCSEL units 100 arranged in a first array, and the second VCSEL sub-chip 20 comprising a plurality of second VCSEL units 200 arranged in a second array. In particular, the first VCSEL chiplet 10 and the second VCSEL chiplet 20 structurally share an N-DBR structure 120.

What is different from the above embodiment 1 is that, in the embodiment of the present application, the second VCSEL units 200 of the second sub-chip are continuously formed between the first VCSEL units 100 of the first sub-chip, and the first VCSEL units 100 of the first VCSEL sub-chip 10 and the second VCSEL units 200 of the second VCSEL sub-chip 20 are formed on the first side a and the second side B of the VCSEL chip, which are opposite to each other. Specifically, as shown in fig. 6, in this example, the first VCSEL sub-chip 10 is formed on a first side a of the monolithically integrated VCSEL chip, and the second VCSEL sub-chip 20 is formed on a second side B of the monolithically integrated VCSEL chip, wherein the second VCSEL units 200 of the second VCSEL sub-chip 20 are continuously formed on the second side B, and the arrangement positions of the second VCSEL units 200 are located between the first VCSEL units 100 of the first sub-chip, that is, the arrangement positions of the second VCSEL units 200 are sandwiched between the first VCSEL units 100 of the first sub-chip.

Accordingly, when the monolithically integrated VCSEL chip is turned on, the first VCSEL chiplet 10 and the second VCSEL chiplet 20 are capable of lasing from a first side a and a second side B, i.e. the monolithically integrated VCSEL chip is capable of lasing from its opposite first and second sides a, B simultaneously.

Further, as shown in fig. 4 and 6, in this embodiment, the N-DBR layer 12 of each of the first VCSEL units 100 is coupled to have a first layer structure, the N-DBR layer 12 of each of the second VCSEL units 200 has a second layer structure, and the first layer structure and the second layer structure are the same layer structure (i.e., the N-DBR structure 120), that is, in this example, the N-DBR layer 12 of each of the first VCSEL units 100 and the N-DBR layer 12 of each of the second VCSEL units 200 share the N-DBR structure 120 at a wafer level of structure. Alternatively, the N-DBR structure 120 is not etched or etched without being cut during the fabrication of the monolithically integrated VCSEL chip, so that the N-DBR structure 120 layers remain as a complete layer structure after the monolithically integrated VCSEL chip is formed.

In particular, in the embodiment of the present application, as shown in fig. 4, in each of the first VCSEL units 100, the reflectivity of the N-DBR layer 12 is higher than the reflectivity of the P-DBR layer 15, so that the laser light generated by the first VCSEL unit 100 is emitted from a first side a of the VCSEL chip (as shown in fig. 6), and in each of the second VCSEL units 200, the reflectivity of the N-DBR layer 12 is lower than the reflectivity of the P-DBR layer, so that the laser light generated by the first VCSEL unit 100 is emitted from a second side B of the VCSEL chip opposite to the first side a (as shown in fig. 6).

It should be understood that, as shown in fig. 4, the reflectivities of the N-DBR layer 12 and the P-DBR layer 15 of the first VCSEL unit 100 and the second VCSEL unit 200 are determined by the number of layers of the N-DBR layer 12 and the P-DBR layer 15. Specifically, in the present embodiment, in each of the first VCSEL units 100, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR; in each of the second VCSEL units 200, the number of layers of the N-DBR layer 12 is smaller than the number of layers of the P-DBR.

In the embodiment of the present application, in each of the first VCSEL units 100, the number of layers of the P-DBR layer 15 ranges from 15 to 45, and the number of layers of the N-DBR layer ranges from 15 to 45; in each of the second VCSEL units 200, the number of layers of the P-DBR layer 15 ranges from 15 to 45, and the number of layers of the N-DBR layer ranges from 15 to 45.

Further, as shown in fig. 4 and 6, in this example, the positive electrodes 16 of the first VCSEL units 100 of the first VCSEL chiplet 10 are formed on the surface of the first side a of the monolithically integrated VCSEL chip, respectively; the anodes 16 of the second VCSEL units 200 of the second VCSEL chiplet 20 are formed over the surface of the first side a of the monolithically integrated VCSEL chip. That is, in the embodiment of the present application, the anode of the monolithically integrated VCSEL chip is formed on one side surface thereof. Further, as shown in fig. 4 and 6, in the present embodiment, the negative electrode 17 of each first VCSEL unit 100 of the first VCSEL sub-chip 10 and the negative electrode 17 of each second VCSEL unit 200 of the second VCSEL sub-chip 20 are coupled to form a negative conductive layer 170, that is, in the present embodiment, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share the negative conductive layer 170, or the monolithically integrated VCSEL chips share a cathode.

As shown in fig. 6, in this example, the negative conductive layer 170 is formed within the N-DBR structure 120. More specifically, the negative conductive layer 170 is located in the middle of the monolithically integrated VCSEL chip, i.e., the cathode of the monolithically integrated VCSEL chip is located in the middle thereof.

Figure 7 illustrates a cross-sectional view of yet another example of the integrated VCSEL chip in accordance with an embodiment of the present application. The example illustrated in fig. 7 is a variant of the embodiment of fig. 6. As shown in fig. 7, in this example, the cathode 17 of each of the first VCSEL unit 100 and the second VCSEL unit 200 is formed on the second side B of the VCSEL chip, and the cathodes 17 of each of the first VCSEL unit 100 and the second VCSEL unit 200 are coupled to each other by a cathode conductive layer 170, wherein the cathode conductive layer 170 is made of a light-permeable conductive material.

It is worth mentioning that in the example as illustrated in fig. 8, it is only necessary that the cathode 17 corresponding to the second VCSEL sub-chip 20 is able to allow the laser light generated by the second VCSEL sub-chip 20 to pass through, i.e. in this example, at least the cathode 17 corresponding to the second VCSEL sub-chip 20 is made of a light-permeable conductive material. In a specific implementation, the light-permeable material is selected from any one of ITO (indium tin oxide), ATO (antimony tin oxide), FTO (antimony tin oxide), AZO (aluminum zinc oxide), GZO (gallium zinc oxide) IZO (indium zinc oxide).

Fig. 8 illustrates a cross-sectional view of yet another example of the integrated VCSEL chip in accordance with an embodiment of the present application, wherein the example illustrated in fig. 8 is a modified implementation of fig. 7. As shown in fig. 8, in this example, the cathode 17 of each of the first VCSEL unit 100 and the second VCSEL unit 200 is formed on the second side B of the VCSEL chip. The cathodes 17 of the second VCSEL units 200 are alternately arranged, and the laser light emitted from each second VCSEL unit 200 is suitable for being emitted from a gap formed between two adjacent cathodes 17.

First, an epitaxial structure including a substrate 11 structure, an N-DBR layer 12, an active region 13 structure, and a P-DRB structure is formed through an MOCVD process (Metal-organic Chemical Vapor Deposition process) or other Metal growth processes; then, processing the epitaxial structure through photoetching or other etching processes to form a mesa structure; next, an oxidation process is performed to form an oxidation limiting layer 14 and fill the gap between the mesa structures with a transparent non-conductive material to form the electrical isolation region 300, wherein the transparent non-conductive material is selected from silicon nitride, silicon oxide, and the like, in particular, in the embodiment of the present application, the width of the electrical isolation region 300 is in a range of 1nm to 5mm, and preferably, the width of the electrical isolation region 300 is in a range of 1um to 10 um; then, the N-DBR structure 120 of the epitaxial structure is further processed by photolithography or other etching process to partially reduce the number of layers of the N-DBR structure 120 at specific locations, and the etched regions of the N-DBR structure 120 are also filled with a transparent non-conductive material to form the electrically isolated region 300; then, forming a positive electrode 16 on the mesa structure by an evaporation process; next, the negative conductive layer 170 is formed in the N-DBR structure 120 to fabricate the monolithically integrated VCSEL chip.

The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.

The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".

It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for the purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.

Claims

1. A monolithically integrated VCSEL chip, comprising:

2. The monolithically integrated VCSEL chip of claim 1, wherein the first VCSEL unit and the second VCSEL unit each comprise: the semiconductor device comprises a substrate, an N-DBR layer formed on the substrate, an active region located above the N-DBR layer, an oxidation limiting layer used for limiting a light emitting aperture, a P-DBR layer located above the active region, and a positive electrode and a negative electrode used for conducting the active region, wherein an electric isolation region is arranged between each first VCSEL unit and each second VCSEL unit, the N-DBR layer of each first VCSEL unit and the N-DBR layer of each second VCSEL unit are coupled with each other to form the N-DBR structure shared by a first VCSEL sub-chip and a second VCSEL sub-chip.

3. The monolithically integrated VCSEL chip of claim 2, wherein the first VCSEL units of the first VCSEL chiplet and the second VCSEL units of the second VCSEL chiplet are formed on the opposing first and second sides of the VCSEL chip in an alternating manner with respect to one another.

4. The monolithically integrated VCSEL chip of claim 2, wherein the first VCSEL units of the first VCSEL chiplet and the second VCSEL units of the second VCSEL chiplet are symmetrically formed on the first and second opposing sides of the VCSEL chip.

5. The monolithically integrated VCSEL chip of claim 2, wherein the second VCSEL units of the second VCSEL chiplet are formed serially between the first VCSEL units of the first VCSEL chiplet and the second VCSEL units of the second VCSEL chiplet are formed on the opposing first and second sides of the VCSEL chip.

6. The chip-integrated VCSEL chip of claim 3 or 5, wherein in each of the first VCSEL units, a reflectivity of the N-DBR layer is higher than a reflectivity of the P-DBR layer so that laser light generated from the first VCSEL unit exits a first side of the VCSEL chip, and in each of the second VCSEL units, the reflectivity of the N-DBR layer is lower than the reflectivity of the P-DBR layer so that laser light generated from the first VCSEL unit exits a second side of the VCSEL chip opposite to the first side.

7. The monolithically integrated VCSEL chip of claim 6, wherein in each of the first VCSEL units, the number of layers of the P-DBR layer is greater than the number of layers of the N-DBR; in each of the second VCSEL units, the number of layers of the P-DBR layer is smaller than the number of layers of the N-DBR.

8. The monolithically integrated VCSEL chip of claim 7, wherein in each of the first VCSEL units, the P-DBR layer number ranges from 15 to 45 layers, and the N-DBR layer number ranges from 15 to 45 layers; in each of the second VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR layer ranges from 15 to 45 layers.

9. The monolithically integrated VCSEL chip of claim 4, wherein, in each of the first VCSEL units, the reflectivity of the N-DBR layer is higher than the reflectivity of the P-DBR layer such that laser light generated by the first VCSEL unit exits a first side of the VCSEL chip, and in each of the second VCSEL units, the reflectivity of the N-DBR layer is higher than the reflectivity of the P-DBR layer such that laser light generated by the first VCSEL unit exits a second side of the VCSEL chip opposite the first side.

10. The monolithically integrated VCSEL chip of claim 9, wherein in each of the first VCSEL units, the number of layers of the N-DBR layer is greater than the number of layers of the P-DBR; in each of the second VCSEL units, the number of N-DBR layers is greater than the number of P-DBR layers.

11. The monolithically integrated VCSEL chip of claim 10, wherein in each of the first VCSEL units, the P-DBR layer number ranges from 15 to 45 layers, and the N-DBR layer number ranges from 15 to 45 layers; in each of the second VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR layer ranges from 15 to 45 layers.

12. A monolithically integrated VCSEL chip as claimed in any of claims 3-5 wherein a negative electrode of each of the first VCSEL units and a negative electrode of each of the second VCSEL units are coupled to each other to form a negative conductive layer.

13. The monolithically integrated VCSEL chip of claim 12, wherein the negative conductive layer is formed within the N-DBR structure.

14. The monolithically-integrated VCSEL chip of claim 13, wherein an anode of each of the first and second VCSEL units is formed on the first side of the VCSEL unit.

15. The monolithically integrated VCSEL chip of any of claims 3-5, wherein a positive electrode of each of the first VCSEL unit and the second VCSEL unit is formed on the first side of the VCSEL unit; the negative pole of each of the first VCSEL unit and each of the second VCSEL unit is formed on the second side of the VCSEL chip.

16. The monolithically integrated VCSEL chip of claim 15, wherein the cathodes of each second VCSEL unit are spaced apart and the laser light emitted from each second VCSEL unit is adapted to be emitted from a gap formed by two adjacent cathodes.

17. The monolithically integrated VCSEL chip of claim 15, wherein the cathode of each second VCSEL unit is made of a light permeable conductive material.

18. The monolithically integrated VCSEL chip of claim 17, wherein cathodes of at least some of the second VCSEL units are coupled to one another to form a cathode conductive layer.

19. The monolithically integrated VCSEL chip of claim 4, wherein the first VCSEL chiplet and the second VCSEL chiplet are selected from any of TOF VCSEL chips and structured light VCSEL chips.

20. The monolithically integrated VCSEL chip of claim 3 or 5, wherein the first VCSEL chiplet and the second VCSEL chiplet are the same type of VCSEL chip and have different optical powers.

21. The monolithically integrated VCSEL chip of claim 20, wherein the first VCSEL chiplet and the second VCSEL chiplet are selected from any of a TOF VCSEL chip and a structured light VCSEL chip.

22. The monolithically integrated VCSEL chip of claim 2, wherein the width of the electrical isolation region ranges from 1nm to 5 mm.

23. The monolithically integrated VCSEL chip of claim 22, wherein the electrically isolated region has a width in a range of 1um to 10 um.