CN212726944U

CN212726944U - Ring oscillator

Info

Publication number: CN212726944U
Application number: CN202020730401.3U
Authority: CN
Inventors: 区力翔; 张亮; 王静
Original assignee: Gree Electric Appliances Inc of Zhuhai; Zhuhai Zero Boundary Integrated Circuit Co Ltd
Current assignee: Gree Electric Appliances Inc of Zhuhai; Zhuhai Zero Boundary Integrated Circuit Co Ltd
Priority date: 2020-05-06
Filing date: 2020-05-06
Publication date: 2021-03-16
Anticipated expiration: 2030-05-06

Abstract

The application discloses a ring oscillator for improving stability of output frequency of the ring oscillator. The ring oscillator includes: a bias current generating circuit and a ring oscillator circuit; the bias current generating circuit is used for generating bias current and inputting the bias current into the ring oscillation circuit; wherein a temperature coefficient of the bias current generating circuit is adjustable; the ring oscillation circuit is used for outputting a clock signal under the action of the bias current; wherein the temperature coefficient of the ring oscillator is associated with the temperature coefficient of the bias current generating circuit, and the temperature coefficient of the ring oscillator is changed by adjusting the temperature coefficient of the bias current generating circuit so that the temperature coefficient of the ring oscillator is smaller than a first threshold value.

Description

Ring oscillator

Technical Field

The present application relates to the field of electronic circuit technology, and more particularly, to a ring oscillator.

Background

With the rise of the internet of things industry and wearable equipment, low power consumption becomes a very important research direction, and a low-power-consumption microcontroller (Micro Control Unit, MCU) has the advantages of small area, high performance, low power consumption and the like, so that the MCU is widely used in consumer electronics, and an oscillator is required to be used for providing a reference clock for an MCU chip.

The oscillator is a circuit capable of changing its output information according to a fixed period in a self-excited manner, and with the development of integrated circuit technology, oscillators with novel circuit structures are in endless numbers. The ring oscillator is applied to an integrated circuit chip because of the advantages of simple structure, convenient use, strong portability, small area, low cost and the like, but the conventional ring oscillator adopts on-chip integration which is influenced by factors such as process angle deviation, temperature change, power supply fluctuation and the like, so that the stability of the output frequency of the ring oscillator is low when the temperature and the process parameters are changed.

In summary, how to improve the stability of the output frequency of the ring oscillator becomes a technical problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a ring oscillator, which is used for improving the stability of the output frequency of the ring oscillator.

In a first aspect, an embodiment of the present application provides a ring oscillator, including: a bias current generating circuit and a ring oscillator circuit;

the bias current generating circuit is used for generating bias current and inputting the bias current into the ring oscillation circuit; wherein a temperature coefficient of the bias current generating circuit is adjustable;

the ring oscillation circuit is used for outputting a clock signal under the action of the bias current;

wherein the temperature coefficient of the ring oscillator is associated with the temperature coefficient of the bias current generating circuit, and the temperature coefficient of the ring oscillator is changed by adjusting the temperature coefficient of the bias current generating circuit so that the temperature coefficient of the ring oscillator is smaller than a first threshold value.

In the embodiment of the application, since the temperature coefficient of the bias current generating circuit is associated with the temperature coefficient of the ring oscillator circuit, and the temperature coefficient of the bias current generating circuit is adjustable, when the temperature changes, the temperature coefficient of the ring oscillator circuit can be changed by adjusting the temperature coefficient of the bias current generating circuit, so that the temperature coefficient of the ring oscillator is smaller than the first threshold, and the clock signal output by the ring oscillator can be basically not influenced by the temperature by changing the temperature coefficient of the ring oscillator.

In one possible design, the bias current generating circuit includes a reference voltage circuit, a temperature coefficient adjusting circuit, and a frequency adjusting circuit;

the reference voltage circuit is used for providing reference voltage for the temperature coefficient regulating circuit and the frequency regulating circuit;

the temperature coefficient adjusting circuit is used for adjusting the temperature coefficient under the action of the reference voltage;

and the frequency adjusting circuit is used for adjusting the current value of the reference current under the action of the reference voltage when the offset of the reference current is larger than a second threshold value, so that the offset of the reference current is smaller than the second threshold value, wherein the current value of the reference current is associated with the output frequency of the ring oscillator, and the output frequency of the ring oscillator is changed by adjusting the current value of the reference current.

In the embodiment of the application, when the temperature coefficient is changed, the temperature coefficient can be adjusted through the temperature coefficient adjusting circuit, and the output frequency of the ring oscillator is ensured not to be influenced by temperature basically. And when the magnitude of the reference current deviates from the typical value due to the process mode and the deviation amount of the deviation is larger than the second threshold value, the frequency adjusting circuit can adjust the current value of the reference current under the action of the reference voltage, namely correct the reference current to approach the typical value, and because the magnitude of the current value of the reference current is related to the frequency of the ring oscillator, the output frequency of the ring oscillator can be basically stabilized and unchanged when the process deviation exists by adjusting the reference current.

In one possible design, the temperature coefficient adjusting circuit includes a plurality of fet arrays, the temperature coefficient is changed by changing a width-to-length ratio of the plurality of fet arrays included in the temperature coefficient adjusting circuit, and the fets included in each of the plurality of fet arrays in the temperature coefficient adjusting circuit are both P-type fets or both N-type fets.

In the embodiment of the application, the temperature coefficient adjusting circuit can change the temperature coefficient by changing the width-to-length ratio of the field effect transistor array, so that the temperature coefficient is adjustable, the output frequency of the ring oscillator can be basically not influenced by the temperature, and the circuit is composed of field effect transistors, so that the occupied area of the circuit structure is small, and the process portability is better.

In one possible design, the frequency adjusting circuit includes a plurality of field effect transistor arrays, and the current value of the reference current is changed by changing the width-to-length ratio of the plurality of field effect transistor arrays included in the frequency adjusting circuit, and the field effect transistors in the plurality of field effect transistor arrays in the frequency adjusting circuit are N-type field effect transistors.

In the embodiment of the application, the frequency adjusting circuit can change the size of the reference current by changing the width-to-length ratio of the field effect transistor array, so that the reference current can be corrected when process deviation exists, the output frequency of the ring oscillator can be basically unaffected when the process deviation exists, the circuit is completely composed of field effect transistors, the occupied area of the circuit structure is small, and the portability of the process is better.

In one possible design, the ring oscillator circuit includes M inverters and M load capacitors;

the M phase inverters are annularly connected in series to form a phase inverter annular loop, each phase inverter in the M phase inverters is composed of an N-type field effect transistor and a P-type field effect transistor, the output end of the bias current generating circuit is connected with the source electrode of the P-type field effect transistor in each phase inverter, and each load capacitor in the M load capacitors is correspondingly connected with each phase inverter one by one.

In one possible design, the sizes of the M N-fets in the M inverters are the same, the sizes of the M P-fets in the M inverters are the same, and the capacitance values of the M load capacitors are the same.

In a possible design, the temperature coefficient adjusting circuit and the frequency adjusting circuit further include at least one switch, and the at least one switch is connected to at least one field effect transistor included in the temperature coefficient adjusting circuit and the frequency adjusting circuit one by one;

and controlling the width-to-length ratio of the field effect tube array formed by the at least one field effect tube by controlling the closed state of each switch.

In the embodiment of the application, the number of the field effect tubes connected in parallel in the field effect tube array is different, the width-to-length ratio of the field effect tube array is different, and the parallel connection number of the field effect tubes is controlled by the closed state of the switch corresponding to each field effect tube one to one, so that the temperature coefficient or the reference current can be effectively changed by changing the width-to-length ratio of the field effect tube array.

In a possible design, the ring oscillator further includes a level shift circuit, and the level shift circuit receives the clock signal sent by the ring oscillator circuit, converts the clock signal into a square wave clock signal, and outputs the square wave clock signal.

In the embodiment of the application, the clock signal output by the ring oscillator circuit can be converted into the square wave signal through the level conversion circuit, which is beneficial to the effective output of the clock signal.

In a possible design, the ring oscillator further includes an output buffer circuit, and the output buffer circuit enhances the driving capability of the square wave clock signal and outputs the square wave clock signal after receiving the square wave clock signal sent by the level shift circuit.

In the embodiment of the application, the driving capability of the clock signal output by the level shifter circuit can be enhanced through the output buffer circuit, so that the effective output of the clock signal can be facilitated, and the finally output clock signal can better meet the clock requirement of equipment needing to provide the clock signal.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a ring oscillator according to the prior art;

fig. 2 is a schematic structural diagram of a ring oscillator according to an embodiment of the present disclosure;

fig. 3 is an equivalent circuit diagram of a bias current generating circuit according to an embodiment of the present disclosure;

fig. 4 is an equivalent circuit diagram of a temperature coefficient adjusting circuit according to an embodiment of the present disclosure;

fig. 5 is an equivalent circuit diagram of a frequency adjustment circuit according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating a storage of a switch control signal according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another ring oscillator according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed out of order here.

The terms "first" and "second" in the description and claims of the present application and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the term "comprises" and any variations thereof, which are intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. The "plurality" in the present application may mean at least two, for example, two, three or more, and the embodiments of the present application are not limited.

In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document generally indicates that the preceding and following related objects are in an "or" relationship unless otherwise specified.

In a conventional ring oscillator, please refer to fig. 1, the ring oscillator may include a ring oscillator circuit, a level shifter circuit and an output buffer circuit, where the ring oscillator circuit includes 5 stages of inverters and 5 load capacitors, each stage of inverter includes a P-type channel Oxide Semiconductor (PMOS) transistor and an N-type field Oxide Semiconductor (NMOS) transistor, the PMOS transistors in the 5 stages of inverters are MP 1-MP 5, and the NMOS transistors are MN 1-MN 5. The ring oscillation circuit inputs the clock signal into the level conversion circuit to perform waveform conversion, then the circuit conversion circuit inputs the clock signal into the output buffer circuit, and the output buffer circuit outputs the final clock signal.

Suppose the threshold voltages of the PMOS transistor and the NMOS transistor in FIG. 1 are | V_THP|＝V_THN＝V_THThen the oscillation period of the ring oscillator circuit can be expressed as formula 1:

equation 1:

where N is the number of inverter stages, with 5 stages of inverters in FIG. 1, N is equal to 5, V_DDIs the supply voltage, C_loadIs a load capacitance, and C_load1-C_load5Equal capacitance value, beta_NAnd beta_PRelated to the process parameters and to the process.

Because the oscillation period is realized by charging and discharging delay accumulation of the load capacitor by the inverter, the load capacitor is easily influenced by the process, beta_NAnd beta_PAnd the conventional ring oscillator is easily affected by power supply, process and temperature changes, so that the stability of the output frequency of the oscillator is low when the temperature and process parameters change.

In view of the above, the present application provides a ring oscillator that can output a clock signal with a stable oscillation frequency by making the oscillation frequency substantially not change with a change in temperature when the temperature changes.

The ring oscillator provided by the embodiment of the present application is described in detail below with reference to the drawings of the specification.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a ring oscillator according to an embodiment of the present disclosure. The ring oscillator comprises a bias current generating circuit 201 and a ring oscillation circuit 202, wherein the bias current generating circuit 201 is used for generating a bias current and inputting the bias current into the ring oscillation circuit 202 so as to charge and discharge a load capacitor in the ring oscillation circuit 202. The ring oscillator circuit 202 outputs a clock signal by the bias current.

The oscillation period of the ring oscillator can be expressed as equation 2:

equation 2:

wherein N is the number of inverter stages, V_OSCIs the amplitude of oscillation, I_BIs the bias current. From this expression, it can be seen that the oscillation period of the ring oscillator is independent of the power supply, but is affected by the bias current, and therefore, by appropriately controlling the bias current, the oscillation period of the ring oscillator can be made substantially invariant with temperature and power supply.

In the embodiment of the present application, when the temperature of the environment in which the ring oscillator is located changes, the temperature coefficient of the ring oscillator itself changes, and when the temperature coefficient of the ring oscillator is greater than a certain threshold, for example, the threshold may be referred to as a first threshold, in which case, the output frequency of the ring oscillator is greatly affected, the first threshold may be 0 or a value close to 0, and when the temperature coefficient of the ring oscillator is 0, it may be understood that the frequency of the ring oscillator is not affected by the temperature.

Since the temperature coefficient of the bias current generating circuit 201 is adjustable, and the temperature coefficient of the ring oscillator is associated with the temperature coefficient of the bias current generating circuit, the temperature coefficient of the ring oscillator can be changed by adjusting the temperature coefficient of the bias current generating circuit, so that the temperature coefficient of the ring oscillator is smaller than the first threshold, and the ring oscillator 202 outputs a clock signal with stable frequency under the action of the bias current.

As shown in fig. 3, the bias current generating circuit 201 includes three parts, namely a reference voltage circuit 301, a temperature coefficient adjusting circuit 302 and a frequency adjusting circuit 303. The reference voltage circuit 301 can provide a reference voltage for the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303, the temperature coefficient adjusting circuit 302 adjusts the temperature coefficient of the bias current generating circuit 201 under the action of the reference voltage provided by the reference voltage circuit 301, the frequency adjusting circuit 303 adjusts the reference current under the action of the reference voltage provided by the reference voltage circuit 301, and the output frequency of the ring oscillator can be adjusted by adjusting the magnitude of the reference current because the current value of the reference current is related to the output frequency of the ring oscillator.

It should be noted that the current value of the reference current needs to be adjusted only when the offset amount is larger than the threshold, and for convenience of distinction, for example, the threshold may be referred to as a second threshold, that is, when the offset amount of the reference current is larger than the second threshold, the frequency adjustment circuit 303 may adjust the offset amount to be smaller than the second threshold. The current value of the reference current deviates from the typical value when the process angle is different, so that the reference current can be basically kept at the value of the typical value by adjusting the current value of the reference current.

As an example, in fig. 3, the reference voltage circuit 301 is composed of a plurality of PMOS transistors, and is divided into two rows and connected correspondingly, the number of the PMOS transistors in each row is the same, the PMOS transistors in the first row and the second row are in one-to-one correspondence, the gate of the previous PMOS transistor in each row of PMOS transistors is connected with the gate of the next PMOS transistor, the sources of all the PMOS transistors in the first row are connected to VDD, the drains are connected to the sources of the corresponding PMOS transistors in the second row, the drains of all the PMOS transistors except the last PMOS transistor in the second row are connected to the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303, and the drain of the last PMOS transistor outputs the bias current.

As shown in fig. 3, the temperature coefficient adjusting circuit 302 includes a plurality of PMOS transistors and a plurality of NMOS transistors, as an example, the plurality of PMOS transistors are M7-M10, the plurality of NMOS transistors are M1, M2 and M4-M6, the drain of M4 is connected to the reference voltage circuit 301, the source is grounded, and the gate is connected to the drain of the PMOS transistor and the gate of M7; the source of M7 is grounded, the drain is connected with the source of M8 and the reference voltage circuit 301; the drain of M8 is connected with the drain of M5, and the gate is connected with the drain of M1, the gate of M9 and the reference voltage circuit 301; the source of M5 is grounded, and the gate is connected with the drain of the M5 and the gate of M6; the grid electrode of the M1 is connected with the drain electrode of the M1 and the grid electrode of the M9, and the source electrode is grounded; the drain of M9 is connected to the source of M10 and the reference voltage circuit 301, and the source is grounded; the drain of M10 is connected with the drain of M6, and the gate is connected with the drain of M2; the source of M6 is grounded; the drain of M2 is connected to reference voltage circuit 301, and the source is connected to the drain of the MR in frequency adjustment circuit 303.

As shown in fig. 3, the frequency adjusting circuit 303 may include two NMOS transistors, MR and M3, where the source of MR is grounded, the drain is connected to the source of M2 in the temperature coefficient adjusting circuit, and the gate is connected to the gate of M3; m3 has its source connected to ground and its drain connected to its gate and to reference voltage circuit 301.

In summary, the bias current generating circuit is composed of field effect transistors, so that the occupied circuit structure area is small, and the process portability is good.

Since the working current of the MOS transistor working in the sub-threshold region is small, the overall power consumption of the circuit can be low, and therefore, the core MOS transistor in the bias current generating circuit 201 can work in the sub-threshold region. M1, M2, M4 and M7-M10 in the temperature coefficient adjusting circuit 302 work in a subthreshold region, M5 and M6 work in a saturation region, an MR in the frequency adjusting circuit 303 works in a deep linear region and is used as a resistor, and M3 works in the saturation region to provide bias voltage for the MR.

Reference current I_REFCan be expressed as equation 3:

equation 3:

wherein, K_RAnd K₃Width to length ratio, V, of MR and M3, respectively_DSRIs the drain voltage of MR, μ is the electron mobility, C_OXIs a MOS tube grid oxide layer capacitor.

Bias current I_BCan be expressed as publicFormula 4:

equation 4: i is_B＝MI_REF；

Where M is the current mirror ratio.

Since M1 and M2 operate in the subthreshold region, equation 5 can be obtained:

equation 5:

wherein, V_GS1Is the gate-source voltage, V, of M1_GS2Is the gate-source voltage of M2, η is the subthreshold slope factor, k is the Boltzmann constant, q is the electronic charge, and T is the temperature.

From equation 5, V can be obtained_DSREquation 6 of (1):

equation 6:

if V in the formula 6 is used_G2-V_G1＝A，

Equation 7 can be derived:

equation 7: v_DSR＝A+BT；

M5 and M6 operate in the saturation region, ensuring that the currents of M7 and M8 are equal to the currents of M9 and M10, where a can be expressed as formula 8:

equation 8:

then I can be obtained_REFThe temperature coefficient of (d) is equation 9:

equation 9:

wherein the value of the coefficient m in the standard cmos process is about 1.5. From equation 9, the adjustment

The temperature coefficient can be adjusted, the current value of the reference current can be controlled, and the temperature coefficient can be adjusted

The coefficient is substantially zero.

Each fet included in the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303 may be connected in parallel to form a plurality of fet arrays, that is, the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303 may be understood to include a plurality of fet arrays. For example, in the temperature coefficient adjusting circuit 302, M1 may be understood as a fet directly connected in the circuit, and M1 may connect a plurality of fets (not shown in fig. 3) of the same type in parallel to form an array of fets corresponding to M1. Similarly, any fet included in the temperature coefficient adjusting circuit 302 and any fet included in the frequency adjusting circuit 303 may be understood as being directly connected in the circuit, and each fet may be connected in parallel with a plurality of fets identical to itself, thereby forming a fet array. It should be noted that, in a specific implementation process, the number of field effect transistors connected in parallel in a part or all of the field effect transistor arrays may be changed, so as to change the aspect ratio of the corresponding field effect transistor array.

In a possible implementation manner, the temperature coefficient adjusting circuit 302 may change the width-to-length ratio of the plurality of fet arrays included in the circuit, and then change the temperature coefficient, since the temperature coefficient of the ring oscillator circuit 202 is associated with the temperature coefficient of the bias current generating circuit 201, for example, in a positive correlation proportional relationship with the ambient temperature, the temperature coefficient of the ring oscillator circuit 202 may be changed by adjusting the temperature coefficient of the bias current generating circuit 201, and then adjust the temperature coefficient of the ring oscillator, and when the temperature changes, the temperature coefficient of the ring oscillator may be adjusted to be adapted to the current ambient temperature, so that the temperature compensation is implemented, and the stability of the output frequency is ensured.

It should be noted that, because the temperature coefficient adjusting circuit 302 includes a PMOS transistor and an NMOS transistor, and when the temperature coefficient adjusting circuit is connected in parallel, each fet is connected in parallel with a fet that is the same as the fet itself, the fets included in each fet array in the plurality of fets in the circuit are all NMOS transistors of the same type, or are all PMOS transistors of the same type.

In one possible implementation, the frequency adjustment circuit 303 may adjust the current value of the reference current by changing the width-to-length ratio of several fet arrays included in the circuit. Different process angles can cause different process deviations, when the process angle parameters change, the current value of the reference current deviates from a typical value, that is, the offset of the reference current is larger than a second threshold value, at this time, the current value of the reference current can be adjusted by changing the width-to-length ratio of the field effect transistor array included in the frequency adjusting circuit 303, so that process compensation is realized, and the output frequency of the ring oscillator circuit 202 is ensured to be basically stable under the action of the bias current.

It should be noted that, because the frequency adjusting circuit 303 only includes NMOS transistors, and when the frequency adjusting circuit is connected in parallel, each fet is connected in parallel with a fet that is the same as the fet itself, the fets included in each fet array of the plurality of fet arrays included in the frequency adjusting circuit are all NMOS transistors of the same type.

In a possible implementation manner, the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303 may further include at least one switch, where the at least one switch corresponds to at least one fet included in the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303 one to one, and in the fet arrays included in the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303, one fet is directly connected to each fet array, and then the remaining fets have corresponding switches, and the number of fets connected in parallel in the fet arrays may be controlled by controlling the on/off states of the switches, so as to change the aspect ratio of the fet arrays. It should be noted that the number of switches and the number of fets included in each fet array may be equal or unequal, and the embodiments of the present application are not limited.

The method of adjusting the fet array by the tcc circuit 302 is further illustrated by fig. 4. Fig. 4 is a partial equivalent circuit diagram of the temperature coefficient adjusting circuit 302 according to the embodiment of the present application, and fig. 4 shows the fet arrays to which M4 and M1 belong. In fig. 4, M1 and M4 are NMOS transistors directly connected in a circuit, the fet array to which M4 belongs further includes K fets identical to M4, the K fets correspond to K switches, i.e., switch 2, switch 4, and switch … …, and the number of fets connected in parallel in the fet array to which M4 belongs can be changed by controlling the on/off states of the K switches, thereby changing the aspect ratio. Similarly, the fet array belonging to M1 may include a plurality of switches and a plurality of fets identical to M1, but the number may be different from the number included in M4, for example, in fig. 4, the fet array belonging to M1 includes K +1 fets identical to M1, and the K +1 fets correspond to K +1 switches, i.e., switch 1, switch 3, and switch 2K +1 of … …, respectively.

The manner of changing the width-to-length ratio of the other fet arrays in the tcc circuit 302 is similar to that described above, and it can be understood that the details are not described here.

The method for adjusting the aspect ratio of the fet array by the frequency adjustment circuit 303 is further described below with reference to fig. 5. Fig. 5 is a partial equivalent circuit diagram of the frequency adjustment circuit 303 according to an embodiment of the present application, and fig. 5 shows a circuit diagram of a fet array to which the MR belongs. In fig. 5, MR is an NMOS transistor directly connected in the circuit, the fet array to which MR belongs further includes K fets identical to MR, the K fets correspond to the K switches, respectively, and are switches 1 to K, and the number of fets connected in parallel in the fet array to which MR belongs can be changed by controlling the on/off states of the K switches, so as to change the aspect ratio.

The other fet arrays in the frequency adjustment circuit 303 may change the aspect ratio in a similar manner to that described above, and it is understood that the details are not repeated here.

In a specific implementation, each switch included in the temperature coefficient adjusting circuit 302 and the frequency adjusting circuit 303 may have its state transition controlled by N control bits, for example, the state transition of the first switch in the fet array corresponding to M1 shown in fig. 4 may be controlled by the control bit SW₁～NSW₁The last switch being controlled by a control bit SW_2K+1～NSW_2K+1The state transition of the first switch in the MR array shown in FIG. 5 can be controlled by a control bit SWR₁～NSWR₁The last switch can be controlled by a control bit SWR_K～NSWR_KAnd in this way, the effectiveness and accuracy of the state transition of each switch can be ensured.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating a storage of a switch control signal according to an embodiment of the present disclosure. The register in fig. 6 may be a register included in the ring oscillator itself, or may be a register in a device that needs the ring oscillator to provide a clock signal in order to simplify the circuit configuration of the ring oscillator. When the width-length ratio of the field effect tube array needs to be adjusted, the register can send the control bit information of each switch to the corresponding field effect tube array, and each field effect tube array can determine the state conversion of each switch according to the control signal given by the register, so that the number of the field effect tubes connected in parallel in the corresponding field effect tube array is changed, and the width-length ratio is changed.

The ring oscillator circuit 202 includes M inverters and M load capacitors, and in fig. 2, M is equal to 5, and each inverter is composed of an NMOS transistor and a PMOS transistor. In fig. 2, the device includes 5 PMOS transistors and 5 NMOS transistors, and 5 load capacitors, where the 5 PMOS transistors are MP 1-MP 5, the 5 NMOS transistors are MN 1-MN 5, and the 5 load capacitors are C_load1～C_load5MP1 and MN1 form the first stage inverter, MP2 and MN2 form the second stage inverter, and MP3 and MN3 form the second stage inverterThe third stage inverter, MP4 and MN4 form the fourth stage inverter and MP5 and MN5 form the fifth stage inverter.

It should be noted that, in a specific implementation process, the number of the inverters and the load capacitors may not be 5, and it is only required to ensure that each inverter has one load capacitor corresponding to the inverter and the number of the load capacitors is an odd number greater than or equal to 3. MOM electric capacity can be selected for use to load capacitance, and the temperature coefficient of this electric capacity is less, and when the temperature variation, it is less to ring oscillator's oscillation cycle's influence, perhaps, can also adopt amplitude temperature coefficient's electric capacity and MOM electric capacity to use in parallel according to the in-service use demand, further ensures temperature compensation's validity, to load capacitance's type, this application embodiment does not do the restriction.

In fig. 2, the source electrodes of 5 PMOS transistors included in the ring oscillator circuit 202 are connected to the output terminal of the bias current generating circuit, the drain electrode of the PMOS transistor in each stage of the inverter is connected to the drain electrode of the corresponding NMOS transistor and the gate electrodes of the PMOS transistor and the NMOS transistor in the next stage of the inverter, the source electrode is connected to the source electrode of the corresponding NMOS transistor, the source electrodes of the 5 NMOS transistors are grounded, 5 load capacitors are respectively in one-to-one correspondence with the 5 inverters, one end of each load capacitor is linked to the output terminal of the inverter, and the other end is grounded. It should be noted that, when the number of the inverters and the load capacitors is not 5, the connection may be performed according to the same connection method, which is not described herein again.

It should be noted that, in the ring oscillator circuit 202, the sizes of M NMOS transistors included in the M inverters are the same, the sizes of M PMOS transistors included in the M inverters are also the same, and the capacitance values of the M load capacitors are equal.

In a specific embodiment, when the bias current generating circuit 201 inputs the bias current to the ring oscillator circuit 202, the load capacitor of the ring oscillator circuit 202 is charged and discharged, and finally the clock signal is output.

Referring to fig. 7, fig. 7 is a schematic structural diagram of another ring oscillator according to an embodiment of the present disclosure, in which the ring oscillator includes a level shift circuit 203 and an output buffer circuit 204 in addition to a bias current generation circuit 201 and a ring oscillation circuit 202. The level shift circuit 203 includes two inverters, two NMOS transistors and two PMOS transistors, where the two inverters are both connected to VDD, an input terminal of the previous inverter is connected to an output terminal of the ring oscillator circuit 202 and a gate of the first NMOS transistor (i.e., the previous NMOS transistor in the circuit diagram), an output terminal is connected to an input terminal of the next inverter, an output terminal of the next inverter is connected to a gate of the second NMOS transistor, sources of the two PMOS transistors are connected to VCC, a gate of the first PMOS transistor (i.e., the previous PMOS transistor in the circuit diagram) is connected to a drain of the second PMOS transistor and a drain of the second NMOS transistor, a gate of the second PMOS transistor is connected to a drain of the first PMOS transistor and a drain of the first NMOS transistor, and sources of the two NMOS transistors are grounded. The ring oscillator circuit 202 inputs the clock signal to the level shifter circuit 203, and the level shifter circuit 203 converts the amplitude of the clock signal from VDD to VCC, that is, converts the clock signal into a square wave signal and outputs the square wave signal.

The output buffer circuit 204 comprises a PMOS tube and an NMOS tube, wherein the source electrode of the PMOS tube is connected with VCC, the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube and then connected with the output end of the bottle conversion, and the source electrode of the NMOS tube is grounded. The output buffer circuit 204 increases the driving capability of the square wave signal output from the level shifter circuit 203, and then transmits the final clock signal to the device that needs to provide the clock signal, so that the output clock signal can be ensured to have stable oscillation frequency, and the effectiveness of signal output can be ensured.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A ring oscillator, comprising: a bias current generating circuit and a ring oscillator circuit;

wherein the temperature coefficient of the ring oscillator is associated with the temperature coefficient of the bias current generation circuit, and the temperature coefficient of the ring oscillator is changed by adjusting the temperature coefficient of the bias current generation circuit so that the temperature coefficient of the ring oscillator is smaller than a first threshold value, so that the output frequency of the ring oscillator is not influenced by temperature.

2. The ring oscillator of claim 1, wherein the bias current generating circuit includes a reference voltage circuit, a temperature coefficient adjustment circuit, and a frequency adjustment circuit;

and the frequency adjusting circuit is used for adjusting the current value of the reference current under the action of the reference voltage when the offset between the current value of the reference current and the typical value of the reference current is larger than a second threshold value, so that the offset is smaller than the second threshold value, wherein the current value of the reference current is associated with the output frequency of the ring oscillator, and the output frequency of the ring oscillator is changed by adjusting the current value of the reference current.

3. The ring oscillator of claim 2, wherein the temperature coefficient adjustment circuit comprises a plurality of fet arrays, the temperature coefficient is changed by changing a width-to-length ratio of the plurality of fet arrays included in the temperature coefficient adjustment circuit, and each fet included in the plurality of fet arrays in the temperature coefficient adjustment circuit is either a P-fet or an N-fet.

4. The ring oscillator of claim 2, wherein the frequency adjustment circuit includes a plurality of fet arrays, the current value of the reference current being changed by changing a width-to-length ratio of the plurality of fet arrays included in the frequency adjustment circuit, the fets in the plurality of fet arrays in the frequency adjustment circuit being N-type fets.

5. The ring oscillator of claim 1 wherein the ring oscillator circuit comprises M inverters and M load capacitors;

6. The ring oscillator of claim 5 wherein the M NFETs in the M inverters are the same size, the M PFETs in the M inverters are the same size, and the capacitance values of the M load capacitors are equal.

7. The ring oscillator according to claim 3 or 4, wherein the temperature coefficient adjusting circuit and the frequency adjusting circuit further comprise at least one switch, and the at least one switch is connected to at least one field effect transistor included in the temperature coefficient adjusting circuit and the frequency adjusting circuit one by one;

8. The ring oscillator of claim 1, further comprising a level shift circuit, wherein the level shift circuit receives the clock signal sent by the ring oscillator circuit, converts the clock signal into a square wave clock signal, and outputs the square wave clock signal.

9. The ring oscillator of claim 8, further comprising an output buffer circuit, wherein the output buffer circuit receives the square wave clock signal sent by the level shift circuit, and then enhances the driving capability of the square wave clock signal and outputs the square wave clock signal.