CN212627933U

CN212627933U - NCSI interface signal adapter and NCSI interface communication equipment

Info

Publication number: CN212627933U
Application number: CN202021527094.5U
Authority: CN
Inventors: 解文军; 刘铁军; 刘丹
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-07-29
Filing date: 2020-07-29
Publication date: 2021-02-26
Anticipated expiration: 2030-07-29

Abstract

The application discloses NCSI interface signal adaptation device and NCSI interface communication equipment, the device includes: the server sends a first signal to the network controller through the connector via the buffer chip, the network controller sends a second signal to the server via the buffer chip and the connector, any one of the resistors is connected with the buffer chip, the buffer chip is arranged close to the connector, wiring between the buffer chip and the connector is shortest, the resistor is close to a pin position of a signal output end of the buffer chip, and the distance between the resistor and the signal output end is less than or equal to 1 inch. The NCSI interface communication equipment is provided with the NCSI interface signal adapting device. Through the application, the electrical performance parameters of the NCSI signal under the condition of longer wiring can be ensured to meet the signal transmission requirement, and the accuracy and the signal transmission efficiency of data transmission are improved.

Description

NCSI interface signal adapter and NCSI interface communication equipment

Technical Field

The present invention relates to the field of NCSI (Network Controller Sideband Interface) signal transmission technology, and in particular, to an NCSI Interface signal adapting device and an NCSI Interface communication device.

Background

NCSI is an industry standard for a sideband interface network controller defined by DMTF (Distributed Management Task Force) to support out-of-band Management of servers. An MC (Management Controller) on the server manages the smart network card through an NCSI interface. In the signal transmission process of the NCSI interface, how to ensure the effectiveness of signal transmission is an important technical problem.

At present, in order to realize NCSI signal transmission between a server and an intelligent network card, the NCSI signal transmission device shown in fig. 1 is generally used. As shown in fig. 1, in the conventional signal transmission device, a clock is divided into two parts by a clock buffer, one part enters a management Controller through a resistor, the other part passes through the resistor, a PCB inside a server and a connector, and is connected to a Network card connector through a cable with a certain length, then the PCB (Printed Circuit Board) passing through an intelligent Network card is wired to an NC (Network Controller, a device capable of being connected to an external Network in the system), and a data signal passes through the resistor and then is directly connected to a receiving end, thereby realizing NCSI signal transmission between the server and the intelligent Network card.

However, due to different topologies of the NCSI interfaces of different server systems, the lengths of the wires may vary, and some server NCSI interfaces pass through one or more cables and connectors with different lengths, some servers may not pass through the cables at all, some servers may have longer wires on the board, and some servers may have shorter wires on the board. The existing NCSI signal transmission device is used for a server with short wiring and cable or simple topological structure, and has few problems. When the method is used in a server or a topology with long overall wiring, due to large load, electrical performance parameters such as the rise time of signals and the like can not meet the NCSI standard, so that the data transmission error rate is high, the communication quality is influenced, and the communication is serious or even impossible. Therefore, the signal transmission accuracy and the transmission efficiency of the current signal transmission device are low.

Disclosure of Invention

The application provides a NCSI interface signal adaptation device and NCSI interface communication equipment to solve the problems of lower accuracy and lower transmission efficiency of signal transmission of an NCSI signal transmission device in the prior art.

In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:

an apparatus for adapting NCSI interface signals, the apparatus comprising: connector, buffer chip, network controller and be used for adjusting a plurality of resistances of inputing buffer chip and exporting buffer chip signal level state, the server passes through the connector and sends first signal to network controller via buffer chip, and network controller sends the second signal to the server via buffer chip and connector, arbitrary resistance all with buffer chip connects, buffer chip is close to the connector setting, just distance between buffer chip and the connector satisfies the PCB design rule of setting for to it is shortest to make the walking line between buffer chip and the connector, resistance is close to buffer chip's signal output terminal pin position, just resistance is less than or equal to 1 inch with signal output terminal's distance, first signal includes: a TXD0 signal, a TXD1 signal, a TXEN signal, and a Clock signal, the second signal comprising: the RXD0 signal, the RXD1 signal, and the CRS _ DV signal.

Optionally, the plurality of resistors comprises: the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7 and the resistor R8;

the resistor R1 is used for adjusting the level of a Clock signal of the output buffer chip, one end of the resistor R1 is connected with the buffer chip, and the other end of the resistor R1 is connected with the network controller;

the resistor R2 is used for adjusting the level of the TXD0 signal of the output buffer chip, one end of the resistor R2 is connected with the buffer chip, and the other end of the resistor R2 is connected with the network controller;

the resistor R3 is used for adjusting the level of the TXD1 signal of the output buffer chip, one end of the resistor R3 is connected with the buffer chip, and the other end of the resistor R3 is connected with the network controller;

the resistor R4 is used for adjusting the level of the TXEN signal of the output buffer chip, one end of the resistor R4 is connected with the buffer chip, and the other end of the resistor R4 is connected with the network controller;

the resistor R5 is used for adjusting the level of an RXD0 signal input into the buffer chip, one end of the resistor R5 is connected with the network controller, and the other end of the resistor R5 is connected with the buffer chip;

the resistor R6 is used for adjusting the level of an RXD1 signal input into the buffer chip, one end of the resistor R6 is connected with the network controller, and the other end of the resistor R6 is connected with the buffer chip;

the resistor R7 is used for adjusting the level of a CRS _ DV signal input to the buffer chip, one end of the resistor R7 is connected with the network controller, and the other end of the resistor R7 is connected with the buffer chip;

the resistor R8 is used for adjusting the level of the signal of the output buffer chip, one end of the resistor R8 is connected with the buffer chip, and the other end of the resistor R8 is connected with the connector.

Optionally, when the trace length of the Clock signal is less than or equal to 0.5 × TXD0 signal trace length, the plurality of resistors include: the resistor R9, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7 and the resistor R8;

the resistance value of the resistor R9 is 0, the resistor R9 is arranged on the trace of the Clock signal, one end of the resistor R9 is connected with the connector, and the other end of the resistor R9 is connected with the network controller;

Optionally, when the trace length of the Clock signal is > 0.5 × TXD0 signal trace length, the plurality of resistors includes: a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8 and a resistor R10;

the resistor R10 is used for adjusting the level of a signal input into the buffer chip, one end of the resistor R10 is connected with the connector, and the other end of the resistor R10 is connected with the buffer chip;

An NCSI interface communication device is provided with the NCSI interface signal adapting device.

Optionally, the NCSI interface communication device includes: intelligent network card, OCP card and server.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

the application provides a NCSI interface signal adapter device, the device mainly includes: the system comprises a connector, a buffer chip, a network controller and a plurality of resistors, wherein the plurality of resistors are used for adjusting the signal level states of the input buffer chip and the output buffer chip, any resistor is connected with the buffer chip and is equivalent to one signal connection with the buffer chip, a first signal sent by the server is transmitted to the network controller through the buffer chip through the connector, and a second signal sent by the network controller is transmitted to the server through the buffer chip and the connector. The setting of buffer chip can effectively compensate the condition that the NCSI signal that the server walk the line longer and lead to weakens to ensure that the electrical property parameter of NCSI signal satisfies the signal transmission requirement, improve data transmission's accuracy and signal transmission efficiency.

The distance between the buffer chip and the connector meets the set PCB design rule, the routing between the buffer chip and the connector is shortest, and the signal transmission quality and the transmission efficiency are improved to the maximum extent. The resistor is close to the pin position of the signal output end of the buffer chip, and the distance between the resistor and the signal output end is less than or equal to 1 inch, so that the signal transmission quality and the transmission efficiency can be further improved.

The application also provides NCSI interface communication equipment, and the NCSI interface signal adapting device is arranged in the NCSI interface communication equipment. By arranging the NCSI interface signal adapting device, the signal transmission efficiency and the transmission quality of the communication equipment can be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a prior art NCSI signal transmission device;

fig. 2 is a schematic structural diagram of an NCSI interface signal adapting device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of the structure of an NCSI interface signal adapting device including 8 resistors;

fig. 4 is a schematic structural diagram of an NCSI interface signal adapting device under different Clock signal trace lengths.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

For a better understanding of the present application, embodiments of the present application are explained in detail below with reference to the accompanying drawings.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an NCSI interface signal adapting device according to an embodiment of the present application. As shown in fig. 2, the NCSI interface signal adapting device in this embodiment mainly includes: the circuit comprises a connector, a buffer chip, a network controller and a plurality of resistors. The plurality of resistors are used for adjusting the level states of the signals of the input buffer chip and the output buffer chip.

The NCSI interface signal adapting device comprises a first signal and a second signal. The server sends a first signal to the network controller through the connector and the buffer chip, and the network controller sends a second signal to the server through the buffer chip and the connector. The first signal includes: a TXD0 signal, a TXD1 signal, a TXEN signal, and a Clock signal, the second signal comprising: the RXD0 signal, the RXD1 signal, and the CRS _ DV signal. The electrical property parameters of the first and second signals include: signal rise time, signal fall time, highest level, and lowest level.

Any resistor is connected with the buffer chip, which is equivalent to that any resistor is matched with a signal and used for adjusting the level state of the signal. The buffer chip can enhance the driving capability of the signal, so that the accuracy of the signal in the transmission process can be kept.

The buffer chip is arranged close to the connector, and the distance between the buffer chip and the connector meets the set PCB design rule. The cache chip is arranged close to the connector, so that the TXD0 signals, TXD1 signals, TXEN signals and Clock signals which arrive through longer wires or cables on the server can be compensated, and the driving capability of RXD0 signals, RXD1 signals and CRS _ DV signals sent by the network controller NC can be enhanced.

In this embodiment, the routing between the buffer chip and the connector is the shortest, the resistor is close to the pin of the signal output end of the buffer chip, and the distance between the resistor and the signal output end is less than or equal to 1 inch, so that the driving capability of the first signal can be further compensated and the driving capability of the second signal can be further enhanced, thereby effectively improving the accuracy and the transmission efficiency of signal transmission.

Further, the plurality of resistors in this embodiment include: the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7 and the resistor R8. The schematic structural diagram of the NCSI interface signal adapting device including 8 resistors can be seen in fig. 3.

As shown in fig. 3, in this embodiment, one end of the resistor R1 is connected to the buffer chip, and the other end of the resistor R1 is connected to the network controller for adjusting the level of the Clock signal of the output buffer chip. One end of the resistor R2 is connected with the buffer chip, and the other end of the resistor R2 is connected with the network controller and used for adjusting the level of the TXD0 signal of the output buffer chip. One end of the resistor R3 is connected with the buffer chip, and the other end of the resistor R3 is connected with the network controller and used for adjusting the level of the TXD1 signal of the output buffer chip. One end of the resistor R4 is connected with the buffer chip, and the other end of the resistor R4 is connected with the network controller and used for adjusting the level of the TXEN signal of the output buffer chip. One end of the resistor R5 is connected with the network controller, and the other end of the resistor R5 is connected with the buffer chip and used for adjusting the level of the RXD0 signal input into the buffer chip. One end of the resistor R6 is connected with the network controller, and the other end of the resistor R6 is connected with the buffer chip and used for adjusting the level of the RXD1 signal input into the buffer chip. One end of the resistor R7 is connected with the network controller, and the other end of the resistor R7 is connected with the buffer chip and is used for adjusting the level of the CRS _ DV signal input to the buffer chip. One end of the resistor R8 is connected with the buffer chip, and the other end of the resistor R8 is connected with the connector and used for adjusting the level of the signal of the output buffer chip.

In this embodiment, a schematic structural diagram of the NCSI interface signal adapting device under different Clock signal routing lengths can be seen from fig. 4. The structure design is mainly applied to two states that the track length of the Clock signal is less than or equal to 0.5 TXD0 signal track length, and the track length of the Clock signal is more than 0.5 TXD0 signal track length.

In fig. 4, the resistor R10 and the resistor R1 are in a non-welding state in a default state, and this structural design can solve the problem of signal transmission when the CLOCK trace length is not greater than 0.5 × TXD0 signal trace length in most cases, and in this case, because the CLOCK trace length is relatively short, the driving capability of the CLOCK signal can meet the requirement, and therefore, only the resistor R9, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, and the resistor R8 need to be started. The resistor R9 is a 0 ohm resistor, and when the CLOCK trace length is less than or equal to 0.5 × TXD0 signal trace length, the CLOCK signal is directly transmitted to the network controller without passing through the buffer chip.

When the trace length of the Clock signal is greater than 0.5 × TXD0, the Clock signal cannot satisfy the signal transmission quality, and the R9 may be disconnected to connect the resistor R1 and the resistor R10, so that the Clock signal Clock is transmitted to the network controller via the buffer chip. At this time, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, and the resistor R10 are activated.

The resistor R1 and the resistor R10 may be connected by welding, and the resistor R9 may be disconnected by welding, or may be disconnected by welding.

The application also provides NCSI interface communication equipment which comprises an NCSI interface signal adapting device. By arranging the NCSI interface signal adapting device, the accuracy and the transmission quality of signal transmission in the communication equipment can be greatly improved.

Further, the NCSI interface communication device in this embodiment includes: intelligent network card, OCP card and server. Namely, the intelligent network card can be provided with an NCSI interface communication device, the OCP card can be provided with an NCSI interface communication device, and the server can also be provided with the NCSI interface communication device.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus for adapting NCSI interface signals, the apparatus comprising: connector, buffer chip, network controller and be used for adjusting a plurality of resistances of inputing buffer chip and exporting buffer chip signal level state, the server passes through the connector and sends first signal to network controller via buffer chip, and network controller sends the second signal to the server via buffer chip and connector, arbitrary resistance all with buffer chip connects, buffer chip is close to the connector setting, just distance between buffer chip and the connector satisfies the PCB design rule of setting for to it is shortest to make the walking line between buffer chip and the connector, resistance is close to buffer chip's signal output terminal pin position, just resistance is less than or equal to 1 inch with signal output terminal's distance, first signal includes: a TXD0 signal, a TXD1 signal, a TXEN signal, and a Clock signal, the second signal comprising: the RXD0 signal, the RXD1 signal, and the CRS _ DV signal.

2. The NCSI interface signal adapting device of claim 1, wherein the plurality of resistors comprise: the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7 and the resistor R8;

3. The apparatus of claim 1, wherein when the trace length of the Clock signal is less than or equal to 0.5 × TXD0, the plurality of resistors comprise: the resistor R9, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7 and the resistor R8;

4. The NCSI interface signal adapting device of claim 1, wherein when the trace length of the Clock signal is > 0.5 x TXD0 signal trace length, the plurality of resistors comprises: a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8 and a resistor R10;

5. An NCSI interface communication device, characterized in that, the NCSI interface communication device is provided with the NCSI interface signal adapting device of any of claims 1-4.

6. An NCSI interface communication device according to claim 5, wherein the NCSI interface communication device comprises: intelligent network card, OCP card and server.