CN212518946U - Alternative data selector - Google Patents

Abstract

The utility model provides an alternative data selector. The alternative data selector includes: a NOR logic circuit configured to receive a select signal and an inverted first input and to generate an intermediate result; and an and or nor logic circuit configured to receive the selection signal, the second input, and an intermediate result of the nor logic circuit and to generate an inverted output.

Description

Alternative data selector

Technical Field

The utility model relates to an alternative data selector.

Background

The area occupied by the data selector is proportional to the number of transistors used to implement the data selector. Therefore, as the total number of transistors decreases, the area occupied by the data selector also decreases. The reduction in data selector area will translate directly into a reduction in chip area and cost savings.

SUMMERY OF THE UTILITY MODEL

The utility model provides a novel circuit of alternative data selector realize, thereby it can reduce the quantity of the transistor of alternative data selector and reduce chip area.

According to an aspect of the utility model, a one-out-of-two data selector is provided, include: a NOR logic circuit configured to receive a select signal and an inverted first input and to generate an intermediate result; and an and or nor logic circuit configured to receive the selection signal, the second input, and an intermediate result of the nor logic circuit and to generate an inverted output.

Preferably, the inverted output is the inverted first input in case the selection signal is a logic 0 and the inverted output is the inverted second input in case the selection signal is a logic 1.

Preferably, the nor logic circuit includes: a first PMOS transistor having a gate terminal configured to receive a selection signal, wherein a source terminal of the first PMOS transistor is coupled to a power supply terminal; a second PMOS transistor having a gate terminal configured to receive the inverted first input, a source terminal coupled to the drain terminal of the first PMOS transistor, and a drain terminal coupled to the first node; a first NMOS transistor having a gate terminal configured to receive a select signal and a drain terminal coupled to a first node; and a second NMOS transistor having a gate terminal configured to receive the inverted first input and a drain terminal coupled to the first node, wherein a source terminal of each of the first and second NMOS transistors is coupled to the ground terminal, wherein the nor logic circuit is configured to produce an intermediate result at the first node.

Preferably, the and or logic circuit includes: a third PMOS transistor having a gate terminal configured to receive an intermediate result of the nor logic circuit, wherein a source terminal of the third PMOS transistor is coupled to the power supply terminal; a fourth PMOS transistor whose gate terminal is configured to receive the selection signal, whose source terminal is coupled to the drain terminal of the third PMOS transistor, and whose drain terminal is coupled to the second node; a fifth PMOS transistor whose gate terminal is configured to receive the second input, whose source terminal is coupled to the drain terminal of the third PMOS transistor, and whose drain terminal is coupled to the second node; a third NMOS transistor having a gate terminal configured to receive the intermediate result of the nor logic circuit and a drain terminal coupled to the second node; a fourth NMOS transistor having a gate terminal configured to receive the selection signal and a drain terminal coupled to the second node; and a fifth NMOS transistor having a gate terminal configured to receive the second input and a drain terminal coupled to the source terminal of the fourth NMOS transistor, wherein the source terminal of each of the third and fifth NMOS transistors is coupled to the ground terminal, wherein the and-or-nor logic circuit is configured to produce an inverted output at the second node.

Drawings

A better understanding of the present invention may be obtained when the following detailed description of the embodiments is considered in conjunction with the following drawings. The same or similar reference numbers are used throughout the drawings to refer to the same or like parts. The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the present invention and together with the detailed description, serve to explain the principles and advantages of the invention.

Fig. 1 shows a truth table for an alternative data selector.

Fig. 2 shows a logic diagram of an alternative data selector.

Fig. 3 shows a block diagram of the MUX2 alternative data selector.

Fig. 4 shows a block diagram of the MUXI2 alternative data selector.

Fig. 5 shows a block diagram of an alternative data selector in which one input is inverted.

Fig. 6 shows a block diagram of an alternative data selector according to an embodiment of the present invention.

Fig. 7 shows a CMOS circuit diagram of an alternative data selector according to an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments presents various details of particular embodiments of the invention. The invention may, however, be embodied in many different forms and covered by the claims. In this specification, like reference numbers may indicate identical or functionally similar elements.

The data selector is a device which transmits data of a plurality of channels to a unique common data channel through selection to realize a data selection function. The logical expression of the alternative data selector is

sel is the select signal, a0 is the first input, a1 is the second input. Fig. 1 shows a truth table of an alternative data selector, and fig. 2 shows a logic diagram of the alternative data selector. When the select signal sel is logic 0, the output X is the first input a 0. When the select signal sel is logic 1, the output X is the second input a 1.

Fig. 3 shows a block diagram of the MUX2 alternative data selector. As shown in FIG. 3, the MUX2 alternate data selector includes one AOI22 logic circuit and two inverter INV logic circuits. Input a0 receives a first input a0 and input a1 receives a second input a 1. The output of AOI22 logic circuit is

Thus, the output of the MUX2 alternate data selector is

The MUX2 alternative data selector occupies a large chip area, and has large delay and low speed.

Fig. 4 shows a block diagram of the MUXI2 alternative data selector. As shown in fig. 4, the MUXI2 alternative data selector includes an AOI22 logic circuit and an inverter INV logic circuit. Input A0 receives a first input a0, input A1 receives a second input a1, and output

Is the inverse of the output X in fig. 3. The MUXI2 alternative data selector has small delayBut in some cases the chip area occupied is still large.

Fig. 5 shows a block diagram of an alternative data selector in which one input is inverted. As shown in FIG. 5, the alternative data selector includes an AOI22 logic circuit and two inverter INV logic circuits. The input terminal A0 receives an inverted first input a0_ n (i.e., an inversion of a 0), the input terminal A1 receives a second input a1, and the output

Is the inverse of the output X in fig. 3. The alternative data selector also has the defects of large occupied chip area, large time delay and low speed.

For CMOS circuits, the natural output is inverted. If a non-inverting output is to be realized, an inverter needs to be added after the natural output. The utility model discloses utilize this characteristic of CMOS circuit, provide a novel circuit realization of alternative data selector, it does not need the phase inverter, thereby can reduce the quantity of the transistor of alternative data selector and reduce chip area.

Fig. 6 shows a block diagram of an alternative data selector according to an embodiment of the present invention. The alternative data selector in fig. 6 includes a nor logic circuit NR2 and an and or logic circuit AOI 21.

The nor logic circuit NR2 is configured to receive the select signal sel and the inverted first input a0 — n and to generate an intermediate result

The AND-OR logic circuit AOI21 is configured to receive the selection signal sel, the second input a1 and the intermediate result gn1 of the OR-OR logic circuit and generate an inverted output

Inverting the first input a0_ n is the inversion of the first input a0, i.e.

Further can obtain

That is to say that

That is, XN is the inverse of the output X.

Thus, in case the selection signal sel is a logic 0, the inverted output XN is the inverted first input

In case the selection signal sel is a logic 1, the inverted output XN is an inverted second input

Fig. 7 shows a CMOS circuit diagram of an alternative data selector according to an embodiment of the present invention.

As shown in fig. 7, the nor logic circuit NR2 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The gate terminal of the first PMOS transistor P1 is configured to receive a selection signal sel. The source terminal of the first PMOS transistor P1 is coupled to the power supply terminal VDD. The gate terminal of the second PMOS transistor P2 is configured to receive the inverted first input a0 — n, its source terminal is coupled to the drain terminal of the first PMOS transistor, and its drain terminal is coupled to the first node J1. The gate terminal of the first NMOS transistor N1 is configured to receive the selection signal sel and its drain terminal is coupled to the first node J1. The gate terminal of the second NMOS transistor N2 is configured to receive the inverted first input a0 — N and its drain terminal is coupled to the first node J1. The source terminal of each of the first NMOS transistor N1 and the second NMOS transistor N2 is coupled to the ground terminal VSS. The nor logic circuit NR2 is configured to generate an intermediate result gn1 at the first node J1.

The and or logic circuit AOI21 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The gate terminal of the third PMOS transistor P3 is configured to receive the intermediate result gn1 of the nor logic circuit. The source terminal of the third PMOS transistor P3 is coupled to the power supply terminal VDD. The gate terminal of the fourth PMOS transistor P4 is configured to receive a select signal sel, its source terminal is coupled to the drain terminal of the third PMOS transistor, and its drain terminal is coupled to the second node J2. The gate terminal of the fifth PMOS transistor P5 is configured to receive the second input a1, its source terminal is coupled to the drain terminal of the third PMOS transistor P3, and its drain terminal is coupled to the second node J2. The gate terminal of the third NMOS transistor N3 is configured to receive the intermediate result gn1 of the nor logic circuit and the drain terminal thereof is coupled to the second node J2. The gate terminal of the fourth NMOS transistor N4 is configured to receive the selection signal sel and the drain terminal thereof is coupled to the second node J2. The gate terminal of the fifth NMOS transistor N5 is configured to receive the second input a1 and its drain terminal is coupled to the source terminal of the fourth NMOS transistor N4. The source terminal of each of the third NMOS transistor N3 and the fifth NMOS transistor N5 is coupled to the ground terminal VSS. The and-or logic circuit AOI21 is configured to generate an inverted output XN at a second node J2.

The alternative data selector of the embodiment of the present invention is formed by combining a nor logic circuit NR2 and a nor logic circuit AOI 21. No inverter is needed in the whole circuit, so that the use of transistors is reduced, and the chip area is saved.

The alternative data selector of the present invention has been described above with reference to specific embodiments. However, it is to be understood that any feature of any one embodiment may be combined with and/or substituted for any other feature of any other embodiment.

Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of electronic devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headsets, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, Personal Digital Assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereos, DVD players, CD players, digital music players such as MP3 players, radios, camcorders, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer/dryers, peripherals, clocks, and the like. Further, the electronic device may include an incomplete product.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", "have", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense. That is, it means "including but not limited to". As generally used herein, the term "coupled" refers to two or more elements that may be connected directly or through one or more intermediate elements. Likewise, the term "connected," as used generally herein, refers to two or more elements that may be connected directly or through one or more intermediate elements. Additionally, as used in this application, the words "herein," "above," "below," "above," and words of similar import shall refer to this application as a whole and not to any particular portions of this application.

Furthermore, conditional language, e.g., "may," e.g., "such as" and the like, as used herein are generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or states, unless expressly stated otherwise or otherwise understood in the context of such usage. Thus, such conditional language is not generally intended to imply that features, elements, and/or states are in any way required for one or more embodiments or are included or performed in any particular embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The various features and processes described above may be implemented independently of one another or may be combined in various ways. All suitable combinations and subcombinations of the features of the disclosure are intended to be within the scope of the disclosure.

Claims (4)

1. An alternative data selector comprising:

a NOR logic circuit configured to receive a select signal and an inverted first input and to generate an intermediate result; and

and or logic circuitry configured to receive the select signal, a second input, and an intermediate result of the nor logic circuitry and to generate an inverted output.

2. The alternative data selector of claim 1,

in the case where the select signal is a logic 0, the inverted output is the inverted first input,

in case the selection signal is a logic 1, the inverted output is an inverted second input.

3. The alternative data selector of claim 1 wherein the nor logic circuit comprises:

a first PMOS transistor having a gate terminal configured to receive a selection signal, wherein a source terminal of the first PMOS transistor is coupled to a power supply terminal;

a second PMOS transistor having a gate terminal configured to receive the inverted first input, a source terminal coupled to the drain terminal of the first PMOS transistor, and a drain terminal coupled to the first node;

a first NMOS transistor having a gate terminal configured to receive a select signal and a drain terminal coupled to a first node; and

a second NMOS transistor having a gate terminal configured to receive the inverted first input and a drain terminal coupled to the first node, wherein a source terminal of each of the first and second NMOS transistors is coupled to a ground terminal,

wherein the NOR logic circuit is configured to produce an intermediate result at the first node.

4. The alternative data selector of claim 1 wherein the and or nor logic circuit comprises:

a third PMOS transistor having a gate terminal configured to receive an intermediate result of the nor logic circuit, wherein a source terminal of the third PMOS transistor is coupled to the power supply terminal;

a fourth PMOS transistor whose gate terminal is configured to receive the selection signal, whose source terminal is coupled to the drain terminal of the third PMOS transistor, and whose drain terminal is coupled to the second node;

a fifth PMOS transistor whose gate terminal is configured to receive the second input, whose source terminal is coupled to the drain terminal of the third PMOS transistor, and whose drain terminal is coupled to the second node;

a third NMOS transistor having a gate terminal configured to receive the intermediate result of the nor logic circuit and a drain terminal coupled to the second node;

a fourth NMOS transistor having a gate terminal configured to receive the selection signal and a drain terminal coupled to the second node; and

a fifth NMOS transistor having a gate terminal configured to receive the second input and a drain terminal coupled to a source terminal of the fourth NMOS transistor, wherein the source terminal of each of the third and fifth NMOS transistors is coupled to the ground terminal,

wherein the AND or NOR logic circuit is configured to produce an inverted output at the second node.

Images