CN212484194U - CMOS voltage reference source - Google Patents

Abstract

The utility model relates to a CMOS voltage reference source, include: the power supply comprises a band gap reference circuit, a power supply ripple suppression circuit and a soft start circuit; the input end of the power supply ripple suppression circuit is connected with an external input power supply voltage, the output end of the power supply ripple suppression circuit is connected with the input end of the band-gap reference circuit, the output end of the band-gap reference circuit outputs a reference voltage, and the soft start circuit is respectively connected with the external input power supply voltage and the band-gap reference circuit; the band-gap reference circuit is used for generating reference voltage, the power supply ripple suppression circuit is used for suppressing power supply ripples so that the band-gap reference circuit does not change along with the voltage of an external input power supply, and the soft start circuit converts the voltage stabilizing circuit from a zero-current working point state to a normal working point state. The utility model discloses have the operating voltage scope of broad, temperature drift inhibition ability and power ripple inhibition ability are good, and the circuit complexity is low, low power dissipation, and area occupied is little.

Description

CMOS voltage reference source

Technical Field

The utility model relates to an integrated circuit's technical field, more specifically say, relate to a CMOS voltage reference source.

Background

The CMOS voltage reference is an indispensable key module in a system chip and has wide application in various analog chips such as operational amplifier bias circuits, ADCs (analog-to-digital converters), power supply management and the like. In particular, in a high-precision sensing circuit, a precise bias circuit plays a crucial role in improving the performance of the whole system. In order to provide stable and high-precision biasing for the whole analog front-end circuit, the voltage reference circuit usually pursues two important design criteria: temperature drift suppression capability and power supply ripple suppression capability. Meanwhile, the complexity, power consumption and chip area of the voltage reference circuit are considered. As a general module, a great number of CMOS voltage reference circuit designs are available.

At present, the main implementation methods for the CMOS voltage reference circuit are as follows:

(1) conventional voltage reference circuits: as a classic voltage band-gap reference circuit, a triode and a resistor are used for temperature compensation, and meanwhile, an operational amplifier is used for error amplification to control an MOS current mirror above the triode so as to improve the output precision of band-gap voltage reference.

(2) Voltage reference circuit of subthreshold region: the MOS tube working in the subthreshold region can work in a lower power supply voltage and a lower bias current, so that a voltage reference circuit working at a low voltage can be designed, and the circuit power consumption is very low.

(3) Switched capacitor type bandgap reference circuit: the switched capacitor technology has the advantages of high matching precision and low static power consumption, and is widely applied to analog integrated circuits. Therefore, the voltage reference circuit designed by the switched capacitor technology can achieve a better level in both area and power consumption.

However, the conventional voltage reference circuit in the above (1) can satisfy basic application, and is suitable for an occasion with low system accuracy requirement, and the temperature drift suppression and power supply ripple suppression capabilities are general. The voltage reference circuit in the above (2) can operate under the condition of a power supply voltage lower than 1V, but since the bias current of the MOS transistor operating in the sub-threshold region is very small, it is very susceptible to the interference of transistor leakage current, circuit noise or other noise. Meanwhile, the MOS transistor in the sub-threshold region is extremely sensitive in working state and is easy to separate from the sub-threshold region under interference, so that the circuit is ineffective. The power supply voltage noise rejection capability is crossed. The voltage reference circuit in the aforementioned (3), although being superior in terms of chip area and power consumption, has an effect on the output of the reference voltage due to switching noise introduced in common and the charge feedthrough effect of the MOS switch, and is also inferior in power supply voltage ripple suppression capability.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the present invention is to provide a CMOS voltage reference source for the above-mentioned defects of the prior art.

The utility model provides a technical scheme that its technical problem adopted is: constructing a CMOS voltage reference source comprising: the power supply comprises a band gap reference circuit, a power supply ripple suppression circuit and a soft start circuit;

the input end of the power supply ripple suppression circuit is connected with an external input power supply voltage, the output end of the power supply ripple suppression circuit is connected with the input end of the band-gap reference circuit, the output end of the band-gap reference circuit outputs a reference voltage, and the soft start circuit is respectively connected with the external input power supply voltage and the band-gap reference circuit;

the band-gap reference circuit is used for generating reference voltage, the power supply ripple suppression circuit is used for suppressing power supply ripples so that the band-gap reference circuit does not change along with the voltage of the external input power supply, and the soft start circuit converts the voltage stabilizing circuit from a zero-current working point state to a normal working point state.

In one embodiment, the bandgap reference circuit comprises: a reference voltage generating circuit and a voltage reference output circuit;

the input end of the reference voltage generating circuit is connected with the output end of the power supply ripple suppression circuit, the output end of the reference voltage generating circuit is connected with the input end of the voltage reference output circuit, and the output end of the voltage reference output circuit outputs the reference voltage;

the input end of the reference voltage generating circuit is the input end of the band-gap reference circuit, and the output end of the voltage reference output circuit is the output end of the band-gap reference circuit.

In one embodiment, the reference voltage generating circuit includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first triode, a second triode and a first resistor;

the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the output end of the voltage reference output circuit is connected with the output end of the power supply ripple suppression circuit, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the emitting electrode of the first triode, the collector electrode of the first triode is grounded, the base electrode of the first triode is in short circuit with the base electrode of the second triode and is connected to the ground, the collector electrode of the second triode is grounded, and the emitting electrode of the second triode is connected with the source electrode of the second NMOS tube through the first resistor;

the grid electrode of the second NMOS tube is in short circuit with the grid electrode of the first NMOS tube and is connected to the soft start circuit together with the drain electrode of the first NMOS tube; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube;

and the grid electrode and the drain electrode of the second PMOS tube are in short circuit and are respectively connected with the input ends of the power supply ripple suppression circuit and the voltage reference output circuit.

In one embodiment, the voltage reference output circuit includes: the third PMOS tube, the fourth PMOS tube, the second resistor and the third triode;

the source electrode of the third PMOS tube is used as the input end of the voltage reference circuit and is connected with the output end of the power supply ripple suppression circuit, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube and is connected to the power supply ripple suppression circuit; the grid electrode of the third PMOS tube is also used as the output end of the voltage reference circuit and is connected to the soft start circuit;

the grid electrode and the drain electrode of the fourth PMOS tube are in short circuit, the drain electrode of the fourth PMOS tube is connected with the emitting electrode of the third triode through the second resistor, and the base electrode and the collector electrode of the third triode are grounded;

and the connection end of the drain electrode of the fourth PMOS tube and the second resistor is used as the output end of the band-gap reference circuit to output the reference voltage.

In one embodiment, the power supply ripple suppression circuit includes: and the embedded amplifier is connected with the band-gap reference circuit.

In one embodiment, the power supply ripple suppression circuit further comprises: a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube;

the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube are connected with the external input power supply voltage, the grid electrode of the seventh PMOS tube is in short circuit with the grid electrode of the eighth PMOS tube, the grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is used as the output end of the power supply ripple suppression circuit and is connected with the input end of the band-gap reference circuit;

the drain electrode of the seventh NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the grid electrode of the seventh NMOS tube is connected with the embedded amplifier; the source electrode of the seventh NMOS tube is grounded; the grid electrode of the eighth NMOS tube is connected with the embedded amplifier, the source electrode of the eighth NMOS tube is connected with the drain electrode of the ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the embedded amplifier, and the source electrode of the ninth NMOS tube is grounded.

In one embodiment, the embedded amplifier comprises: a fifth PMOS tube, a sixth PMOS tube, a first capacitor, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the drain electrode of the eighth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the gate electrode of the seventh NMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the fifth PMOS tube is also connected with the drain electrode of the seventh NMOS tube through the first capacitor;

the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the sixth PMOS tube is connected with the connecting ends of the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube; the drain electrode of the sixth PMOS tube is connected with the first end of the embedded resistor, and the drain electrode of the sixth PMOS tube is also connected with the grid electrode of the eighth NMOS tube, the grid electrode of the third NMOS tube and the connecting end of the grid electrodes of the fourth NMOS tube and the fourth NMOS tube;

the second end of the embedded resistor is connected with the drain electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the sixth NMOS tube and the source electrode of the fifth NMOS tube are grounded; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube and is connected to the grid electrode of the ninth NMOS tube and the drain electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube.

In one embodiment, the soft start circuit includes: and the bias circuit is connected with the external input power supply voltage and provides bias for the soft start circuit.

In one embodiment, the soft start circuit further comprises: a ninth PMOS tube, a tenth PMOS tube and an eleventh PMOS tube;

the source electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are connected with the external input power supply voltage, the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube;

the drain electrode of the ninth PMOS tube is connected with the drain electrode of the first NMOS tube and the connecting end of the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the bias circuit.

In one embodiment, the bias circuit includes: a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a tenth NMOS tube and an eleventh NMOS tube;

the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube are sequentially connected in series in an inverted ratio manner, the source electrode of the twelfth PMOS tube is connected with the external input power supply voltage, the drain electrode of the fifteenth PMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the eleventh NMOS tube is in short circuit with the grid electrode of the eleventh NMOS tube;

the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube are grounded together, and the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube.

Implement the utility model discloses a CMOS voltage reference source has following beneficial effect: the method comprises the following steps: the power supply comprises a band gap reference circuit, a power supply ripple suppression circuit and a soft start circuit; the input end of the power supply ripple suppression circuit is connected with an external input power supply voltage, the output end of the power supply ripple suppression circuit is connected with the input end of the band-gap reference circuit, the output end of the band-gap reference circuit outputs a reference voltage, and the soft start circuit is respectively connected with the external input power supply voltage and the band-gap reference circuit; the band-gap reference circuit is used for generating reference voltage, the power supply ripple suppression circuit is used for suppressing power supply ripples so that the band-gap reference circuit does not change along with the voltage of an external input power supply, and the soft start circuit converts the band-gap reference circuit from a zero-current working point state to a normal working point state. The utility model discloses have the operating voltage scope of broad, power ripple rejection is good, and the circuit complexity is low, and the low power dissipation, and area occupied is little.

Drawings

The invention will be further explained with reference to the drawings and examples, wherein:

fig. 1 is a schematic structural diagram of a CMOS voltage reference source according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of a CMOS voltage reference source according to an embodiment of the present invention.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a CMOS voltage reference source provided by an embodiment of the present invention, which can be widely applied to analog chips such as an operational amplifier bias circuit, an ADC, and a power management.

Specifically, as shown in fig. 1, the CMOS voltage reference source includes: a bandgap reference circuit 20, a power supply ripple rejection circuit 10, and a soft start circuit 30.

The input end of the power supply ripple suppression circuit 10 is connected with an external input power supply voltage, the output end of the power supply ripple suppression circuit 10 is connected with the input end of the band-gap reference circuit 20, the output end of the band-gap reference circuit 20 outputs a reference voltage, and the soft start circuit 30 is respectively connected with the external input power supply voltage and the band-gap reference circuit 20; the band-gap reference circuit 20 is used for generating a reference voltage, the power supply ripple suppression circuit 10 is used for suppressing power supply ripples so that the band-gap reference circuit 20 does not change with an externally input power supply voltage, and the soft start circuit 30 converts the voltage stabilizing circuit from a zero-current operating point state to a normal operating point state.

In the present embodiment, the bandgap reference circuit 20 includes: a reference voltage generating circuit and a voltage reference output circuit.

The input end of the reference voltage generating circuit is connected with the output end of the power supply ripple suppression circuit 10, the output end of the reference voltage generating circuit is connected with the input end of the voltage reference output circuit, and the output end of the voltage reference output circuit outputs reference voltage; the input end of the reference voltage generating circuit is the input end of the bandgap reference circuit 20, and the output end of the voltage reference output circuit is the output end of the bandgap reference circuit 20.

Referring to fig. 2, fig. 2 is a circuit diagram of a CMOS voltage reference source according to an embodiment of the present invention. As shown in fig. 2, VDD is the external input power voltage, and GND is ground (i.e., power reference ground).

As shown in fig. 2, the reference voltage generating circuit includes: the transistor comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2, a first triode Q1, a second triode Q2 and a first resistor R1.

The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected and the output of the voltage reference output circuit is connected to the output of the power ripple suppression circuit 10, the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, the source of the first NMOS transistor MN1 is connected to the emitter of the first triode Q1, the collector of the first triode Q1 is grounded, the base of the first triode Q1 is shorted to the base of the second triode Q2 and connected to ground, the collector of the second triode Q2 is grounded, and the emitter of the second triode Q2 is connected to the source of the second NMOS transistor Q2 through the first resistor R1; the grid electrode of the second NMOS transistor MN2 is in short circuit with the grid electrode of the first NMOS transistor MN1 and is connected to the soft start circuit 30 together with the drain electrode of the first NMOS transistor MN 1; the drain electrode of the second NMOS transistor MN2 is connected with the drain electrode of the second PMOS transistor MP 2; the gate of the second PMOS transistor MP2 is shorted with the drain thereof and is connected to the input terminals of the power ripple rejection circuit 10 and the voltage reference output circuit, respectively.

Further, as shown in fig. 2, the voltage reference output circuit includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second resistor R2, and a third transistor Q3.

The source of the third PMOS transistor MP3 is connected to the output of the power supply ripple suppression circuit 10 as the input of the voltage reference circuit, the drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4, and the gate of the third PMOS transistor MP3 is connected to the drain of the second PMOS transistor MP2 and connected to the power supply ripple suppression circuit 10; the grid electrode of the third PMOS transistor MP3 is also used as the output end of the voltage reference circuit and connected to the soft start circuit 30; the grid electrode and the drain electrode of the fourth PMOS pipe MP4 are in short circuit, the drain electrode of the fourth PMOS pipe MP4 is connected with the emitting electrode of the third triode Q3 through a second resistor R2, and the base electrode and the collector electrode of the third triode Q3 are grounded; the connection end of the drain of the fourth PMOS transistor MP4 and the second resistor R2 serves as the output end of the bandgap reference circuit 20 for outputting the reference voltage.

In this embodiment, the reference voltage generating circuit is independent of temperature. In this embodiment, the design principle of the reference voltage generating circuit is that voltages with opposite temperature coefficients are linearly superimposed with appropriate weights, and a reference voltage with a zero temperature coefficient is reached at a certain temperature, thereby obtaining a reference voltage that does not substantially change with temperature. The negative temperature coefficient voltage is generated by base-emitter voltages of a first triode Q1 and a second triode Q2 of the PNP, and the positive temperature coefficient voltage is generated by a base-emitter voltage difference delta VBE generated by a first triode Q1 and a second triode Q2 which work under different current densities.

Wherein the current proportional to temperature is:

in the above formula, V_BE1Is the base-emitter voltage, V, of the first transistor Q1_BE2Is the base-emitter voltage of the second transistor Q2, R1 is the resistance of the first resistor R1, KT/Q is the coefficient, and n is the area ratio of the first transistor Q1 to the second transistor Q2.

The voltage reference output circuit consists of a third PMOS tube MP3, a fourth PMOS tube MP4, a third triode Q3 and a second resistor R2, and the output band gap voltage is as follows:

in the above formula, Vref is the reference voltage output by the bandgap reference circuit 20, VBE3 is the base-emitter voltage of the third transistor Q3, and R2 is the resistance of the second resistor R2.

Combining (formula 1) and (formula 2) can result in:

as can be seen from equation (3), by setting the area ratio n between the first transistor Q1 and the second transistor Q2 and the resistances of the second resistor R2 and the first resistor R1, the voltage reference output (i.e., the reference voltage output) after temperature compensation can be obtained.

The embodiment of the utility model provides an in, because whole voltage reference circuit has adopted the inside feedback mechanism, consequently, band gap reference circuit 20 does not adopt the bars cascade structure altogether that uses in mainstream band gap reference circuit 20, has avoided the mainstream to grid cascade structure altogether and has consumed extra MOS pipe overdrive voltage and cause the higher problem of mains voltage of normal work.

In addition, the reference voltage output by the bandgap reference circuit 20 of the present invention is lower than the power voltage by at least 3 overdrive voltages, so that the power voltage can operate under the condition of lower than 1.8V. Of course, the power supply voltage as low as about 1.5V or even lower can be realized by reasonable design in the embodiment.

Further, the power supply ripple suppression circuit 10 of the present embodiment includes: an embedded amplifier connected to a bandgap reference circuit 20.

As shown in fig. 2, the power supply ripple suppression circuit 10 further includes: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN 9.

The source electrode of the seventh PMOS transistor MP7 and the source electrode of the eighth PMOS transistor MP8 are connected to an external input power supply voltage, the gate electrode of the seventh PMOS transistor MP7 is shorted with the gate electrode of the eighth PMOS transistor MP8, the gate electrode of the seventh PMOS transistor MP7 is connected to the drain electrode thereof, and the drain electrode of the eighth PMOS transistor MP8 serves as the output end of the power supply ripple suppression circuit 10 and is connected to the input end of the bandgap reference circuit 20; the drain electrode of the seventh NMOS transistor MN7 is connected with the drain electrode of the eighth PMOS transistor MP8, and the gate electrode of the seventh NMOS transistor MN7 is connected with the embedded amplifier; the source electrode of the seventh NMOS transistor MN7 is grounded; the grid electrode of the eighth NMOS transistor MN8 is connected with the embedded amplifier, the source electrode of the eighth NMOS transistor MN8 is connected with the drain electrode of the ninth NMOS transistor MN9, the grid electrode of the ninth NMOS transistor MN9 is connected with the embedded amplifier, and the source electrode of the ninth NMOS transistor MN9 is grounded.

Further, as shown in fig. 2, the embedded amplifier includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first capacitor C1, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN 6.

A source electrode of the fifth PMOS transistor MP5 and a source electrode of the sixth PMOS transistor MP6 are connected to a drain electrode of the eighth PMOS transistor MP8, a drain electrode of the fifth PMOS transistor MP5 is connected to a gate electrode of the seventh NMOS transistor MN7 and a drain electrode of the third NMOS transistor MN3, and a drain electrode of the fifth PMOS transistor MP5 is further connected to a drain electrode of the seventh NMOS transistor MN7 through a first capacitor C1; the grid electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the first PMOS tube MP1, and the grid electrode of the sixth PMOS tube MP6 is connected with the connecting ends of the grid electrode of the first PMOS tube MP1 and the grid electrode of the second PMOS tube MP 2; the drain electrode of the sixth PMOS transistor MP6 is connected to the first end of the embedded resistor, and the drain electrode of the sixth PMOS transistor MP6 is further connected to the gate electrode of the eighth NMOS transistor MN8, the gate electrode of the third NMOS transistor MN3, and the connection end of the gate electrode of the fourth NMOS transistor; the second end of the embedded resistor is connected with the drain electrode of a fourth NMOS transistor MN4, the drain electrode of a fourth NMOS transistor MN4 is connected with the drain electrode of a sixth NMOS transistor MN6, and the source electrode of the sixth NMOS transistor MN6 and the source electrode of a fifth NMOS transistor MN5 are grounded; the grid electrode of the fifth NMOS tube MN5 is connected with the grid electrode of the sixth NMOS tube MN6 and is connected to the grid electrode of the ninth NMOS tube MN9 and the drain electrode of the fourth NMOS tube MN4, the drain electrode of the fifth NMOS tube MN5 is connected with the source electrode of the third NMOS tube MN3, and the grid electrode of the third NMOS tube MN3 is connected with the grid electrode of the fourth NMOS tube MN 4.

As can be seen from fig. 2, the bandgap reference circuit 20 is set to operate at the internal calibration voltage Vreg (i.e., the eighth PMOS transistor MP8), and the high-gain feedback loop ensures that the drain potential of the first PMOS transistor MP1 is the same as the gate potential of the second PMOS transistor MP2, so as to adjust Vreg (i.e., the drain voltage of the eighth PMOS transistor MP8) to be substantially unchanged with the supply voltage, and finally, the bandgap reference circuit 20 operating at the internal voltage has a higher supply rejection ratio.

Specifically, the suppression principle of the power supply ripple suppression circuit 10 of the present embodiment is as follows: assume that the drain voltage (i.e., Vreg) of the eighth PMOS transistor MP8 is increased by the change (i.e., increase) of the external input power voltage VDD, so that the current flowing through the first transistor Q1 and the second transistor Q2 and the relative values of the drain potential of the first PMOS transistor MP1 and the gate potential of the second PMOS transistor MP2 are changed. The variation of the drain potential of the first PMOS transistor MP1 and the gate potential of the second PMOS transistor MP2 is amplified by the embedded amplifier formed by the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6, so that the gate potential of the seventh NMOS transistor MN7 is increased, and finally the drain voltage of the eighth PMOS transistor MP8 is decreased by the feedback current generated by the seventh NMOS transistor MN7 to maintain the required correct voltage. The embedded amplifier is a diode amplifier, and the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 form a common gate cascode cascaded structure, so that the gain of the embedded amplifier has a very high open-loop gain. The first capacitor C1 acts as a miller compensation capacitor, making the embedded amplifier highly stable. Through the internal high-gain feedback mechanism, the circuit can ensure that the gate-drain voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 are stable and equal, so that the Vreg voltage can be kept stable and does not change with the change of the external input power supply Voltage (VDD).

In addition, in this embodiment, the feedback mechanism ensures that the current of the first transistor Q1 and the current of the second transistor Q2 relatively change little, and the output Vref dc current is a current mirror image formed by the third PMOS transistor MP3 and the second PMOS transistor MP2, so that the Vref branch current can be kept stable, and the Vref output has a high capability of suppressing the change of the power supply VDD.

In this embodiment, the soft start circuit 30 includes: a bias circuit connected to an external input power supply voltage to bias the soft-start circuit 30.

Further, the soft-start circuit 30 further includes: a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, and an eleventh PMOS transistor MP 11.

A source electrode of the ninth PMOS transistor MP9, a source electrode of the tenth PMOS transistor MP10, and a source electrode of the eleventh PMOS transistor MP11 are connected to an external input power supply voltage, a gate electrode of the eleventh PMOS transistor MP11 is connected to a gate electrode of the third PMOS transistor MP3, and a drain electrode of the eleventh PMOS transistor MP11 is connected to a drain electrode of the tenth PMOS transistor MP 10; the drain of the ninth PMOS transistor MP9 is connected to the connection end of the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1 to the gate of the second NMOS transistor MN2, the gate of the ninth PMOS transistor MP9 is connected to the gate of the tenth PMOS transistor MP10, the gate of the tenth PMOS transistor MP10 is connected to the drain thereof, and the drain of the tenth PMOS transistor MP10 is connected to the bias circuit.

In this embodiment, the bias circuit includes: a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN 11.

A twelfth PMOS tube MP12, a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14 and a fifteenth PMOS tube MP15 are sequentially connected in series in an inverted ratio manner, the source electrode of the twelfth PMOS tube MP12 is connected with an external input power voltage, the drain electrode of the fifteenth PMOS tube MP15 is connected with the drain electrode of an eleventh NMOS tube MN11, and the drain electrode of the eleventh NMOS tube MN11 is in short circuit with the grid electrode thereof; the source of the tenth NMOS transistor MN10 and the source of the eleventh NMOS transistor MN11 are commonly grounded, and the gate of the tenth NMOS transistor MN10 and the gate of the eleventh NMOS transistor MN11 are connected.

The soft start circuit 30 of the present embodiment mainly functions to convert the bandgap reference circuit 20 from a zero-current operating point state to a normal operating point state of the circuit, so as to avoid that the circuit enters a steady state of a zero state after being powered on and cannot realize circuit start.

Further, the bias circuit provides a bias to the soft start circuit 30, wherein the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15 are connected in series by four inverting transistors to obtain a large resistance, so that the circuit has a very low quiescent current.

Specifically, the soft start circuit 30 operates according to the following principle: when the voltage regulator circuit is powered on, if the voltage regulator circuit cannot work normally, the whole bias circuit generates zero current, and at this time, the gate voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 are low, and the gate voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 are high, so that the eleventh PMOS transistor MP11 in the soft start circuit 30 is turned off. When the circuit is powered on, the current mirror formed by the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 starts to operate through the self-bias circuit of the soft start circuit 30, so as to cause the first NMOS transistor MN1 and the second NMOS transistor MN2 to operate, and thus the bandgap reference circuit 20 starts to operate. Meanwhile, the gate voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 decrease, so that the eleventh PMOS transistor MP11 is turned on, and through the design of the circuit, the current that can flow through the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 caused by the eleventh PMOS transistor MP11 is almost zero, thereby turning off the soft start circuit 30. In the bias circuit of the soft start circuit 30, the current itself is extremely small (in the order of nanoamperes) due to the zener diode connected in series with a plurality of diodes. Therefore, the power consumption of the soft start circuit 30 after normal start is extremely small, and the current in the bandgap reference circuit 20 can be in the micro-ampere level, so that the power consumption of the whole voltage stabilizing circuit can reach the micro-watt level.

In other embodiments, the embodiment of the utility model provides a can adopt the high-pressure MOS pipe to realize, also can change the structure of embedded amplifier in the inside feedback control, for example adopt inside OTA amplifier to realize inside feedback control. In addition, in the bandgap reference circuit 20, a conventional common-gate cascaded PMOS transistor may be used to replace the first PMOS transistor MP1 and the second PMOS transistor MP2 in fig. 2. Similarly, the first NMOS transistor MN1 and the first NMOS transistor MN1 in the bandgap reference circuit 20 may be replaced by conventional common-gate cascaded NMOS transistors. The soft start circuit 30 may adopt other forms of modification to implement circuit start. Can realize equally based on such design the utility model relates to an effect and performance that promote mains voltage ripple and restrain.

It should be noted that the present invention is designed based on lower voltage and frequency, but the architecture and design principle thereof are suitable for the voltage reference circuit design applied in other application scenarios, such as high voltage power supply chip and high frequency circuit power supply chip.

The utility model discloses circuit structure is simple, can provide the reference voltage to the temperature drift and the high rejection ability of mains voltage ripple, has low circuit consumption and small-size chip area simultaneously. The power supply ripple suppression circuit 10 based on the internal high-gain feedback mechanism can obtain stronger power supply ripple suppression capability. In addition, the band gap reference circuit 20 of the present invention can normally operate under a voltage lower than 1.8V, even 1.5V, within the operating voltage range. Moreover, the circuit adopts low bias current, and has low static power consumption while realizing higher performance; the circuit has few components and small size, and is easy to realize single chip integration under a standard CMOS process and a high-voltage CMOS process.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and implement the present invention accordingly, which can not limit the protection scope of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention shall fall within the scope of the claims of the present invention.

Claims (10)

1. A CMOS voltage reference source, comprising: the power supply comprises a band gap reference circuit, a power supply ripple suppression circuit and a soft start circuit;

the input end of the power supply ripple suppression circuit is connected with an external input power supply voltage, the output end of the power supply ripple suppression circuit is connected with the input end of the band-gap reference circuit, the output end of the band-gap reference circuit outputs a reference voltage, and the soft start circuit is respectively connected with the external input power supply voltage and the band-gap reference circuit;

the band-gap reference circuit is used for generating reference voltage, the power supply ripple suppression circuit is used for suppressing power supply ripples so that the band-gap reference circuit does not change along with the voltage of the external input power supply, and the soft start circuit converts the CMOS voltage reference source from a zero-current working point state to a normal working point state.

2. The CMOS voltage reference source of claim 1, wherein the bandgap reference circuit comprises: a reference voltage generating circuit and a voltage reference output circuit;

the input end of the reference voltage generating circuit is connected with the output end of the power supply ripple suppression circuit, the output end of the reference voltage generating circuit is connected with the input end of the voltage reference output circuit, and the output end of the voltage reference output circuit outputs the reference voltage;

the input end of the reference voltage generating circuit is the input end of the band-gap reference circuit, and the output end of the voltage reference output circuit is the output end of the band-gap reference circuit.

3. The CMOS voltage reference source of claim 2, wherein the reference voltage generation circuit comprises: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first triode, a second triode and a first resistor;

the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the output end of the voltage reference output circuit is connected with the output end of the power supply ripple suppression circuit, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the emitting electrode of the first triode, the collector electrode of the first triode is grounded, the base electrode of the first triode is in short circuit with the base electrode of the second triode and is connected to the ground, the collector electrode of the second triode is grounded, and the emitting electrode of the second triode is connected with the source electrode of the second NMOS tube through the first resistor;

the grid electrode of the second NMOS tube is in short circuit with the grid electrode of the first NMOS tube and is connected to the soft start circuit together with the drain electrode of the first NMOS tube; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube;

and the grid electrode and the drain electrode of the second PMOS tube are in short circuit and are respectively connected with the input ends of the power supply ripple suppression circuit and the voltage reference output circuit.

4. The CMOS voltage reference source of claim 3, wherein said voltage reference output circuit comprises: the third PMOS tube, the fourth PMOS tube, the second resistor and the third triode;

the source electrode of the third PMOS tube is used as the input end of the voltage reference circuit and is connected with the output end of the power supply ripple suppression circuit, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube and is connected to the power supply ripple suppression circuit; the grid electrode of the third PMOS tube is also used as the output end of the voltage reference circuit and is connected to the soft start circuit;

the grid electrode and the drain electrode of the fourth PMOS tube are in short circuit, the drain electrode of the fourth PMOS tube is connected with the emitting electrode of the third triode through the second resistor, and the base electrode and the collector electrode of the third triode are grounded;

and the connection end of the drain electrode of the fourth PMOS tube and the second resistor is used as the output end of the band-gap reference circuit to output the reference voltage.

5. The CMOS voltage reference source of claim 4, wherein said power supply ripple rejection circuit comprises: and the embedded amplifier is connected with the band-gap reference circuit.

6. The CMOS voltage reference source of claim 5, wherein said power supply ripple rejection circuit further comprises: a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube;

the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube are connected with the external input power supply voltage, the grid electrode of the seventh PMOS tube is in short circuit with the grid electrode of the eighth PMOS tube, the grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is used as the output end of the power supply ripple suppression circuit and is connected with the input end of the band-gap reference circuit;

the drain electrode of the seventh NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the grid electrode of the seventh NMOS tube is connected with the embedded amplifier; the source electrode of the seventh NMOS tube is grounded; the grid electrode of the eighth NMOS tube is connected with the embedded amplifier, the source electrode of the eighth NMOS tube is connected with the drain electrode of the ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the embedded amplifier, and the source electrode of the ninth NMOS tube is grounded.

7. The CMOS voltage reference source of claim 6, wherein said embedded amplifier comprises: a fifth PMOS tube, a sixth PMOS tube, a first capacitor, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the drain electrode of the eighth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the gate electrode of the seventh NMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the fifth PMOS tube is also connected with the drain electrode of the seventh NMOS tube through the first capacitor;

the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the sixth PMOS tube is connected with the connecting ends of the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube; the drain electrode of the sixth PMOS tube is connected with the first end of the embedded resistor, and the drain electrode of the sixth PMOS tube is also connected with the grid electrode of the eighth NMOS tube, the grid electrode of the third NMOS tube and the connecting end of the grid electrodes of the fourth NMOS tube and the fourth NMOS tube;

the second end of the embedded resistor is connected with the drain electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the sixth NMOS tube and the source electrode of the fifth NMOS tube are grounded; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube and is connected to the grid electrode of the ninth NMOS tube and the drain electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube.

8. The CMOS voltage reference source of claim 7, wherein the soft start circuit comprises: and the bias circuit is connected with the external input power supply voltage and provides bias for the soft start circuit.

9. The CMOS voltage reference source of claim 8, wherein the soft start circuit further comprises: a ninth PMOS tube, a tenth PMOS tube and an eleventh PMOS tube;

the source electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are connected with the external input power supply voltage, the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube;

the drain electrode of the ninth PMOS tube is connected with the drain electrode of the first NMOS tube and the connecting end of the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the bias circuit.

10. The CMOS voltage reference source of claim 9, wherein the biasing circuit comprises: a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a tenth NMOS tube and an eleventh NMOS tube;

the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube are sequentially connected in series in an inverted ratio manner, the source electrode of the twelfth PMOS tube is connected with the external input power supply voltage, the drain electrode of the fifteenth PMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the eleventh NMOS tube is in short circuit with the grid electrode of the eleventh NMOS tube;

the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube are grounded together, and the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube.

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