CN212484123U

CN212484123U - HART protocol communication circuit

Info

Publication number: CN212484123U
Application number: CN202021420829.4U
Authority: CN
Inventors: 张锦华
Original assignee: Beijing Ripeness Sanyuan Instrumentation Co ltd
Current assignee: Beijing Ripeness Sanyuan Instrumentation Co ltd
Priority date: 2019-12-11
Filing date: 2020-07-17
Publication date: 2021-02-05
Anticipated expiration: 2030-07-17

Abstract

The utility model discloses a HART protocol communication circuit, including master control circuit. And the main control circuit receives command signals sent by each sensor on site. The main control circuit is connected with the filter circuit through the analog switch, the main control circuit is connected with the HART modulation and demodulation circuit, the filter circuit and the HART modulation and demodulation circuit are respectively connected with the D/A conversion superposition circuit, the D/A conversion superposition circuit is connected with the HART modulation and demodulation circuit through the 4-20 mA loop circuit, the HART modulation and demodulation circuit is connected with the main control circuit through the carrier detection circuit, and data sending and receiving can be carried out between the main control circuit and the HART modulation and demodulation circuit. The utility model discloses can become the instruction signal of all kinds of sensor output in scene and send, and with low costs, be suitable for the popularization.

Description

HART protocol communication circuit

Technical Field

The utility model relates to a HART communication circuit for transmitting sensor command signal.

Background

The HART protocol is an open communication protocol for mutual communication between field smart instruments and control room devices, which requires a relatively narrow bandwidth and a moderate response time, so that the HART technology has matured at home and abroad through years of development and has become an industrial standard for global smart instruments. The HART technology is characterized in that modulated industrial standard digital signals are superposed on 4-20 mA analog signals for transmission, and the HART technology has the advantages that analog measurement values obtained by field tests and communication and non-cyclic transmission of bidirectional digital signals are combined, so that field diagnosis, maintenance and process information transmission to a control room system of a higher level are possible. At present, most industrial field instruments require HART protocol communication capability, but the industrial field instruments are realized by chips with HART protocol communication capability, the chip is very high in price, is not beneficial to improving the competitiveness of products, and is not suitable for popularization and promotion.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a HART protocol communication circuit, it can be with the output of all kinds of sensors on-the-spot through various command signal transmitting, and with low costs, is suitable for the popularization.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a HART protocol communication circuit, characterized in that: it includes master control circuit, DA conversion stack circuit, 4 ~ 20mA return circuit, HART modem circuit and carrier wave detection circuit, wherein: the main control circuit receives command signals sent by each sensor on site; the square wave signal output end of the master control circuit is connected with the input end of the filter circuit through the analog switch, the instruction level signal transmission end of the master control circuit is connected with the instruction level signal transmission end of the HART modulation and demodulation circuit, the filter signal output end of the filter circuit and the frequency signal output end of the HART modulation and demodulation circuit are respectively connected with the two input ends of the D/A conversion superposition circuit, the superposition output end of the D/A conversion superposition circuit is connected with the feedback signal end of the HART modulation and demodulation circuit through a 4-20 mA loop circuit, the detection signal end of the HART modulation and demodulation circuit is connected with the detection result receiving end of the master control circuit through a carrier detection circuit, and the data sending receiving end of the master control circuit is connected with the data sending receiving end of the HART.

The utility model has the advantages that:

the utility model discloses satisfying and carrying out the basis that the transmission was carried out with the constant current form with all kinds of sensor output on the scene through various command signal on, reduced product cost by a wide margin with the mode of low-cost hardware circuit, be suitable for popularization and popularization.

Drawings

Fig. 1 is a block diagram of the present invention.

Fig. 2 is a circuit schematic of the master control circuit.

Fig. 3 is a circuit schematic diagram of a filter circuit and a D/a conversion superimposing circuit.

Fig. 4 is a circuit schematic of a HART modem circuit.

Fig. 5 is a circuit schematic of the carrier sense circuit.

FIG. 6 is a schematic circuit diagram of a 4-20 mA loop circuit.

Detailed Description

As shown in fig. 1 to fig. 6, the HART protocol communication circuit of the present invention comprises a main control circuit 10, a da conversion superposition circuit 40, a 4-20 mA loop circuit 50, a HART modulation and demodulation circuit 60 and a carrier detection circuit 70, wherein: the main control circuit 10 receives the instruction signals sent by the sensors 90 after analog-to-digital conversion, that is, the signal receiving end of the main control circuit 10 is connected with the signal sending end of each sensor 90 on the site; the square wave signal output end of the main control circuit 10 is connected with the input end of the filter circuit 30 through the analog switch 20, the instruction level signal transmission end of the main control circuit 10 is connected with the instruction level signal transmission end of the HART modulation and demodulation circuit 60, the filter signal output end of the filter circuit 30 and the frequency signal output end of the HART modulation and demodulation circuit 60 are respectively connected with two input ends of the D/a conversion superposition circuit 40, the superposition output end of the D/a conversion superposition circuit 40 is connected with the feedback signal end of the HART modulation and demodulation circuit 60 through the 4-20 mA loop circuit 50, the detection signal end of the HART modulation and demodulation circuit 60 is connected with the detection result receiving end of the main control circuit 10 through the carrier detection circuit 70, and the data sending and receiving end of the main control circuit 10 is connected with the data sending and receiving end of the HART modulation.

The sensor 90 is a field-ready device that has analog-to-digital conversion capability or is equipped with analog-to-digital conversion means, which are well known in the art and not described in detail herein.

As shown in fig. 2, the main control circuit 10 includes a single-chip microcomputer U9, wherein: the singlechip U9 is LPC series singlechip.

As shown in fig. 2, the analog switch 20 employs an analog switch U10 of the chip SGM 3157.

In practical design, the filter circuit 30 is composed of 4 stages of RC filter circuits, such as four stages of filtering realized by the resistor R24 and the capacitor C29, the resistor R25 and the capacitor C30, the resistor R26 and the capacitor C31, and the resistor R27 and the capacitor C32 in fig. 3.

As shown in fig. 3, the D/a conversion superposition circuit 40 is constructed by using a separate element, and includes a voltage follower composed of a plurality of operational amplifiers U7B, U7A, and U6B, a plurality of resistors, and a plurality of capacitors. For example, fig. 3 shows a case where the D/a conversion superimposing circuit 40 is configured by two operational amplifiers OPA2336E (U7B, U7A) and one operational amplifier OPA2348(U6B) together with a resistor and a capacitor.

As shown in fig. 6, the 4-20 mA loop circuit 50 includes a current loop generator U3, an IO pin of the current loop generator U3 is divided into two paths, one path is connected to a power supply BATT through an anti-interference circuit formed by an anti-interference resistor EMI1, an EMI2, and voltage regulators D1 and D2 to provide power, the other path is connected in parallel with an output terminal (collector) of a transistor T1 connected to a pin B and a pin E of the current loop generator U3 and then connected to a feedback signal terminal of the HART modulation and demodulation circuit 60 through a feedback filter circuit, and an IIN pin of the current loop generator U3 receives an analog signal Uda output by the D/a conversion superposition circuit 40, where: the current loop generator U3 adopts an XTR115 chip; the feedback filter circuit includes an operational amplifier U5A, i.e., an operational amplifier U5A, a resistor and a capacitor as shown in fig. 6.

As shown in fig. 4, the HART modem circuit 60 is used for analog modem process, and includes a mixed signal processor U2, the mixed signal processor U2 receives a crystal oscillator signal sent by the single chip U9 of the main control circuit 10 as a reference, wherein: the mixed signal processor U2 adopts an MSP430 series single chip microcomputer, and each IO pin of the MSP430 series single chip microcomputer is used for being connected with corresponding terminals of the main control circuit 10, the D/A conversion superposition circuit 40, the 4-20 mA loop circuit 50 and the carrier detection circuit 70.

As shown in fig. 5, the carrier detection circuit 70 includes an operational amplifier U5B and a field effect transistor T3, wherein two input terminals of the operational amplifier U5B are respectively connected to two IO pins of the MSP430 series single chip microcomputer, an output terminal of the operational amplifier U5B is connected to a gate of the field effect transistor T3, and a source of the field effect transistor T3 is connected to a corresponding IO pin of the single chip microcomputer U9.

Referring to fig. 1 to 6, in operation, the single-chip microcomputer U9 of the main control circuit 10 receives a command signal sent by the on-site sensor 90 after analog-to-digital conversion, then the main control circuit 10 generates a square wave signal by using the PWM _ C pin of the single-chip microcomputer U9, the square wave signal is shaped by the analog switch 20 to obtain a stable square wave signal, the square wave signal is subjected to 4-stage RC filtering by the filter circuit 30 and then input to the D/a conversion superposition circuit 40, and on the other hand, the mixed signal processor U2 of the HART modulation and demodulation circuit 60 receives a corresponding level signal sent by the R1T1 pin of the single-chip microcomputer U9 according to the command signal sent by the sensor 90, modulates the received high level signal into a 1200HZ frequency signal, modulates the low level signal into a 2200HZ frequency signal, and then inputs to the D/a conversion superposition circuit 40.

The D/a conversion superimposing circuit 40 superimposes the two kinds of input signals to be a frequency signal of ± 0.5mA and outputs the signal. Then, the analog signal output by the D/a conversion superposition circuit 40 is finally input to the 4-20 mA loop circuit 50, and the current loop generator U3 of the 4-20 mA loop circuit 50 converts the received analog signal into a corresponding 4-20 mA current signal, so as to realize the superposition transmission of the ± 0.5mA frequency signal on the two-wire 4-20 mA current loop. In addition, the current loop generator U3 of the 4-20 mA loop circuit 50 controls the current output at the same time to ensure that the loop current is at a certain stable value of 20 mA-24 mA, thereby ensuring normal HART communication.

The mixed signal processor U2 of the HART modem circuit 60 receives the feedback signal output by the 4-20 mA loop circuit 50 and then sends the feedback signal to the carrier detection circuit 70 for carrier detection. When the signal frequency is detected to be within the range of 1200HZ to 2200HZ, a low level signal is sent to the single chip microcomputer U9 of the main control circuit 10 to indicate that an effective frequency signal exists on the line, then, the single chip microcomputer U9 of the main control circuit 10 informs the HART modulation and demodulation circuit 60 to demodulate through RxD1 and TxD1 pins, demodulates the 1200HZ frequency signal into a high level signal, demodulates the 2200HZ frequency signal into a low level signal, and feeds back the demodulated signal to the single chip microcomputer U9 of the main control circuit 10 through the RITI pin.

The utility model has the advantages that:

The above description is the preferred embodiment of the present invention and the technical principle applied by the preferred embodiment, and for those skilled in the art, without departing from the spirit and scope of the present invention, any obvious changes based on the equivalent transformation, simple replacement, etc. of the technical solution of the present invention all belong to the protection scope of the present invention.

Claims

1. A HART protocol communication circuit, characterized in that: it includes master control circuit, DA conversion stack circuit, 4 ~ 20mA return circuit, HART modem circuit and carrier wave detection circuit, wherein: the main control circuit receives command signals sent by each sensor on site; the square wave signal output end of the master control circuit is connected with the input end of the filter circuit through the analog switch, the instruction level signal transmission end of the master control circuit is connected with the instruction level signal transmission end of the HART modulation and demodulation circuit, the filter signal output end of the filter circuit and the frequency signal output end of the HART modulation and demodulation circuit are respectively connected with the two input ends of the D/A conversion superposition circuit, the superposition output end of the D/A conversion superposition circuit is connected with the feedback signal end of the HART modulation and demodulation circuit through a 4-20 mA loop circuit, the detection signal end of the HART modulation and demodulation circuit is connected with the detection result receiving end of the master control circuit through a carrier detection circuit, and the data sending receiving end of the master control circuit is connected with the data sending receiving end of the HART.

2. The HART protocol communication circuit of claim 1, wherein:

the master control circuit comprises a singlechip, wherein: the single chip microcomputer adopts LPC series single chip microcomputer.

3. The HART protocol communication circuit of claim 1, wherein:

the filter circuit is composed of a 4-stage RC filter circuit.

4. The HART protocol communication circuit of claim 1, wherein:

the D/A conversion superposition circuit comprises a voltage follower consisting of a plurality of operational amplifiers, a plurality of resistors and a plurality of capacitors.

5. The HART protocol communication circuit of claim 1, wherein:

the 4-20 mA loop circuit comprises a current loop generator, an IO pin of the current loop generator is divided into two paths, one path is connected with a power supply through an anti-interference circuit formed by an anti-interference resistor and a voltage stabilizing tube, the other path is connected with the output end of a triode connected with a pin B and a pin E of the current loop generator in parallel and then connected with the feedback signal end of the HART modulation and demodulation circuit through a feedback filter circuit, wherein: the current loop generator adopts an XTR115 chip; the feedback filter circuit includes an operational amplifier.

6. The HART protocol communication circuit of claim 1, wherein:

HART modulation and demodulation circuit includes mixed signal processor, mixed signal processor receives the crystal oscillator signal that master control circuit's singlechip sent, wherein: the mixed signal processor adopts an MSP430 series single chip microcomputer, and each IO pin of the MSP430 series single chip microcomputer is used for being connected with corresponding terminals of the main control circuit, the D/A conversion superposition circuit, the 4-20 mA loop circuit and the carrier detection circuit.

7. The HART protocol communication circuit of claim 1, wherein:

the carrier detection circuit comprises an operational amplifier and a field effect tube.