CN212459997U - POE net gape automatic checkout device - Google Patents
POE net gape automatic checkout device Download PDFInfo
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- CN212459997U CN212459997U CN202021134166.XU CN202021134166U CN212459997U CN 212459997 U CN212459997 U CN 212459997U CN 202021134166 U CN202021134166 U CN 202021134166U CN 212459997 U CN212459997 U CN 212459997U
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Abstract
The utility model discloses a POE net gape automatic detection device, which comprises a processor module, an MCU module, a power supply module, a network cable detection module, a socket module, a POE power management module and a display module; the processor module is respectively connected with the display module and the POE power management module, and is also respectively connected with the power supply module to the network cable detection module and the MCU module to the network detection module; the other end of the network detection module is connected to one end of the socket module, and the other end of the socket module is connected with an electric appliance; the utility model discloses carry out the modularized design to POE equipment automatic check out test set, through the reasonable setting of each module, accomplish the connection sequence detection and analysis of each group line pair, the simultaneous display testing result, and then to power supply control, protection circuit.
Description
Technical Field
The utility model relates to a POE controlled research field, in particular to POE net gape automatic checkout device.
Background
The conventional POE network device mainly obtains a direct current power supply from an RJ45 port of a POE switch, and then supplies power to corresponding powered devices. A complete POE system comprises two parts, namely a Power Sourcing Equipment (PSE) and a Power receiving Equipment (PD). The PSE output voltage range 44V to 57V and the PD receive voltage range 36V to 57V. POE provides a larger voltage value relative to the voltages required on the motherboard and the core board, such as 12V, 5V, 3.3V, etc. When the network cable is used to obtain voltage from the network port of the POE Switch (PSE) and is connected to a powered device (such as a network camera, an IP phone, an AP, a palm computer, etc.), if the sequence of the network cable connecting the two devices is incorrect, the powered device may be burned, which brings great economic loss. At present, most POE switches in the market do not have the function of automatic detection of network cable sequences. When one end of the network cable receives the RJ45 network port of the electric equipment and the other end is connected with the POE switch, the POE switch cannot find the type of the electric equipment, the required voltage value and the network cable sequence and directly supplies power. When the PD is a non-standard device or the line sequence of the network cable (such as a manually made network cable and a crystal head) is incorrect, unpredictable results often occur to the PD, which is a disadvantage of the current POE device. In order to overcome this drawback, a device capable of automatically detecting the network cable sequence needs to be provided in the POE switch.
SUMMERY OF THE UTILITY MODEL
The utility model aims to overcome prior art's shortcoming with not enough, provide a POE net gape automatic checkout device, carry out the modularized design to POE equipment automatic checkout equipment, through the reasonable setting of each module, accomplish the connection sequence detection and analysis of each group line pair, the simultaneous display testing result. The detection result comprises 4 modes of normal, short circuit, open circuit and wrong connection, and the cable impedance of the measured line pair can be displayed. In the detection process, if the 3 conditions of short circuit, open circuit and wrong connection occur, the wiring sequence of the network cable needs to be adjusted until the detection result shows normal. Otherwise, the corresponding RJ45 port, PSE (power sourcing equipment), will not supply power to PD (power receiving end).
The purpose of the utility model is realized through the following technical scheme:
a POE network port automatic detection device is characterized by comprising a processor module, an MCU module, a power supply module, a network cable detection module, a socket module, a POE power management module and a display module; the processor module is respectively connected with the display module and the POE power management module, and is also respectively connected with the power supply module to the network cable detection module and the MCU module to the network detection module; the other end of the network detection module is connected to one end of the socket module, and the other end of the socket module is connected with an electric appliance.
Furthermore, the MCU module comprises an analog-to-digital conversion module, and the analog-to-digital conversion module is connected with the network cable detection module.
Furthermore, the network cable detection module comprises a network cable detection circuit, and the network cable detection circuit is composed of a relay and an MOS (metal oxide semiconductor) tube.
Further, the network cable detection circuit comprises a micro relay J37, a resistor R9, a capacitor C34 and a MOS transistor Q9; wherein pin 12 of J37 is connected to pin 3 of resistor Q9; a pin 2 of the resistor Q9 is grounded, and a pin 1 of the resistor Q9 is connected with the GPIO port SW 3; the 1 pin of J37 is connected with 3.3V power supply; one end of the capacitor C34 is connected with 3.3V, and the other end is grounded; the pin 8 of J37 is connected with R9 in series and then grounded; the 5 pins of J37 are connected with 3.3V; a net-5 network with 9 pins of J37 connected to network cable; a net _4 network with 4 pins of J37 connected to network cable; legs 3 and 10 of J37 are suspended; and the SW3 network corresponds to the 1 pin of the resistor Q9 and is used for controlling the closing and attracting of the J37.
Further, the socket module is an RJ45 socket with model number LPJG0926 HENL.
Further, the processor model is longson 2H.
Further, the MCU module is PIC18F47J 13.
Further, the POE power management module includes a PD69200 and a PD 69208.
The working process of the utility model is as follows:
in the normal case, 8 wires of the net wire are divided into 4 wire pairs of 1 and 2, 3 and 6, 4 and 5, 7 and 8. The detection adopts a polling mechanism, namely, only one pair of control switches (SW1, SW2, SW3 and SW4) are opened at the same time. Each time the control switch is turned on, one round of a/D sampling (8 lines of high and low level sampling) is performed. And calculating the logic level to obtain the actual connection condition of the network cable. And according to the judged result, carrying out line sequence adjustment on the network cable between the PD (powered device) and the POE power supply until the detection is passed. Therefore, the correctness of the network cable connection is ensured, and the guarantee is provided for the next power supply.
It should be noted that, the above working process uses the direction of the signal as a clue to further explain the connection relationship of the components of the POE gateway automatic detection device of the present invention, so that the skilled in the art can more clearly and conveniently implement the present invention, but does not represent the improvement point of the technical proposal of the utility model on the software, the improvement point of the technical proposal of the utility model is on the whole framework of the whole device, although the technical scheme involves treater and other controllers, its execution all is conventional operation, the utility model discloses the components and parts of selecting for use also are current components and parts (also give concrete model), the improvement point of the technical scheme of the utility model lies in how to build into a device with these current components and parts, and the creation point lies in structural promptly, therefore is the protection object who belongs to the utility model patent.
Compared with the prior art, the utility model, following advantage and beneficial effect have:
1. the utility model discloses a low-cost and from the MCU module of taking AD to detect the function, can in time feed back the current line preface state of net twine to godson 2H CPU and handle, realize net twine automated inspection's function, when net twine testing result does not show correctly, PSE can not supply power to the PD. The PD can be protected by avoiding burning the powered device due to human or other factors;
2. the utility model discloses innovation integrated design, detection device's circuit board wiring occupation space is little, and whole board size is little. And put on same PCB board with POE switch mainboard, reliable and stable, convenient practicality.
Drawings
Fig. 1 is a block diagram of the structure of an automatic POE gateway detection device of the present invention;
fig. 2 is a block diagram of the design of the POE gateway automatic detection apparatus in the embodiment of the present invention;
fig. 3 is a circuit diagram of the network cable sequence detection circuit according to the embodiment of the present invention;
fig. 4 is a circuit diagram of an RJ jack according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples and drawings, but the present invention is not limited thereto.
Example (b):
an automatic detection device for a POE (power over Ethernet) port is shown in figure 1 and comprises a processor module, an MCU (microprogrammed control unit) module, a power supply module, a network cable detection module, a socket module, a POE power management module and a display module; the processor module is Loongson2H and is respectively connected with the display module and the POE power management module, and the processor module is also respectively connected with the power supply module to the network cable detection module and the MCU module to the network detection module; the other end of the network detection module is connected to one end of the socket module, and the other end of the socket module is connected with an electric appliance; the POE power management module includes PD69200 and PD 69208. The scheme design block diagram is shown in fig. 2.
Further, the MCU module is a PIC18F47J13, and includes an analog-to-digital conversion module, and the analog-to-digital conversion module is connected to the network cable detection module.
Further, the network cable detection module includes a network cable detection circuit, i.e., a network cable sequence detection circuit, which is shown in fig. 3 and is composed of a relay and an MOS transistor.
Further, the network cable detection circuit comprises a micro relay J37, a resistor R9, a capacitor C34 and a MOS transistor Q9; wherein pin 12 of J37 is connected to pin 3 of resistor Q9; a pin 2 of the resistor Q9 is grounded, and a pin 1 of the resistor Q9 is connected with the GPIO port SW 3; the 1 pin of J37 is connected with 3.3V power supply; one end of the capacitor C34 is connected with 3.3V, and the other end is grounded; the pin 8 of J37 is connected with R9 in series and then grounded; the 5 pins of J37 are connected with 3.3V; a net-5 network with 9 pins of J37 connected to network cable; a net _4 network with 4 pins of J37 connected to network cable; legs 3 and 10 of J37 are suspended; and the SW3 network corresponds to the 1 pin of the resistor Q9 and is used for controlling the closing and attracting of the J37.
The jack module is an RJ45 jack with model number LPJG0926HENL, and a circuit diagram of the RJ jack is shown in fig. 4.
The RJ45 socket comprises resistors R1-R8, electrostatic protection devices (TVS tubes) Q1-Q8 and a J45 socket J12. Wherein 1-8 pins of the J12 are respectively connected with 8 wires of the net wire, 1 and 2 wire pairs, 3 and 6 wire pairs, 4 and 5 wire pairs and 7 and 8 wire pairs. The 1 pin of J12 is connected with R8 in series and then connected to Q1; the 2 pin of J12 and R7 are connected in series and then connected to Q2; the 3 pin of J12 is connected with R6 in series and then connected to Q3; the 4 pin of J12 is connected with R5 in series and then connected to Q4; the 5 pin of J12 is connected with R4 in series and then connected to Q5; the 6 pin of J12 is connected with R3 in series and then connected to Q6; the 7 pin of J12 is connected with R2 in series and then connected to Q7; the 8 pin of J12 is connected with R1 in series to be connected to Q8. Pins 9 and 11 of the J12 are connected with status lights of the RJ45 socket respectively, and the colors are green and orange respectively.
The CPU sends out an instruction through the SPI bus to inform the MCU to start network cable detection:
step 1: line order detection
The MCU starts to carry out line sequence detection, firstly, SW1 (high level) is controlled, AD 1-AD 8 levels are detected, the high level is found when more than 1V is found, and the low level is found when 0.3V is found; and recording the display state. Table 4-1 is the design logic for each line pair. Then, the SW2, SW3 and SW4 switches need to be turned on in turn, i.e. only one switch is turned on at the same time. The indicator light shows the situation: and (3) normal line sequence green lighting: LED1_ G _ SW is high, LED1_ R _ SW is low; the design logic truth table is as follows:
design logic truth table
| Displaying status | AD1 | AD2 | AD3 | AD4 | AD5 | | AD7 | AD8 | |
| 1. 2 Normal sequence of lines | H | H | L | L | L | | L | L | |
| 1. 2 short circuit | H | H | Or H | Or H | Or H | Or H | Or | Or H | |
| 1. 2 open circuit | H | L | L | L | L | | L | L | |
| 1. 2 connect wrong | H | L | Or H | Or H | Or H | Or H | Or | Or H | |
| 3. 6 Normal sequence of lines | L | L | H | L | L | | L | L | |
| 3. 6 short-circuiting | Or H | Or H | H | Or H | Or H | H | Or | Or H | |
| 3. 6-way circuit | L | L | H | L | L | | L | L | |
| 3. 6 wrong connection | Or H | Or H | H | Or H | Or H | L | Or | Or H | |
| 4. 5 Normal sequence of lines | L | L | L | H | H | | L | L | |
| 4. 5 short circuit | Or H | Or H | Or H | H | H | Or H | Or | Or H | |
| 4. 5 breaking circuit | L | L | L | H | L | | L | L | |
| 4. 5 connect wrong | Or H | Or H | Or H | H | L | Or H | Or H | Or H | |
| 7. 8 Normal sequence of lines | L | L | L | L | L | L | H | H | |
| 7. 8 short circuit | Or H | Or H | Or H | Or H | Or H | Or H | H | H | |
| 7. 8-way cut | L | L | L | L | L | L | H | L | |
| 7. 8 connect the mistake | Or H | Or H | Or H | Or H | Or H | Or H | H | L |
Step 2: impedance testing
When the line sequence and the short circuit are normal, the impedance test is started, SW1 (high level) is controlled, AD1 and AD2 voltages are detected, and the voltages of AD1 and AD2 are calculated, wherein the formula is that the network line impedance R is (AD1 voltage-AD 2 voltage) × 51.5/AD2 voltage. Calculating the impedance R of the network cable to be less than or equal to 30 ohms and displaying the impedance R as normal; greater than 30 ohms is unusual. Similarly, the SW2, the SW3 and the SW4 are controlled to normally light green lights on the screen wires: LED1_ G _ SW is high and LED1_ R _ SW is low. The impedance calculation is to check the materials used in the production of the network cable, and the impedance of different medium materials can also be different. The register function description table is consulted specifically.
Register function description table
And step 3: after the test is finished, the CPU loongson2H for data transmission is performed and the result is displayed, as shown in the display result table:
display result table
Through the design process, after power supply detection is carried out before the Loongson2H development board is powered on, the Loongson2H development board starts to be powered on, and after the PMON is downloaded through a JTAG debugging interface (an SPI FLASH burn-in mode can also be used), the development board normally operates. Meanwhile, the system reads NAND FLASH the main program, and can view and configure the related information through UART serial port. And displaying a result table as a related detection result, and debugging log information of serial port printing.
The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be equivalent replacement modes, and all are included in the scope of the present invention.
Claims (8)
1. A POE network port automatic detection device is characterized by comprising a processor module, an MCU module, a power supply module, a network cable detection module, a socket module, a POE power management module and a display module; the processor module is respectively connected with the display module and the POE power management module, and is also respectively connected with the power supply module to the network cable detection module and the MCU module to the network detection module; the other end of the network detection module is connected to one end of the socket module, and the other end of the socket module is connected with an electric appliance.
2. The automatic detection device for the POE internet access of claim 1, wherein the MCU module comprises an analog-to-digital conversion module, and the analog-to-digital conversion module is connected to the network cable detection module.
3. The automatic detection device for the POE port according to claim 1, wherein the network cable detection module comprises a network cable detection circuit, and the network cable detection circuit is composed of a relay and an MOS (metal oxide semiconductor) tube.
4. The automatic detection device for the POE port according to claim 3, wherein the network cable detection circuit comprises a micro relay J37, a resistor R9, a capacitor C34 and a MOS transistor Q9; wherein, the 12 pins of the J37 are connected with the 3 pins of the MOS transistor Q9; a pin 2 of the MOS transistor Q9 is grounded, and a pin 1 of the MOS transistor Q9 is connected with a GPIO port SW 3; the 1 pin of J37 is connected with 3.3V power supply; one end of the capacitor C34 is connected with 3.3V, and the other end is grounded; the pin 8 of J37 is connected with the resistor R9 in series and then is grounded; the 5 pins of J37 are connected with 3.3V; a net-5 network with 9 pins of J37 connected to network cable; a net _4 network with 4 pins of J37 connected to network cable; legs 3 and 10 of J37 are suspended; and the SW3 network corresponds to the 1 pin of the resistor Q9 and is used for controlling the closing and attracting of the J37.
5. The automatic detecting device for POE ports of claim 1, wherein the jack module is an RJ45 jack, model LPJG0926 HENL.
6. The automatic detection device for the POE gateway of claim 1, wherein the processor type is longson 2H.
7. The automatic detection device for the POE internet access port according to claim 1, wherein the MCU module is a PIC18F47J 13.
8. The apparatus of claim 1, wherein the POE power management module comprises a PD69200 and a PD 69208.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021134166.XU CN212459997U (en) | 2020-06-18 | 2020-06-18 | POE net gape automatic checkout device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021134166.XU CN212459997U (en) | 2020-06-18 | 2020-06-18 | POE net gape automatic checkout device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112910738A (en) * | 2021-02-05 | 2021-06-04 | 四川天邑康和通信股份有限公司 | Router and PON-based line sequence classification method for network port panel butt joint |
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2020
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112910738A (en) * | 2021-02-05 | 2021-06-04 | 四川天邑康和通信股份有限公司 | Router and PON-based line sequence classification method for network port panel butt joint |
| CN112910738B (en) * | 2021-02-05 | 2023-02-28 | 四川天邑康和通信股份有限公司 | Router and PON-based line sequence classification method for network port panel butt joint |
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