CN212411260U - Access control system - Google Patents

Abstract

The present disclosure provides an access control system, which includes a first processor, a second processor, and at least one external device: the first processor acquires first data of a target object, receives second data of the second processor, and generates control information according to the first data and/or the second data; the second processor is connected with the at least one external device, receives the control information of the first processor, and controls the external device according to the control information.

Description

Access control system

Technical Field

The present disclosure relates to the field of intelligent control, and more particularly, to an access control system.

Background

With the rapid development of artificial intelligence, the face recognition technology is widely applied to the fields of face access control, face payment, human evidence verification and the like. In particular to the field of human face entrance guard, a plurality of external devices such as RFID card swiping peripherals, wiegand interfaces, human body perception sensors, matrix keyboard keys and the like need to be managed. The existing face access control system generally has the problems of low working efficiency, insufficient interface resources and the like.

SUMMERY OF THE UTILITY MODEL

According to an aspect of the present disclosure, an access control system is provided. The system comprises a first processor, a second processor and at least one external device: the first processor acquires first data of a target object, receives second data of the second processor, and generates control information according to the first data and/or the second data; the second processor is connected with the at least one external device, receives the control information of the first processor, and controls the external device according to the control information.

In connection with any embodiment provided by the present disclosure, the first processor includes an SOC and the second processor includes an MCU; and at least one interface of the MCU is used for connecting external equipment.

In combination with any of the embodiments provided by the present disclosure, the system further comprises at least one image capture device, the image capture device being connected to the interface of the first processor.

In combination with any one of the embodiments provided by the present disclosure, the system further includes a first power source and a second power source, the first power source is configured to supply power to the first processor, and the second power source is configured to supply power to the second processor and the external device.

In connection with any embodiment provided by the present disclosure, the interface of the second processor comprises at least one analog-to-digital conversion interface; the second processor is connected with a photosensitive detection circuit through the analog-to-digital conversion interface to obtain a detection result of the photosensitive detection circuit, wherein the photosensitive detection circuit is used for detecting the illumination intensity of the ambient light.

In combination with any one of the embodiments provided by the present disclosure, the interface of the second processor includes at least one analog-to-digital conversion interface, and the second processor is configured to obtain the voltage of the setting signal through the analog-to-digital conversion interface.

In connection with any embodiment provided by the present disclosure, the interface of the second processor includes at least one analog-to-digital conversion interface and at least one general input/output interface; the second processor is connected with a temperature sensor through the analog-to-digital conversion interface to obtain a detection result of the temperature sensor, wherein the temperature sensor is used for detecting the temperature of a setting device in the system; the second processor is also connected with a heating system and a heat dissipation system through the general input/output interface, so as to control the heating system and/or the heat dissipation system according to the detection result, and the second processor starts the heat dissipation system in response to the temperature of the setting device being greater than a first set value; and, in response to the temperature of the setting device being less than a second set point, the second processor turns on the heating system.

In connection with any embodiment provided by the present disclosure, the interface of the second processor includes a plurality of general purpose input/output interfaces including a first general purpose input/output interface and a second general purpose input/output interface;

the first general input/output interface is connected with a first power supply of the first processor; the second general input/output interface is connected with the dormancy and awakening key to acquire the state of the dormancy and awakening key, generate a state control instruction according to the state of the dormancy and awakening key and send the state control instruction to the first processor; and the second processor controls the first power supply of the first processor according to the state of the dormancy and wakeup key.

In connection with any embodiment provided by the disclosure, the interface of the second processor includes at least one general purpose input/output interface; the second processor is used for monitoring the running state of the first processor through the general input/output interface and sending enabling information to the first processor or the first power supply according to the running state.

The access control system of the embodiment of the disclosure utilizes the first processor to obtain the first data of the target object and/or receive the second data of the second processor, generates the control letter according to the first data and/or the second data, utilizes the second processor to connect with the external device, receives the control information through the second processor, and controls the external device according to the control information, thereby realizing the data co-processing of the external device of the first processor by the second processor, compared with the access control system which uses a single processor to process data to generate control information, and connects with the external device to control the external device, the embodiment of the disclosure improves the data processing efficiency of the first processor, and solves the problems that the number and resources of the external interfaces of the single processor platform are limited, and software and hardware are not easy to transplant, and the system has improved anti-ESD (Electro-Static Discharge) Interference ability, reduced EMI (Electro-Magnetic Interference) radiation of the system.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and together with the description, serve to explain the principles of the specification.

Fig. 1 is a schematic view of an access control system according to at least one embodiment of the present disclosure;

FIGS. 2A and 2B are schematic ground plane diagrams of the SOC connection external device and the MCU connection external device;

FIGS. 3A and 3B are schematic diagrams of a backflow path between the SOC connection external device and the MCU connection external device;

FIGS. 4A and 4B are schematic diagrams of a plate-level conduction mode and a spatial coupling mode, respectively, of ESD energy;

FIG. 5 is a schematic diagram of ESD energy discharging to ground;

FIG. 6 is a diagram of GPIO output structure of SOC;

FIGS. 7A and 7B are schematic diagrams of ESD conducted energy of the SOC connected to the external device and the MCU connected to the external device;

FIGS. 8A and 8B are schematic diagrams of surges when the SOC connects the external device and the MCU connects the external device;

fig. 9 is a block diagram of an access control system according to at least one embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

The disclosed embodiments may be applied to computer systems/servers that are operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well known computing systems, environments, and/or configurations that may be suitable for use with the computer system/server include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set top boxes, programmable consumer electronics, network pcs, minicomputer systems, mainframe computer systems, distributed cloud computing environments that include any of the above systems, and the like.

The computer system/server may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system/server may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

Fig. 1 is a schematic diagram of an access control system according to at least one embodiment of the present disclosure. The system comprises a first processor 101, a second processor 102 and at least one external device 103.

The first processor 101 obtains first data of a target object and receives second data of the second processor 102, and generates control information according to the first data and/or the second data.

The target object comprises a user of an access control system, and the first data comprises image data of the target object, including face image data, human body image data and the like.

In the embodiment of the present disclosure, the first data may be data acquired by an image acquisition device in the access control system, the image acquisition device is connected to an interface of the first processor 101, and the first processor 101 acquires the first data through the interface; the first data may also be acquired by the first processor 101 via a network. The embodiment of the present disclosure does not limit the manner of acquiring the first data.

The second data of the second processor 102 may include data acquired or generated by the external device 103. Since the external device 103 is directly connected to the second processor 102, the second processor 102 may acquire data of the external device 102 and transmit the acquired data to the first processor 101.

The first processor 101 generates control information according to the first data and/or the second data, and the control information controls external equipment in the access control system. The second processor 102 receives the control information and controls the external device according to the control information.

Taking the first processor 101 to obtain a face image acquired by an image acquisition device in the access control system, taking the external device to be controlled as a magnetic lock as an example, the first processor 101 compares the obtained face image with a face image in a set database to obtain a comparison result, where the comparison result includes, for example, a similarity. Comparing the comparison result with a preset threshold, and in response to that the comparison result is greater than or equal to the threshold, determining that the target object corresponding to the acquired face image passes verification, generating a door opening signal by the first processor 101, and receiving the door opening signal by the second processor 102 and controlling the magnetic lock to be opened so as to enable the target object to pass through the access control system; and responding to the comparison result smaller than the threshold value, determining that the target object corresponding to the face image fails to be verified, and not generating a door opening signal, wherein the target object cannot pass through the access control system.

In the disclosed embodiment, first data of a target object is acquired by a first processor, and/or second data of a second processor is received, and generates a control signal according to the first data and/or the second data, and is connected with the external equipment by utilizing the second processor, the second processor receives the control information and controls the external equipment according to the control information, so that the data co-processing of the external equipment of the first processor by the second processor is realized, compared with the situation that a single processor is used for data processing in an access control system to generate the control information, the embodiment of the disclosure improves the data processing efficiency of the first processor, solves the problems that the number and resources of peripheral interfaces of a single processor platform are limited, and software and hardware are not easy to transplant, and improves the anti-ESD interference capability of the system.

In the embodiment of the present disclosure, the first processor for processing the first data and/or the second data may be a System On Chip (SOC) with built-in RAM, ROM and capable of running an operating System, or other processors with corresponding processing capabilities. The second processor for connecting and controlling the external device may be an MCU (Micro Controller Unit), or other processor having a corresponding processing capability. The MCU can be connected with a plurality of low-speed external devices and can cooperatively process data processing services of a plurality of SOC external devices.

Since the access control system needs to manage a plurality of external devices, such as an RFID card swiping peripheral, a wiegand interface, a human body sensing sensor, a matrix keyboard key and the like, the problem of insufficient communication interfaces of the external devices of the SOC is often encountered under the condition that the SOC is directly connected with the plurality of external devices. According to the access control system, the MCU connected with the SOC is added, and the interface of the MCU is connected with the external equipment, so that the problem that the quantity of the peripheral interfaces of the SOC platform and resources are limited is solved.

Due to the fact that the data generation of the external device is unknown in time, frequent interrupt response can disturb the CPU core in the SOC to check the data processing service, such as the execution thread of the face recognition service. Therefore, the performance and the critical work efficiency of the CPU core are affected in the case of concurrent data of the external devices. According to the access control system, the MCU connected with the SOC is added, and the interface of the MCU is connected with the external equipment, so that the performance and the key working efficiency of the CPU core in the SOC are improved.

Due to the problem of product iteration or cost optimization, when the SOC is directly connected with the external device, a chip interface error or a native driver problem of a software development tool may be encountered when a new platform is migrated, and software driving and code transplantation of the SOC of the new platform may increase a software development cycle of the access control system, particularly, transplantation across operating systems, such as transplantation between an Android system and a Linux system. In addition, the switching of the SOC platform also causes hardware compatibility problems, which generally increases workload of hardware risk assessment in the early stage of system development and workload of reliability test and consistency test of the interface in the later stage. According to the method, the MCU is applied to the access control system to manage the plurality of low-speed peripherals, the problem that software and hardware are not easy to transplant due to shear of the SOC platform in the design stage is solved, and the product scheme design of the new platform SOC can be quickly met.

Fig. 2A and 2B are schematic ground plane diagrams of the SOC connecting the external device and the MCU connecting the external device. As shown in fig. 2A, the SOC direct-connected peripheral architecture makes the integrity of the PCB (Printed Circuit Board) ground plane under the SOC poor, which is not favorable for heat dissipation. The MCU coprocessing technology framework provided by the embodiment of the disclosure reduces the number of direct-connection IO (Input/Output) interfaces between the peripheral and the SOC, thereby reducing via holes of the IO interfaces of the SOC, as shown in FIG. 2B, improving the integrity of a copper foil plane below the SOC, and improving the heat dissipation capability.

In addition, the SOC becomes a main EMI emission source in the system due to the core operating frequency, internal clock frequencies, and signal frequencies of internal physical layers (PHYs). And once the interconnected IO wiring generates antenna benefit, the noise energy with complex SOC can be further radiated to the space. Fig. 3A and 3B are schematic diagrams of a backflow path between the SOC and the MCU. As the IO layer-change via may destroy the power and ground signal planes, the SOC direct-connection peripheral architecture may cause an increase of a backflow path of the SOC High-speed signal, as shown in fig. 3A, the SOC High-speed signal may be, for example, a DDR (Double Data Rate), an HDMI (High Definition Multimedia Interface), a USB (Universal Serial Bus), or a digital signal with a large edge slope. The longer the return path of the high speed signal, the greater the parasitic inductance of its PCB, i.e., the impedance will increase. When the impedance of the return path is greater than the wave impedance of free space 377 Ω, free space becomes the return path for high speed signals, further exacerbating EMI emissions. The MCU coprocessing technology framework provided by the embodiment of the disclosure reduces the number of direct-connected IO of peripheral equipment and SOC, thereby reducing via holes of IO interfaces of SOC, shortening backflow paths of SOC high-speed signals, as shown in FIG. 3B, reducing EMI radiation, and improving antenna effect of IO wiring.

In system applications, ESD suppression is also desirable. Suppressing ESD is actually preventing ESD high voltage pulses from affecting system function through spatial radiation coupling and board level conduction. Fig. 4A and 4B are schematic diagrams of a board level conduction mode and a spatial coupling mode of ESD energy, respectively. The continual accumulation of ESD energy can damage the IO structure or interfere with the transmission of data causing functional failure. Meanwhile, most of the multimedia SOC is business grade, and the ESD grade of the multimedia SOC only meets HBM 2000KV of JEDEC standard. The MCU coprocessing technology framework provided by the embodiment of the disclosure reduces the number of direct-connected IO of peripheral equipment and SOC, reduces ESD energy entering an SOC chip from an IO path in a space coupling or board level conduction mode, and also brings ESD benefit due to improvement of a power supply and a ground signal plane below the SOC. By selecting the MCU with good ESD interference resistance, the ESD interference resistance of the whole machine can be effectively improved.

In addition, as the ESD discharges to ground, current flows through the ground loop, which creates an unbalanced potential difference at the ground plane, causing an electrical shift of the zero volt reference potential, as shown in fig. 5. The MCU co-processing technical framework provided by the embodiment of the disclosure improves the integrity of a ground plane below the SOC, reduces the electrical deviation of the SOC, and improves the problems of deadlock or logic error of a CMOS circuit.

When the SOC is directly connected to a plurality of external devices, the Input/Output current of a GPIO (General-Purpose Input/Output) interface of the SOC is increased, thereby exacerbating the temperature rise and power consumption of the SOC.

Fig. 6 shows a GPIO output structure diagram of the SOC. As shown in fig. 6, for a single GPIO output structure, the on internal resistances Rup, Rdown of the transistors Q1, Q2 limit the IO output and sink currents while also converting electrical energy into heat, and this portion of power is the dominant power point in the IO structure.

When the GPIO of the SOC outputs a high level, the dissipation power Pup (unit mW) of the transistor Q1 is calculated as follows:

Pup＝Rup·I² (1)

the output current (in mA) when the GPIO of the SOC outputs a high level is the I, and the magnitude of the output current depends on the external impedance of the interface connection, and may be generally 1 mA. Taking HI3516DV300 SOC as an example, in a voltage domain of 3.3V, the high-level output voltage Voh of the SOC is 2.4V, and the high-level output current Ioh is 3.5mA, so that the on-resistance is known

The dissipated power of transistor Q1 was 0.26 mW.

The calculation formula of the temperature rise generated by each GPIO is as follows:

ΔT＝Rup·N·θJA (2)

wherein θ JA is junction-to-air thermal resistance, and takes HI3516DV300 SOC as an example, and θ JA is 0.26 mW.

According to the access control system that this disclosed embodiment provided, under the condition that reduces the interface that uses 20 SOC, the temperature rise that reduces can reach 0.15 ℃.

Part of the interfaces of the SOC support a low power consumption mode, such as a UART (Universal Asynchronous Receiver/Transmitter) interface, an IIC (Inter-Integrated Circuit) interface, a function of disabling the UART, IIC or UART, IIC transmission/reception by programming to reduce power consumption, and a function of turning off the UART, IIC clocks to save power consumption. In the direct connection technology architecture, most or all of the UART interface and the IIC interface of the SOC are occupied, so that the low power consumption mode cannot be used. The access control system provided by the embodiment of the disclosure can support the closing of UART and IIC interfaces of more SOCs, thereby saving power consumption.

In the embodiment of the disclosure, the MCU connected with the SOC is added in the access control system, and the interface of the MCU is connected with the external device, so that more SOC interfaces are in an idle state, the quiescent current of the GPIO interface of the SOC is reduced, active cooling is realized, and the problem of temperature rise is improved; the power consumption is reduced by forbidding the functions of the UART interface and the IIC interface, and the power consumption is further saved by closing the clocks of the UART interface and the IIC interface, so that the power consumption of the SOC in the access control system is reduced.

In some embodiments, the system further comprises a first power source for powering the first processor and a second power source for powering the second processor and the external device. Namely, for the SOC and the MCU in the access control system, two power supplies which are independent of each other are adopted for supplying power.

In some embodiments, the first processor, the second processor, and the external device may be powered by the same power source.

It should be noted that, in the above embodiments, the first power supply, the second power supply and the power supply may be batteries or external power supplies, and are not limited specifically.

Fig. 7A and 7B are schematic diagrams of ESD conducted energy of the SOC connection external device and the MCU connection external device. Under the SOC-direct-connected peripheral architecture, as shown in fig. 7A, ESD energy is easily cross-talk to the SOC-sensitive voltage domain through the power domain of the peripheral (low speed load), and the SOC may be dead or burned due to ESD. The MCU coprocessing technology architecture provided by the embodiment of the present disclosure, as shown in fig. 7B, the MCU and the low-speed load power supply are independent of the SOC IO power supply, the ESD conduction energy is constrained in the MCU loop and cannot cross-talk to the SOC sensitive voltage domain through the power domain, and the industrial MCU can be used to further provide higher anti-interference capability to the system.

In addition, as the chip process is smaller and higher, the thickness of the gate oxide layer of the chip unit is thinner and thinner, and the problem of Surge (Surge) of the IO interface of the chip is more and more prominent. Fig. 8A and 8B are schematic diagrams of surges when the SOC is connected with the external device and the MCU is connected with the external device. Since EFT (Electrical Fast Transient) is Transient impulse interference and mainly common mode interference of IO interfaces, the multimedia SOC generally does not have sufficient anti-interference capability. The MCU co-processing technical framework provided by the embodiment of the disclosure can adopt an industrial-grade MCU to connect with and control a peripheral. The IO interface of the MCU has better surge interference resistance, particularly the IO interface of the industrial MCU can bear the interference of 4KV EFT, the problem of interface surge is improved, and the surge grade of the whole exposed interface and the cost of a passive protection device can be improved.

Fig. 9 is a block diagram of an access control system according to at least one embodiment of the present disclosure. As shown in fig. 9, the MCU is connected to a plurality of external devices to cooperatively process the SOC peripheral data processing service. The MCU can share data with the SOC through the UART interface and execute a control command of the SOC. For example, the SOC is interconnected with the UART interface of the MCU through the UART interface to establish a data transmission channel. The UART sequence number in FIG. 9 is for illustration only and is not intended to be limiting, as follows.

In one example, the MCU reads data of an RFID (Radio Frequency Identification) device through a UART interface, so as to read data of an RFID access card. The MCU transmits the read RFID data to the SOC, and the SOC processes the data and generates control information for controlling other external devices, such as a magnetic lock. And the MCU receives the control information and controls the magnetic lock so as to enable the target object to pass or not pass through the entrance guard.

In one example, the MCU is connected to the wiegand Interface through the GPIO group to implement data reading of a remote HID (Human Interface Devices) card. The GPIO groups include at least one GPIO interface, and the sequence numbers of the GPIO groups in fig. 9 are only for example and are not intended to be limiting, and the same applies below.

In one example, the MCU is interconnected with the human perception sensor through the IIC interface to obtain the distance between the target object and the door access. The serial numbers of the IIC interfaces in fig. 9 are for illustration only and are not intended to be limiting, as follows.

In one example, the MCU is connected to a matrix keyboard circuit through GPIO groups to achieve keyboard data acquisition, where the matrix keyboard is 4 × 4, for example.

In one example, the MCU is connected through a set of GPIOs to one or more of the following: alarm input and output circuit, door magnetism control circuit, doorbell circuit to realize functions such as warning, door magnetism control, doorbell. It will be appreciated by those skilled in the art that the MCU may also be connected to other peripherals and that fig. 9 is for illustration only and is not intended to be limiting.

The face recognition access control system usually needs to measure the illumination intensity, the temperature of key devices and the voltage value of key signals, and the measurement precision will influence the consistency of performance indexes of the access control system. At present, the acquisition precision of an ADC (Analog-to-Digital Converter) of the multimedia SOC only supports 8/10 bits, and the number of ADC channels is limited. In view of the above, in the embodiment of the present disclosure, the MCU is connected to the photosensitive detection circuit through the ADC interface to obtain a detection result of the photosensitive detection circuit, where the photosensitive detection circuit is used to detect the illumination intensity of the ambient light. Because MCU's ADC acquisition precision is higher, for example can reach 12 bits, consequently the access control system that this disclosed embodiment provided can realize the quantitative detection of environment light illumination intensity of high accuracy. The number and number of ADC interfaces in fig. 9 are for example only and not intended to be limiting, as follows.

Door access products used in outdoor environments are subject to environmental problems of low temperature and high temperature, for example, as low as-30 ℃ and as high as 70 ℃. The SOC nominal working environment temperature applied to the access control system at present is usually 0-70 ℃, and faults are easy to occur under the low-temperature condition. In view of the above, in the embodiment of the present disclosure, the MCU is connected to a Temperature sensor through an ADC interface to obtain a detection result of the Temperature sensor, wherein the Temperature sensor is used to detect a Temperature of a setting device in the system, and the Temperature sensor is, for example, an NTC (Negative Temperature Coefficient) sensor to detect a Temperature rise on a surface of the setting device. Because the working environment temperature of the industrial-grade MCU can reach-40-85 ℃, and the ADC acquisition precision of the MCU is higher, the access control system provided by the embodiment of the disclosure improves the reliability, and can realize high-precision quantitative temperature rise detection.

And the MCU is connected with the heating system and the heat dissipation system through GPIO interfaces so as to control the heating system and/or the heat dissipation system according to the detection result of the temperature sensor. Specifically, in response to the temperature of the setting device being greater than a first setting value, the second processor turns on the heat dissipation system; and/or responding to the temperature of the setting device being smaller than a second set value, the second processor starts the heating system, so that the temperature control management of the access control system is realized. In the embodiment of the present disclosure, the first set value and the second set value may be set according to a temperature nominal value of the setting device, which is not limited by the present disclosure.

In one example, the MCU obtains the voltage of the setting signal through the ADC interface to realize high-precision detection of power supply voltage, battery level, and the like, thereby realizing functions such as early warning of low input operating voltage, early warning of low battery level, and the like.

In one example, the MCU is connected with the sleep and wake-up key through one of the GPIO interfaces to acquire the state of the sleep and wake-up key, generate a state control instruction according to the state and send the state control instruction of the sleep and wake-up key to the SOC; and the SOC controls the power supply of the MCU according to the states of the dormancy and awakening keys. That is, when the MCU receives a system sleep command through the sleep and wake-up button, the SOC is informed to sleep and the system power is turned off; when the MCU receives a system awakening instruction, the system power supply is turned on, and the system is awakened. In the embodiment of the disclosure, the system can be dormant and awakened without adding extra cost.

In the gate inhibition comb in the related art, an SOC internal watchdog technology is generally adopted, and a soft restart command is automatically executed under the condition that no dog is fed within a specified time. However, at a low temperature or a high temperature, the SOC with a temperature scale of 0 to 70 ℃ may have the problem of probabilistic functional failures such as incapability of loading flash firmware and initialization of DDR configuration, which results in loss of the effect of a door-open dog due to incapability of loading and executing configuration codes and incapability of meeting the reliability requirement of outdoor access control products. In view of the above, in the embodiment of the present disclosure, the MCU monitors the operating state of the SOC through the GPIO interface, and transmits the enable information to the SOC or the first power supply of the SOC according to the operating state. The protection mechanism applied by the embodiment of the disclosure is a double-dog mechanism, a watchdog mechanism in SOC and a watchdog mechanism outside MCU, and because the working environment temperature of the industrial MCU can reach-40-85 ℃, the reliability of the system keep-alive mechanism under a wide temperature range is improved.

In one example, the MCU is connected with the SOC through a GPIO to transmit and trigger the receiving/transmitting state in a GPIO interruption mode.

In addition, by reserving SPI (Serial Peripheral Interface), PWM (Pulse Width Modulation), and GPIO interfaces of the MCU, the extensibility of the MCU co-processing technical framework of the access control system proposed by the embodiment of the present disclosure is enhanced, and interfaces are reserved for later-stage projects and new functions; meanwhile, the GPIO interface can be expanded to control the time sequence of the peripheral power supply and the like, so that the control of the peripheral power supply is facilitated.

As will be appreciated by one skilled in the art, one or more embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The term "and/or" as used in this disclosure means having at least one of the two, e.g., "a and/or B" includes three scenarios: A. b, and "A and B".

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the data processing apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to part of the description of the method embodiment.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Embodiments of the subject matter and the functional operations described in this specification can be implemented in: digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a tangible, non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode and transmit information to suitable receiver apparatus for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

Computers suitable for executing computer programs include, for example, general and/or special purpose microprocessors, or any other type of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory and/or a random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer does not necessarily have such a device. Moreover, a computer may be embedded in another device, e.g., a mobile telephone, a Personal Digital Assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device such as a Universal Serial Bus (USB) flash drive, to name a few.

Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., an internal hard disk or a removable disk), magneto-optical disks, and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. In other instances, features described in connection with one embodiment may be implemented as discrete components or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Further, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous.

The above description is only for the purpose of illustrating the preferred embodiments of the one or more embodiments of the present disclosure, and is not intended to limit the scope of the one or more embodiments of the present disclosure, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the one or more embodiments of the present disclosure should be included in the scope of the one or more embodiments of the present disclosure.

Claims (9)

1. An access control system, comprising a first processor, a second processor, and at least one peripheral device:

the first processor acquires first data of a target object, receives second data of the second processor, and generates control information according to the first data and/or the second data;

the second processor is connected with the at least one external device, receives the control information of the first processor, and controls the external device according to the control information.

2. The system of claim 1, wherein the first processor comprises an SOC and the second processor comprises an MCU; and at least one interface of the MCU is used for connecting external equipment.

3. The system of claim 1 or 2, further comprising at least one image capture device, the image capture device being connected to the interface of the first processor.

4. The system of claim 2, further comprising a first power source for powering the first processor and a second power source for powering the second processor and the external device.

5. The system of claim 1 or 2, wherein the interface of the second processor comprises at least one analog-to-digital conversion interface; the second processor is connected with a photosensitive detection circuit through the analog-to-digital conversion interface to obtain a detection result of the photosensitive detection circuit, wherein the photosensitive detection circuit is used for detecting the illumination intensity of the ambient light.

6. The system of claim 1 or 2, wherein the interface of the second processor comprises at least one analog-to-digital conversion interface; and the second processor acquires the voltage of the set signal through the analog-to-digital conversion interface.

7. The system of claim 1 or 2, wherein the interface of the second processor comprises at least one analog-to-digital conversion interface and at least one general purpose input/output interface; the second processor is connected with a temperature sensor through the analog-to-digital conversion interface to obtain a detection result of the temperature sensor, wherein the temperature sensor is used for detecting the temperature of a setting device in the system;

the second processor is also connected with a heating system and a heat dissipation system through the general input/output interface so as to control the heating system and/or the heat dissipation system according to the detection result,

in response to the temperature of the setting device being greater than a first setting value, the second processor turns on the heat dissipation system; and the number of the first and second groups,

the second processor turns on the heating system in response to the temperature of the setting device being less than a second set point.

8. The system of claim 4, wherein the interface of the second processor comprises a plurality of general purpose input/output interfaces including a first general purpose input/output interface and a second general purpose input/output interface;

the first general input/output interface is connected with a first power supply of the first processor; the second general input/output interface is connected with the dormancy and awakening key to acquire the state of the dormancy and awakening key, generate a state control instruction according to the state of the dormancy and awakening key and send the state control instruction to the first processor; and the second processor controls the first power supply of the first processor according to the state of the dormancy and wakeup key.

9. The system of claim 4, wherein the interface of the second processor comprises at least one general purpose input/output interface; the second processor is used for monitoring the running state of the first processor through the general input/output interface and sending enabling information to the first processor or the first power supply according to the running state.

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