CN212381121U

CN212381121U - High-voltage BUCK response circuit

Info

Publication number: CN212381121U
Application number: CN202021720088.1U
Authority: CN
Inventors: 方建平; 薛永强; 张适
Original assignee: Xi'an Tuoer Microelectronics Co ltd
Current assignee: Tuoer Microelectronics Co.,Ltd.
Priority date: 2020-08-17
Filing date: 2020-08-17
Publication date: 2021-01-19
Anticipated expiration: 2030-08-17

Abstract

The invention provides a high-voltage BUCK response circuit, which is used in the field of related protection circuits and comprises an N-channel enhanced MOS transistor NM 0-NM 1, an inductor L, resistors R0-R2, a capacitor C0, a low-voltage driving circuit module, a high-voltage driving circuit module, a charge pump module, a PWM (pulse-width modulation) adjusting circuit module, an EA (energy-area array) module, an A/D (analog-to-digital) converter module, a VIN (voltage-input) port, a VREF (reference voltage) input port and a VOUT (voltage output) output port, wherein the circuit automatically adjusts the main loop parameters of the circuit through an adjusting loop to achieve the effects of detection, feedback and adjustment in a. The invention has simple overall circuit design, is completely suitable for a high-voltage CMOS process, has simpler and quicker loop detection SW waveform, can well transmit the stable condition of output to a main loop of the circuit for quick adjustment, can increase the number of bits output by an A/D converter according to actual requirements, thereby grading the adjustment of the gain of an EA module and selecting the gain required to be increased in real time according to the actual output waveform.

Description

High-voltage BUCK response circuit

Technical Field

The invention relates to the technical field of circuits, in particular to a loop quick response circuit.

Background

With the rapid development of science and technology, electronic products are continuously upgraded and updated, and the requirements on the input voltage of a power supply and the stability and quality of a chip are higher and higher. The BUCK chip is used as one of power supply chips, and has the characteristics of high conversion efficiency, low cost and good dynamic performance, and becomes an essential chip in a power supply module. However, as the input voltage is increased and the application range of the load is enlarged, the BUCK chip cannot be adjusted in time to generate an unstable or voltage and current overshoot phenomenon when the load is changed, so that the chip or the output end is burned out. Therefore, it is desirable to design a BUCK chip with fast response and good recovery function, so as to be able to cope with the effect of fast stabilizing the circuit when the load changes under the condition of high-voltage input.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a high-voltage BUCK response circuit which is used in the field of related protection circuits. Therefore, the loop quick response method applicable to the high-voltage BUCK can effectively solve the technical problems in the related field.

The technical scheme adopted by the invention for solving the technical problems is as follows:

a high-voltage BUCK response circuit comprises an N-channel enhancement type MOS transistor NM0_ NM1, an inductor L, resistors R0-R2, a capacitor C0, a low-voltage driving circuit module, a high-voltage driving circuit module, a charge pump module, a PWM (pulse-width modulation) adjusting circuit module, an EA (emitter array) module, an A/D (analog-to-digital) converter module, a VIN (voltage input) port, a VREF (voltage reference) input port and a VOUT (voltage output) output port.

The source electrode of the N-channel enhanced MOS tube NM0 is connected with a VIN input port, the grid electrode of the N-channel enhanced MOS tube NM0 is connected with the output port of the high-voltage driving circuit module, and the drain electrode of the N-channel enhanced MOS tube NM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM 2, one end of a resistor R2 and; the source electrode of the N-channel enhanced MOS tube NM1 is grounded, the grid electrode of the N-channel enhanced MOS tube NM1 is connected with the output port of the low-voltage driving circuit module, and the drain electrode of the N-channel enhanced MOS tube NM0 is connected with the drain electrode of the resistor R2 and one end of the inductor L; the other end of the inductor L is connected with one end of the resistor R0 and the VOUT output port; the other end of the resistor R0 is connected with one end of a resistor R1 and the 3 input port of the EA module; the other end of the resistor R is grounded; the other end of the resistor R2 is connected with the upper plate of the capacitor C0 and the input port of the A/D converter module; the lower plate of the capacitor C0 is grounded; the output end of the A/D converter module is connected with the 2 input port of the EA module; an input port of the EA module 1 is connected with a VREF input port, and an output port of the EA module is connected with an input end of the PWM regulating circuit module; the input port of the PWM adjusting circuit module is connected with the output port of the EA module, the port of the output 1 is connected with the input end of the high-voltage driving circuit module 1, and the port of the output 2 is connected with the input port of the low-voltage driving circuit module; the input port of the low-voltage driving circuit module is connected with the 2 output port of the PWM adjusting circuit, and the output port of the low-voltage driving circuit module is connected with the grid electrode of an N-channel enhanced MOS (metal oxide semiconductor) transistor NM 1; the input end of the high-voltage driving circuit module 1 is connected with the output port 1 of the PWM adjusting circuit, the input port 2 is connected with the output port of the charge pump module, and the output port is connected with the grid electrode of an N-channel enhanced MOS transistor NM 0; and the input end of the charge pump is connected with a VIN input port and the drain electrode of an N-channel enhanced MOS (metal oxide semiconductor) transistor NM0, and the output end of the charge pump is connected with the input end of the high-voltage driving circuit module 2.

When the response circuit works, the charge pump module enables the voltage at the VIN input end to be higher than the VIN voltage so as to provide a driving voltage for the grid electrode of the N-channel enhancement type MOS tube NM0 through the high-voltage driving circuit. The circuit compares VFB feedback voltage of a middle node between a voltage dividing resistor R0 and a R1 connected with the output end of VOUT with VREF reference voltage through an EA module, then transmits the result to a PWM adjusting circuit module for PWM waveform adjustment, and then controls the grids of a P channel enhanced MOS (metal oxide semiconductor) transistor PM0 and an N channel enhanced MOS transistor NM0 of an upper power transistor and a lower power transistor through a driving circuit module, so that SW switching waveform is generated at the drain electrode of the P channel enhanced MOS transistor PM0, and a main loop is formed by the circuit. The SW waveform is filtered and then transmitted to the A/D converter module by adding a filter consisting of a resistor R2 and a capacitor C0 at the SW end, when the output voltage drops due to the fact that a system is disturbed, the SW waveform analog signal is converted into a corresponding digital signal through the A/D converter, the digital signal enters the EA module, a corresponding control circuit with the increased control bandwidth is started, the duty ratio of the circuit is increased in this way, and the output voltage can also be increased rapidly to counteract the disturbed output voltage. The output voltage is disturbed to rise.

The invention has the beneficial effects that:

1. the whole circuit is simple in design and completely suitable for a high-voltage CMOS (complementary metal oxide semiconductor) process, the loop detection SW waveform is simpler and quicker, and the output stable condition can be well transmitted to a main loop of the circuit to be quickly adjusted.

2. The number of bits output by the A/D converter can be increased according to actual requirements, so that adjustment of the gain of the EA module can be graded, and the size of the gain required to be increased is selected in real time according to the actual output waveform.

Drawings

Fig. 1 is a schematic diagram of a loop fast response method applicable to high-voltage BUCK according to the present invention.

Detailed Description

The invention is further illustrated with reference to the following figures and examples.

A high-voltage BUCK response circuit is shown in figure 1: the high-voltage power supply mainly comprises an N-channel enhancement type MOS transistor NM 0-NM 1, an inductor L, resistors R0-R2, a capacitor C0, a low-voltage driving circuit module, a high-voltage driving circuit module, a charge pump module, a PWM (pulse-width modulation) adjusting circuit module, an EA (emitter-emitter) module, an A/D (analog-to-digital) converter module, a VIN (voltage input) port, a VREF (reference voltage) input port and a VO.

The source electrode of the N-channel enhanced MOS tube NM0 is connected with a VIN input port, the grid electrode of the N-channel enhanced MOS tube NM0 is connected with the output port of the high-voltage driving circuit module, the drain electrode of the N-channel enhanced MOS tube NM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM 3526, one end of a resistor R2 and one; the source electrode of the N-channel enhanced MOS tube NM1 is grounded, the grid electrode of the N-channel enhanced MOS tube NM1 is connected with the output port of the low-voltage driving circuit module, the drain electrode of the N-channel enhanced MOS tube NM0 is connected with the drain electrode of the N-channel enhanced MOS tube NM 3526, one end of a resistor R2 and one end of an inductor; one end of the inductor L is connected with one end of an N-channel enhanced MOS tube NM0, an N-channel enhanced MOS tube NM1 and one end of a resistor R2, and the other end of the inductor L is connected with one end of a resistor R0 and the output port VOUT; one end of the resistor R0 is connected with the other end of the inductor L and the VOUT output port, and the other end of the resistor R0 is connected with one end of the resistor R1 and the 3 input port of the EA module; one end of the resistor R1 is connected with the other end of the resistor R0 and the 3 input port of the EA module, and the other end of the resistor R1 is grounded; one end of the resistor R2 is connected with one end of the N-channel enhanced MOS tube NM0, one end of the N-channel enhanced MOS tube NM1 and one end of the inductor L, and the other end of the resistor R2 is connected with the upper pole plate of the capacitor C0 and the input port of the A/D converter module; the upper polar plate of the capacitor C0 is connected with the other end of the resistor R2 and the input port of the A/D converter module, and the lower polar plate is grounded; the input port of the A/D converter module is connected with the other end of the resistor R2 and the upper polar plate of the capacitor C0, and the output end of the A/D converter module is connected with the 2 input port of the EA module; an input port of the EA module 1 is connected with a VREF input port, an input port of the EA module 2 is connected with an output port of the A/D converter, an input port of the EA module 3 is connected with the other end of the resistor R0 and one end of the resistor R1, and an output port of the EA module is connected with an input end of the PWM regulating circuit module; the input port of the PWM adjusting circuit module is connected with the output port of the EA module, the port of the output 1 is connected with the input end of the high-voltage driving circuit module 1, and the port of the output 2 is connected with the input port of the low-voltage driving circuit module; the input port of the low-voltage driving circuit module is connected with the 2 output port of the PWM adjusting circuit, and the output port of the low-voltage driving circuit module is connected with the grid electrode of an N-channel enhanced MOS (metal oxide semiconductor) transistor NM 1; the input end of the high-voltage driving circuit module 1 is connected with the output port 1 of the PWM adjusting circuit, the input port 2 is connected with the output port of the charge pump module, and the output port is connected with the grid electrode of an N-channel enhanced MOS transistor NM 0; and the input end of the charge pump is connected with a VIN input port and the drain electrode of an N-channel enhanced MOS (metal oxide semiconductor) transistor NM0, and the output end of the charge pump is connected with the input end of the high-voltage driving circuit module 2.

With reference to fig. 1, the working flow of the high-voltage BUCK response circuit is as follows: when the circuit works, the charge pump module enables the voltage at the VIN input end to be higher than the VIN voltage so as to provide a driving voltage for the grid electrode of the N-channel enhancement type MOS tube NM0 through the high-voltage driving circuit. The circuit compares VFB feedback voltage of a middle node between a voltage dividing resistor R0 and a R1 connected with the output end of VOUT with VREF reference voltage through an EA module, then transmits the result to a PWM adjusting circuit module for PWM waveform adjustment, and then controls the grids of a P channel enhanced MOS (metal oxide semiconductor) transistor PM0 and an N channel enhanced MOS transistor NM0 of an upper power transistor and a lower power transistor through a driving circuit module, so that SW switching waveform is generated at the drain electrode of the P channel enhanced MOS transistor PM0, and a main loop is formed by the circuit. According to the invention, a filter consisting of a resistor R2 and a capacitor C0 is added at the SW end, the SW waveform is filtered and then transmitted to the A/D converter module, when the output voltage is reduced due to the disturbance of the system, the SW waveform analog signal is converted into a corresponding digital signal through the A/D converter, the digital signal enters the EA module, a corresponding control circuit with the increased control bandwidth is started, the duty ratio of the circuit is increased by the mode, the output voltage can be rapidly increased to counteract the disturbance, and the same principle is carried out when the output voltage is disturbed and increased.

In summary, the invention provides a high-voltage BUCK response circuit and an implementation method thereof, which can effectively regulate a circuit loop. Compared with the conventional BUCK loop regulation method, the BUCK loop regulation method has the advantages that the whole circuit is simple in design, the response speed is high, the added SW detection circuit does not occupy excessive area, the internal power consumption of the circuit is low, and the quick circuit stability regulation can be realized.

Claims

1. A high-voltage BUCK response circuit is characterized in that:

the high-voltage BUCK response circuit comprises an N-channel enhancement type MOS (metal oxide semiconductor) transistor NM 0-NM 1, an inductor L, resistors R0-R2, a capacitor C0, a low-voltage driving circuit module, a high-voltage driving circuit module, a charge pump module, a PWM (pulse-width modulation) adjusting circuit module, an EA (emitter array) module, an A/D (analog-to-digital) converter module, a VIN (vehicle input) port, a VREF (reference voltage) input port and a VOUT;