CN212342619U - Three-dimensional package structure that piles up of wafer level chip fan-out - Google Patents

Three-dimensional package structure that piles up of wafer level chip fan-out Download PDF

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Publication number
CN212342619U
CN212342619U CN202022254148.1U CN202022254148U CN212342619U CN 212342619 U CN212342619 U CN 212342619U CN 202022254148 U CN202022254148 U CN 202022254148U CN 212342619 U CN212342619 U CN 212342619U
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fan
layer
chip
rewiring
packaging body
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CN202022254148.1U
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Inventor
郭洪岩
胡正勋
赵强
夏剑
张朝云
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Changdian Integrated Circuit Shaoxing Co ltd
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Changdian Integrated Circuit Shaoxing Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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Abstract

The utility model discloses a three-dimensional packaging structure that piles up of wafer level chip fan-out belongs to semiconductor packaging technical field. The packaging structure comprises a lower packaging body, a rewiring layer (150) and an upper packaging body, wherein the upper packaging body is stacked above the lower packaging body, and telecommunication connection is realized through the rewiring layer (150); and metal core solder balls (120) for interconnecting the upper packaging body and the lower packaging body are arranged around the chip I (110), so that the telecommunication connection between the upper packaging body and the lower packaging body is realized. The packaging structure adopts the high-density rewiring fan-out layer (102) of the wafer level process to replace a traditional packaging substrate, and adopts the rewiring layer on the lower packaging body to replace a patch panel, so that the thickness of the packaging body can be effectively reduced.

Description

Three-dimensional package structure that piles up of wafer level chip fan-out
Technical Field
The utility model relates to a three-dimensional packaging structure that piles up of wafer level chip fan-out belongs to semiconductor packaging technical field.
Background
In the smart terminals such as smart phones and smart watches of today, the application processor and the memory chip are generally stacked and packaged together in a Package-on-Package (PoP) manner and a Package-on-Package (Package on Package) manner. The package can shorten the path length of signal transmission between the application processor and the memory chip, improve the data processing efficiency and remarkably reduce the occupied area of the mainboard.
In a conventional PoP package, the underlying application processor is Flip-Chip mounted on a package substrate and then the Chip is encapsulated, typically using a standard Flip-Chip ball grid array Flip Chip BGA package. The interconnection between the upper package and the lower package is realized by adopting a mode of plastic package material perforation TMV (through moving via), a hole is punched on a plastic package body packaged by the lower application processor by using laser and is directly led to a reserved bonding pad of the substrate, and then a solder ball is placed in the hole to be communicated with the bonding pad. And finally, the upper memory chip is welded on the upper side and is communicated with the lower application processor through a solder ball in the TMV. In most designs, the pins of the memory chip are distributed around the periphery of the package and can be directly aligned with the TMV of the package below.
With the increasing requirements of intelligent terminals, the packaging method also has the following problems:
1. with the process nodes of the mobile terminal application processor chip becoming smaller and smaller, the packaging density becomes higher and higher, and the requirements for the packaging substrate also become higher and higher. The wiring line width/line distance of the current packaging substrate is usually 15um/15 um. Higher and higher packaging density requires more wiring layers of the substrate, which increases the thickness of the substrate and is not in line with the thinning trend of mobile terminals and wearable products. Even if the number of the substrate layers is kept unchanged, the method for reducing the thickness of the packaging body by reducing the thickness of the substrate is difficult under the current process capability condition in the industry;
2. at present, the packaging appearance of a mainstream memory chip in the industry is uniformly fixed with the I/O position, if the position of TMV cannot be corresponding to the I/O position of the memory chip in certain designs, a layer of switching layer needs to be added between the lower-layer packaging and the memory chip packaging body, the process complexity can be increased by adopting the mode, the thickness of the packaging body is increased, and the requirement of the terminal on thinning the packaging body cannot be met.
Disclosure of Invention
Bear the upper the, the utility model aims to overcome the not enough of above-mentioned PoP encapsulation, provide a three-dimensional packaging structure that piles up of wafer level chip fan-out, can effectively improve packaging density and reduce the packaging body height.
The purpose of the utility model is realized like this:
the utility model relates to a three-dimensional package structure that piles up of wafer level chip fan-out, it includes lower part packaging body, rewiring layer and upper portion packaging body, the stacking of upper portion packaging body sets up in the top of lower part packaging body to realize telecommunications connection through rewiring layer;
the lower packaging body comprises a high-density rewiring fan-out layer, a plurality of chips I, a plurality of metal core welding balls, a plastic packaging material I, under-bump metals and ball grid array welding balls, wherein the centers of the metal core welding balls are high-melting-point metal balls, and the outsides of the metal core welding balls are coated with solder; the high-density rewiring fan-out layer comprises a plurality of insulating layers and metal wiring layers which are selectively isolated, the chip I is connected to the upper surface of the high-density rewiring fan-out layer in a flip-chip mode, and ball grid array solder balls are arranged on the lower surface of the high-density rewiring fan-out layer; the metal core solder balls are arranged around the chip I and connected with the upper surface of the high-density rewiring fan-out layer, and the height of the metal core solder balls is greater than that of the chip I; the plastic packaging material I is arranged above the high-density rewiring fan-out layer to plastically package a chip I and metal core solder balls, and the metal core solder balls are partially exposed out of the upper surface of the plastic packaging material I;
the rewiring layer is arranged between the upper packaging body and the lower packaging body, the upper packaging body comprises a plurality of chips II and/or passive elements II, solder balls, a plastic packaging material II and an underfill material II, the chips II are connected with the rewiring layer through the solder balls, the underfill material II fills the bottom space of the chips II, and the plastic packaging material II is used for plastically packaging the chips II and/or the passive elements II above the rewiring layer;
and the chip II and/or the passive element II of the upper packaging body are in telecommunication connection with the chip I of the lower packaging body sequentially through the solder balls, the rewiring layer', the metal core solder balls of the lower packaging body and the high-density rewiring fan-out layer.
Furthermore, the size of the upper packaging body is larger than that of the lower packaging body, the plastic packaging material I is located above the high-density rewiring fan-out layer and is used for plastically packaging the chip I and the metal core solder balls, the edge of the high-density rewiring fan-out layer is reserved, and the plastic packaging material II of the upper packaging body is located above the rewiring layer and is used for plastically packaging the chip II and/or the passive element II, and the lower edge of the rewiring fan-out layer is plastically packaged to the edge of the high-density rewiring fan-out layer.
Further, the line width/line distance of the high-density rewiring fan-out layer is smaller than 8um/8 um.
Further, the line width/line distance of the high-density rewiring fan-out layer is as small as 1.5um/1.5 um.
Furthermore, the plastic package material I also plastically packages a passive element I, wherein the passive element I is arranged on the front surface of the high-density rewiring fan-out layer, and the height of the passive element I is smaller than that of the metal core solder ball.
Furthermore, the rewiring layer sequentially comprises an insulating layer I, a metal wiring layer, an insulating layer II and a bonding pad from bottom to top, the metal wiring layer is communicated with the metal core solder balls through an opening of the insulating layer I, the bonding pad is arranged on the metal wiring layer through an opening of the insulating layer II, and the bonding pad is provided with the solder balls.
Further, still include copper post lug and chip underfill I, the copper post lug sets up in I bottom of chip, chip I is connected with the pad on the fan-out layer of high-density rewiring through the soldering tin cap on the copper post lug of I bottom of chip, chip underfill I fills the bottom of chip I.
Furthermore, the back surface of the high-density rewiring fan-out layer is provided with under-bump metal, and ball grid array solder balls are arranged through the under-bump metal.
Advantageous effects
1. With the process nodes of the mobile terminal application processor chip becoming smaller and smaller, the packaging density becomes higher and higher, and the requirements for the packaging substrate also become higher and higher. The wiring line width/line distance of the current packaging substrate is usually 15um/15 um. Higher and higher packaging density requires more wiring layers of the substrate, which increases the thickness of the substrate and is not in line with the thinning trend of mobile terminals and wearable products. Even if the number of the substrate layers is kept unchanged, the method for reducing the thickness of the packaging body by reducing the thickness of the substrate is difficult under the current process capability condition in the industry;
2. at present, the packaging appearance of a mainstream memory chip in the industry is uniformly fixed with the I/O position, if the position of TMV cannot be corresponding to the I/O position of the memory chip in certain designs, a layer of switching layer needs to be added between the lower-layer packaging and the memory chip packaging body, the process complexity can be increased by adopting the mode, the thickness of the packaging body is increased, and the requirement of the terminal on thinning the packaging body cannot be met.
Drawings
Fig. 1 is a schematic cross-sectional view of a first embodiment of a wafer level chip fan-out three-dimensional stacked package structure according to the present invention;
FIGS. 2 to 4 are schematic distribution diagrams of a chip I and a passive component I of the lower package in FIG. 1;
fig. 5 is a schematic cross-sectional view of a second embodiment of a wafer level chip fan-out three-dimensional stacked package structure according to the present invention;
description of the main elements
High density rewiring fan-out layer 102
Chip I110
Copper pillar bump 111
Solder cap 112
Metal core solder ball 120
Solder 121
Underfill I130
Plastic packaging material I140
Redistribution layer 150
Insulating layer I151
Metal wiring layer 152
Insulating layer II 153
Pad 154
Passive element I160
Solder ball 201
Underfill II 210
Plastic packaging material II 220
Under bump metallurgy 300
Ball grid array solder balls 301.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown, so that the present disclosure fully conveys the scope of the invention to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Example one
The utility model relates to a three-dimensional packaging structure that piles up of wafer level chip fan-out contains the lower part packaging body, rewiring layer 150 and upper portion packaging body, the upper portion packaging body piles up the top that sets up at the lower part packaging body, and rewiring layer 150 sets up between upper portion packaging body and lower part packaging body, and the upper portion packaging body realizes telecommunications connection through rewiring layer 150 and lower part packaging body.
The lower package body includes a high-density rewiring fan-out layer 102, a plurality of chips i 110, a plurality of metal core solder balls 120, a molding compound i 140, under bump metal 300 and ball grid array solder balls 301, as shown in fig. 1, which is a schematic cross-sectional view of an embodiment of the wafer level chip fan-out three-dimensional stacked package structure of the present invention. The chip i 110 in the lower package is usually a logic chip using an advanced chip process, such as an application processor, and the pitch of the micro copper pillar bumps 111 on the chip i 110 is usually 40um to 70um, and the micro copper pillar bumps are soldered on the pads of the high-density rewiring fan-out layer 102 by a flip chip interconnection method. Specifically, the chip i 110 is connected to the pads on the high-density rewiring fan-out layer 102 through solder caps 112 on copper pillar bumps 111 at the bottom of the chip i 110. After the flip chip is completed, the bottom of the chip i 110 is filled with a chip underfill i 130.
The high-density rewiring fan-out layer 102 includes a plurality of selectively isolated insulating layers and metal wiring layers. Generally, the high-density rewiring fan-out layer 102 has 3 layers or more than 3 layers. The line width/line distance of the high-density rewiring fan-out layer 102 is less than 8um/8um, and preferably, the line width/line distance of the high-density rewiring fan-out layer 102 is as small as 1.5um/1.5 um.
In the lower package, the chip i 110 may be one chip, two chips, or more than two chips, or may be a combination of the chip i 110 and a passive element i 160, where the passive element i 160 includes but is not limited to a resistor and a capacitor. The chip i 110 and/or the passive component i 160 are disposed on the upper surface of the high-density rewiring fan-out layer 102, and the height thereof is smaller than the height of the metal core solder balls 120, as shown in fig. 2 to 4, which are schematic distribution diagrams of the chip i 110 and the passive component i 160 of the lower package in fig. 1.
The back of the high-density rewiring fan-out layer 102 is provided with ball grid array solder balls 301 through under bump metal 300, the pitch of the ball grid array solder balls 301 is usually 0.3mm or 0.35mm, and the ball grid array solder balls are used for forming electrical and structural connection with a printed circuit board; in some designs, the ball grid array solder balls 301 may be higher than the passive components because the passive components are required to be disposed on the backside of the package.
A metal core solder ball 120 is disposed around the chip 110, and the center of the metal core solder ball 120 is a high melting point metal ball, which includes but is not limited to copper, and is covered with solder. Since the core of the metal core solder ball 120 is usually copper metal, which has a melting point higher than that of solder metal, it will not collapse during reflow; the lower end of the metal core solder ball 120 forms a metallurgical connection with a pad reserved on the high-density rewiring fan-out layer 102 through a solder coating layer, and the upper end part of the metal core solder ball is exposed outside the lower packaging body and is connected with a rewiring layer 150 above the lower packaging body. The metal core solder balls 120, the chip I110 and the like are plastically packaged by a plastic packaging material I140 to form a lower packaging body.
A rewiring layer 150 is arranged above the lower packaging body, the rewiring layer 150 sequentially comprises an insulating layer I151, a metal wiring layer 152, an insulating layer II 153 and a bonding pad 154 from bottom to top on the upper surface of the lower packaging body, an opening of the insulating layer I151 exposes part of the metal core solder ball 120, the metal wiring layer 152 is communicated with the metal core solder ball 120 through the opening of the insulating layer I, and the bonding pad 154 is arranged on the metal wiring layer through the opening of the insulating layer II.
The upper packaging body comprises a chip II 200 and/or a passive element II, solder balls 201, a plastic packaging material II 220 and an underfill material II 210, wherein the chip II 200 is connected with the bonding pads 154 on the rewiring layer 150 through the solder balls 201, and the underfill material II 210 fills the bottom space of the chip II 200. And the plastic packaging material II 220 is used for plastically packaging the chip II 200 and/or the passive element II above the rewiring layer 150.
The utility model discloses be provided with the metal core solder ball 120 that is used for upper and lower packaging body interconnection around the chip. Specifically, the chip II 200 and/or the passive component II of the upper package are connected with the chip I110 of the lower package in a telecommunication way through the solder ball 201, the rewiring layer' 150, the metal core solder ball 120 of the lower package and the high-density rewiring fan-out layer 102 in sequence.
Example two
The utility model relates to a three-dimensional packaging structure that piles up of wafer level chip fan-out contains the lower part packaging body, rewiring layer 150 and upper portion packaging body, the upper portion packaging body piles up the top that sets up at the lower part packaging body, and rewiring layer 150 sets up between the upper portion packaging body and lower part packaging body, and the upper portion packaging body realizes telecom connection through rewiring layer 150 and lower part packaging body, as shown in figure 5.
The lower package body includes a high-density rewiring fan-out layer 102, a plurality of chips i 110, a plurality of metal core solder balls 120, a molding compound i 140, under bump metal 300 and ball grid array solder balls 301, as shown in fig. 5, which is a schematic cross-sectional view of an embodiment of the wafer level chip fan-out three-dimensional stacked package structure of the present invention. The chip i 110 in the lower package is usually a logic chip using an advanced chip process, such as an application processor, and the pitch of the micro copper pillar bumps 111 on the chip i 110 is usually 40um to 70um, and the micro copper pillar bumps are soldered on the pads of the high-density rewiring fan-out layer 102 by a flip chip interconnection method. Specifically, the chip i 110 is connected to the pads on the high-density rewiring fan-out layer 102 through solder caps 112 on copper pillar bumps 111 at the bottom of the chip i 110. After the flip chip is completed, the bottom of the chip i 110 is filled with a chip underfill i 130.
The high-density rewiring fan-out layer 102 includes a plurality of selectively isolated insulating layers and metal wiring layers. Generally, the high-density rewiring fan-out layer 102 has 3 layers or more than 3 layers. The line width/line distance of the high-density rewiring fan-out layer 102 is less than 8um/8um, and preferably, the line width/line distance of the high-density rewiring fan-out layer 102 is as small as 1.5um/1.5 um.
In the lower package, the chip i 110 may be one chip, two chips, or more than two chips, or may be a combination of the chip i 110 and a passive element i 160, where the passive element i 160 includes but is not limited to a resistor and a capacitor. The chip i 110 and/or the passive component i 160 are disposed on the front surface of the high-density rewiring fan-out layer 102, and the height thereof is smaller than the height of the metal core solder balls 120, as shown in fig. 2 to 4, which are schematic distribution diagrams of the chip i 110 and the passive component i 160 of the lower package in fig. 1.
The back of the high-density rewiring fan-out layer 102 is provided with ball grid array solder balls 301 through under bump metal 300, the pitch of the ball grid array solder balls 301 is usually 0.3mm or 0.35mm, and the ball grid array solder balls are used for forming electrical and structural connection with a printed circuit board; in some designs, the ball grid array solder balls 301 may be higher than the passive components because the passive components are required to be disposed on the backside of the package.
A metal core solder ball 120 is disposed around the chip 110, and the center of the metal core solder ball 120 is a high melting point metal ball, which includes but is not limited to copper, and is covered with solder. Since the core of the metal core solder ball 120 is usually copper metal, which has a melting point higher than that of solder metal, it will not collapse during reflow; the lower end of the metal core solder ball 120 forms a metallurgical connection with a pad reserved on the high-density rewiring fan-out layer 102 through a solder coating layer, and the upper end part of the metal core solder ball is exposed outside the lower packaging body and is connected with a rewiring layer 150 above the lower packaging body. The metal core solder balls 120, the chip I110 and the like are plastically packaged by a plastic packaging material I140 to form a lower packaging body, and the edge of the high-density rewiring fan-out layer 102 is reserved.
A rewiring layer 150 is arranged above the lower packaging body, the rewiring layer 150 sequentially comprises an insulating layer I151, a metal wiring layer 152, an insulating layer II 153 and a bonding pad 154 from bottom to top on the upper surface of the lower packaging body, an opening of the insulating layer I151 exposes part of the metal core solder ball 120, the metal wiring layer 152 is communicated with the metal core solder ball 120 through the opening of the insulating layer I, and the bonding pad 154 is arranged on the metal wiring layer through the opening of the insulating layer II.
The upper packaging body comprises a chip II 200 and/or a passive element II, solder balls 201, a plastic packaging material II 220 and an underfill material II 210, wherein the chip II 200 is connected with the bonding pads 154 on the rewiring layer 150 through the solder balls 201, and the underfill material II 210 fills the bottom space of the chip II 200. And the plastic packaging material II 220 is used for plastically packaging the chip II 200 and/or the passive element II above the rewiring layer 150, and is plastically packaged to the edge of the high-density rewiring fan-out layer 102 along the lower edge. The size of the upper package is larger than that of the lower package, so as to improve the strength of the whole package and enhance the shock resistance, as shown in fig. 5.
The utility model discloses be provided with the metal core solder ball 120 that is used for upper and lower packaging body interconnection around the chip. Specifically, the chip ii 200 and/or the passive component ii of the upper package are electrically connected to the chip i 110 of the lower package sequentially through the solder ball 201, the redistribution layer' 150, the metal core solder ball 120 of the lower package, and the high-density redistribution fan-out layer 102.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only a detailed description of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (8)

1. The wafer level chip fan-out three-dimensional stacked packaging structure is characterized by comprising a lower packaging body, a rewiring layer (150) and an upper packaging body, wherein the upper packaging body is stacked above the lower packaging body and is in telecommunication connection through the rewiring layer (150);
the lower packaging body comprises a high-density rewiring fan-out layer (102), a plurality of chips I (110), a plurality of metal core solder balls (120), a plastic packaging material I (140), under-bump metal (300) and ball grid array solder balls (301), wherein the center of each metal core solder ball (120) is a high-melting-point metal ball, and the outside of each metal core solder ball is coated with a solder material; the high-density rewiring fan-out layer (102) comprises a plurality of insulating layers and metal wiring layers which are selectively isolated, the chip I (110) is connected to the upper surface of the high-density rewiring fan-out layer (102) in a flip-chip mode, and ball grid array solder balls (301) are arranged on the lower surface of the high-density rewiring fan-out layer (102); the metal core solder balls (120) are arranged around the chip I (110), are connected with the upper surface of the high-density rewiring fan-out layer (102), and are higher than the chip I (110); the plastic package material I (140) is arranged above the high-density rewiring fan-out layer (102) to plastically package the chip I (110) and the metal core solder balls (120), and part of the metal core solder balls (120) is exposed out of the upper surface of the plastic package material I (140);
the rewiring layer (150) is arranged between the upper packaging body and the lower packaging body, the upper packaging body comprises a plurality of chips II (200) and/or passive elements II, solder balls (201), a plastic packaging material II (220) and an underfill material II (210), the chips II (200) are connected with the rewiring layer (150) through the solder balls (201), the underfill material II (210) fills the bottom space of the chips II (200), and the plastic packaging material II (220) is arranged above the rewiring layer (150) to plastically package the chips II (200) and/or the passive elements II;
and the chip II (200) and/or the passive element II of the upper packaging body are in telecommunication connection with the chip I (110) of the lower packaging body sequentially through the solder balls (201), the rewiring layer (150), the metal core solder balls (120) of the lower packaging body and the high-density rewiring fan-out layer (102).
2. The wafer level chip fan-out three-dimensional stacked package structure of claim 1, wherein the size of the upper package body is larger than that of the lower package body, the edge of the high-density rewiring fan-out layer (102) is left un-molded above the high-density rewiring fan-out layer (102) by the molding compound I (140), and the edge of the high-density rewiring fan-out layer (102) is molded by the molding compound II (220) of the upper package body above the rewiring layer (150) and/or the passive component II, and is molded to the edge of the high-density rewiring fan-out layer (102) along the lower edge.
3. The wafer level chip fan-out three dimensional stacked package structure of claim 1 or 2, wherein a linewidth/linepitch of the high density rewiring fan-out layer (102) is less than 8um/8 um.
4. The wafer level chip fan-out three dimensional stacked package structure of claim 3, wherein a linewidth/linepitch of the high density rewiring fan-out layer (102) is 1.5um/1.5 um.
5. The three-dimensional stacked package structure of fan-out of wafer level chip as claimed in claim 1 or 2, wherein the molding compound i (140) further molds a passive component i (160), and the passive component i (160) is disposed on the front surface of the high-density rewiring fan-out layer (102) and has a height smaller than that of the metal core solder balls (120).
6. The wafer level chip fan-out three-dimensional stacked packaging structure of claim 1 or 2, wherein the rewiring layer (150) sequentially comprises an insulating layer I (151), a metal wiring layer (152), an insulating layer II (153) and a bonding pad (154) from bottom to top, the metal wiring layer (152) is communicated with the metal core solder ball (120) through an opening of the insulating layer I, the bonding pad (154) is arranged on the metal wiring layer through an opening of the insulating layer II, and the bonding pad (201) is arranged on the bonding pad (154).
7. The wafer level chip fan-out three-dimensional stacked package structure of claim 1 or 2, further comprising copper pillar bumps (111) and a chip underfill i (130), wherein the copper pillar bumps (111) are disposed on the bottom of the chip i (110), the chip i (110) is connected to pads on the high-density rewiring fan-out layer (102) through solder caps (112) on the copper pillar bumps (111) on the bottom of the chip i (110), and the chip underfill i (130) fills the bottom of the chip i (110).
8. The wafer level chip fan-out three-dimensional stacked package structure of claim 1 or 2, wherein an under bump metallization (300) is disposed on a back side of the high density rewiring fan-out layer (102), and ball grid array solder balls (301) are disposed through the under bump metallization (300).
CN202022254148.1U 2020-10-12 2020-10-12 Three-dimensional package structure that piles up of wafer level chip fan-out Active CN212342619U (en)

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