CN212305345U - Transmitting detection circuit based on receiving and transmitting assembly detection mark signal processing - Google Patents
Transmitting detection circuit based on receiving and transmitting assembly detection mark signal processing Download PDFInfo
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- CN212305345U CN212305345U CN202021458094.4U CN202021458094U CN212305345U CN 212305345 U CN212305345 U CN 212305345U CN 202021458094 U CN202021458094 U CN 202021458094U CN 212305345 U CN212305345 U CN 212305345U
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Abstract
The utility model discloses an emission detection circuit based on receiving and dispatching subassembly detection sign signal processing, through setting up detection control terminal, transmission signal source, FPGA logic control circuit, DAC module and radio frequency channel, utilize detection control terminal to provide transmission detection control signal for FPGA logic control circuit and radio frequency channel, the transmission signal source provides the signal source of transmission detection for FPGA logic control circuit and DAC module; then, the radio frequency channel detects and outputs the transmission signal according to the received transmission detection control signal, and simultaneously feeds back a detection mark signal to the FPGA logic control circuit when the radio frequency is output; and finally, outputting a detection result by utilizing the FPGA logic control circuit according to the received emission detection control signal, the signal source and the detection mark signal. The utility model discloses on radio frequency channel's basis, be equipped with detection controlgear, DAC module and FPGA logic control circuit. The method aims to solve the technical problem that the judgment accuracy of successful transmission of signals on the transceiving component is not high in the prior art.
Description
Technical Field
The invention relates to the field of communication, in particular to a transmitting and detecting circuit based on signal processing of a transmitting and receiving component detecting mark.
Background
When the transceiver module performs normal transmission operation, it needs to know whether the signal is really transmitted, and detection (amplitude demodulation) is the inverse process of amplitude modulation, and it can know whether the signal is transmitted through the antenna through detection operation.
At present, circuits for realizing detection are all analog circuits, and the detection circuit mainly comprises three parts, namely: a high-frequency modulated signal source, a nonlinear device and an RC low-pass filter. The output of such a detector will depend on the amplitude of the signal (without a defined threshold), and the amplitude of the modulated wave position signal will be uncertain when the transceiver module is transmitting normally, and the false alarm rate will be high if it is determined by the output of such a detector alone. Therefore, how to improve the accuracy of determining the success of signal transmission on the transceiver module is a technical problem that needs to be solved.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide a transmitting and detecting circuit based on signal processing of a transmitting and receiving component detecting mark, and aims to solve the technical problem that in the prior art, the judgment accuracy of successful transmission of signals on the transmitting and receiving component is not high.
In order to achieve the above object, the present invention provides a transmission detection circuit based on a transceiver module detecting a flag signal, the transmission detection circuit comprising: the device comprises a detection control terminal, a transmitting signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel; the first output end of the detection control terminal is connected with the control signal input end of the radio frequency channel, and the second output end of the detection control terminal is connected with the control signal input end of the FPGA logic control circuit; the first output end of the transmitting signal source is connected with the transmitting signal input end of the FPGA logic control circuit, and the second output end of the transmitting signal source is connected with the transmitting signal input end of the DAC module; the transmitting signal output end of the DAC module is connected with the transmitting signal input end of the radio frequency channel; the first output end of the radio frequency channel is connected with the detection mark signal input end of the FPGA logic control circuit; wherein:
preferably, the detection control terminal provides a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel; the transmitting signal source provides a transmitting and detecting signal source for the FPGA logic control circuit and the DAC module;
preferably, the radio frequency channel detects and outputs the transmission signal according to the received transmission detection control signal, or inputs the reception signal; meanwhile, feeding back a detection mark signal to the FPGA logic control circuit during radio frequency output;
preferably, the FPGA logic control circuit is connected to the control end of the DAC module to provide a clock signal and a control signal for the DAC module, and the FPGA logic control circuit outputs a detection result according to the received transmission detection control signal, the signal source, and the detection flag signal.
Preferably, the radio frequency channel comprises a radio frequency transmitting channel, a radio frequency receiving channel, a radio frequency state switch circuit, a radio frequency power switch circuit and a first power supply; the output end of the radio frequency transmitting channel and the input end of the radio frequency receiving channel are connected with a receiving and transmitting antenna, and the access of the radio frequency transmitting channel and the radio frequency receiving channel is controlled through a radio frequency state switch circuit; the radio frequency power supply switch circuit controls the connection and the access of the radio frequency channel and the first power supply.
Preferably, the radio frequency channel further comprises a detection circuit, the detection circuit is connected with the radio frequency transmitting channel and the receiving transmitting antenna, and when the radio frequency channel receives the signal source of the DAC module and transmits and outputs the signal, the detection circuit returns the detection mark signal of the radio frequency channel to the FPGA logic control circuit.
Preferably, the DAC module comprises a DAC chip, a DAC power switch circuit, and a second power supply; the DAC chip receives a clock signal and a chip control signal sent by the FPGA logic control circuit, converts a digital signal transmitted by a transmitting signal source into an analog signal and transmits the analog signal to a radio frequency channel; and the DAC power switch circuit controls the connection and the access of the DAC chip and a second power supply.
Preferably, the detection control terminal is used for sending transmission detection control signals to the radio frequency channel and the FPGA logic control circuit respectively, and the detection control signals comprise a receiving and transmitting switching control signal TR and a transmission power switch control signal AM; the FPGA logic control circuit receives the detection marking signal sent by the radio frequency channel according to the receiving and sending switching control signal TR and the transmitting power switch control signal AM.
Preferably, the FPGA logic control circuit executes the state machine to output the transmission detection result according to the amplitude value of the signal I/Q sent by the transmission signal source and the received detection flag signal.
According to the invention, by arranging a detection control terminal, a transmission signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel, the detection control terminal is utilized to provide a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel, and the transmission signal source provides a signal source for transmission detection for the FPGA logic control circuit and the DAC module; then, the radio frequency channel detects the transmission signal according to the received transmission detection control signal and outputs the transmission signal in a radio frequency mode, and meanwhile, a detection mark signal is fed back to the FPGA logic control circuit when the radio frequency signal is output; and finally, outputting a detection result by utilizing the FPGA logic control circuit according to the received emission detection control signal, the signal source and the detection mark signal. The invention is provided with a DAC module for detecting control equipment and radio frequency emission and an FPGA logic control circuit for judging and outputting detection results on the basis of a radio frequency channel. The method aims to solve the technical problem that the judgment accuracy of successful transmission of signals on the transceiving component is not high in the prior art.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of a transmitting and detecting circuit based on the processing of a detecting mark signal of a transceiver module according to the present invention;
fig. 2 is a schematic diagram of the operation steps of an embodiment of a transmitting and detecting circuit based on the processing of the detecting mark signal of the transceiver module.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
The present invention provides an embodiment, referring to fig. 1, fig. 1 is a schematic structural diagram of a transmitting and detecting circuit based on the processing of a detecting mark signal of a transceiver module.
As shown in fig. 1, in the present embodiment, a transmission detector circuit based on a transceiver module detecting a flag signal process, the transmission detector circuit includes: the device comprises a detection control terminal, a transmitting signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel; the first output end of the detection control terminal is connected with the control signal input end of the radio frequency channel, and the second output end of the detection control terminal is connected with the control signal input end of the FPGA logic control circuit; the first output end of the transmitting signal source is connected with the transmitting signal input end of the FPGA logic control circuit, and the second output end of the transmitting signal source is connected with the transmitting signal input end of the DAC module; the transmitting signal output end of the DAC module is connected with the transmitting signal input end of the radio frequency channel; the first output end of the radio frequency channel is connected with the detection mark signal input end of the FPGA logic control circuit; wherein:
it should be noted that the detection control terminal provides a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel; the transmitting signal source provides a transmitting and detecting signal source for the FPGA logic control circuit and the DAC module;
it should be noted that, the radio frequency channel detects and outputs the transmission signal according to the received transmission detection control signal, or inputs the reception signal; meanwhile, feeding back a detection mark signal to the FPGA logic control circuit during radio frequency output;
it should be noted that the FPGA logic control circuit is connected to the control end of the DAC module to provide a clock signal and a control signal for the DAC module, and meanwhile, the FPGA logic control circuit outputs a detection result according to the received transmission detection control signal, the signal source, and the detection flag signal.
Furthermore, in this embodiment, the rf channel includes an rf transmitting channel, an rf receiving channel, an rf status switch circuit, an rf power switch circuit, and a first power supply; the output end of the radio frequency transmitting channel and the input end of the radio frequency receiving channel are connected with a receiving and transmitting antenna, and the access of the radio frequency transmitting channel and the radio frequency receiving channel is controlled through a radio frequency state switch circuit; the radio frequency power supply switch circuit controls the connection and the access of the radio frequency channel and the first power supply.
In this embodiment, the rf channel further includes a detection circuit, the detection circuit is connected to the rf transmitting channel and the receiving transmitting antenna, and when the rf channel receives the signal source of the DAC module and transmits and outputs the signal, the detection circuit returns the detection flag signal of the rf channel to the FPGA logic control circuit.
Furthermore, in this embodiment, the DAC module includes a DAC chip, a DAC power switch circuit, and a second power supply; the DAC chip receives a clock signal and a chip control signal sent by the FPGA logic control circuit, converts a digital signal transmitted by a transmitting signal source into an analog signal and transmits the analog signal to a radio frequency channel; and the DAC power switch circuit controls the connection and the access of the DAC chip and a second power supply.
Furthermore, in this embodiment, the detection control terminal is configured to send transmission detection control signals to the radio frequency channel and the FPGA logic control circuit, respectively, where the detection control signals include a transmit-receive switching control signal TR and a transmit power switch control signal AM; the FPGA logic control circuit receives the detection marking signal sent by the radio frequency channel according to the receiving and sending switching control signal TR and the transmitting power switch control signal AM.
Furthermore, in the embodiment, the FPGA logic control circuit executes the state machine to output the transmission detection result according to the amplitude value of the signal I/Q sent by the transmission signal source and the received detection flag signal.
It should be understood that, as shown in fig. 2, the transmission detection method of the present embodiment mainly includes the following steps:
s1, setting the transceiving function of a transceiving component to be controlled by control signals TR and AM:
TR is a receiving and transmitting switching control signal, and when TR is 1, switching to a transmitting state is indicated; when TR is 0, switching to a receiving state is indicated;
the AM is a control signal of a transmitting power switch, the transmitting power switch is turned on when the AM is 1, and the transmitting power switch is turned off when the AM is 0;
s2, before signal transmission, firstly enabling TR to be 1, switching to a transmission state, then enabling a control signal AM to be 1, turning on a transmission power switch, and starting signal transmission;
s3, when the signal is transmitted out through the radio frequency channel, the radio frequency channel can output a detection mark signal (if the mark signal is directly used as a final judgment result of transmission and detection, the judgment can be unstable and even wrong);
and S4, after the signal transmission is finished, firstly setting the AM to be 0, then setting the control signal TR to be 0, entering a receiving state, and waiting for the coming of the next transmission process.
And S5, executing a program running state machine by the controller (FPGA) according to the amplitude value of the transmission signal I/Q and the detection mark signal obtained in the S3, and finally outputting a transmission detection judgment signal.
In the embodiment of the present application, if the transmitting power supply is in the on state (AM ═ 1) and switches to the receiving state (TR ═ 0), in this case, the transmitting signal will wander in the transmitting channel, eventually burning the device, so this must be avoided; therefore, in the receiving state (TR ═ 0), the transmission power switch (AM ═ 0) must be turned off some time ahead (1 us in the embodiment of the present application).
In the receiving state, no signal is sent to the radio frequency channel through a digital-to-analog converter (DAC), and it is normal that the radio frequency channel does not output the emission detection mark signal in the receiving state. The procedure must therefore avoid the decision to transmit detect in the receive state.
To this end, we first set a fixed threshold d0 according to the bit width of the DAC, and on one hand, many experiments have proved that: if the digital-to-analog converter is sent to the DAC according to the value of d0 and is transmitted out through a radio frequency channel, the FPGA can receive a transmission detection mark signal; on the other hand, the I/Q values sent to the DAC in the receiving state are both 0, and the amplitude value cannot exceed d0, so that the judgment of emission detection in the receiving state is effectively avoided. In addition, to obtain a stable and correct final decision result, the number of detections needs to be accumulated, so the program uses a state machine to implement this process, specifically:
specifically, the implementation of step S5 includes the following steps:
s501, calculating
(ImaxAnd QmaxAre determined by the bit width of the DAC, I is 14 bitsmax＝16384，Qmax＝16384，d0＝5793)。
S502, the program sets a detection counter, which sets a fixed initial value c0 (in this example, c0 is 40) when the power supply is reset.
S503, during the time that TR is equal to 1 and AM is equal to 1, the controller (FPGA) calculates the amplitude value of the transmission data I/Q
S504. for each transmission, if d1> -d 0, the transmitted I/Q data is considered as valid detected data, and the program state machine will check the detection flag signal returned by the rf channel in the next state and count into the detection counter: c0+1 when the detection flag is detected (the detection counter sets the maximum detection count c1, in this example, c1 is equal to 250), and c0-1 when the detection flag is not detected (the detection counter sets the minimum detection count c2, in this example, c2 is equal to 10), until the transmission process is finished; if d1< d0, the transmitted I/Q data is considered invalid detected data, and the program state machine will remain in the current state until the end of the transmission (no matter what relationship between d1 and d0, the I/Q data is still transmitted normally).
And S505, when the system normally transmits (generally, multiple times of continuous transmission), if the detection counter value is lower than c2, judging that the transmission detection is fault, otherwise, judging that the transmission detection is normal.
In the embodiment of the present application, the specific transmission detection implementation principle of the transmission detection circuit based on the transceiver component detection flag signal processing is as follows:
the FPGA is arranged at the output end of a radio frequency channel in the transceiving component, an FPGA program processes a transmitting detection mark signal output by the radio frequency channel, and TR and AM signals are generated by baseband processing equipment or external equipment in the embodiment; the TR signal is used for controlling a receiving and transmitting change-over switch, and when the TR is 0, the receiving and transmitting change-over switch is switched to a receiving channel and is connected with a receiving and transmitting antenna; when TR is 1, the receiving and transmitting switch is switched to a transmitting channel to connect the transmitting channel with a receiving and transmitting antenna; in the whole embodiment, power is supplied by an external power supply, and except for the transmitting channel and the DAC, power is uniformly and directly supplied only after the transmitting and receiving assembly is started; the external power supply supplies power to the transmitting channel and the DAC through the transmitting power switch, and the on-off of the transmitting power switch is controlled by an AM signal; when AM is 1, the transmitting power switch is turned on, and when AM is 0, the transmitting power switch is turned off; in this embodiment, TR and AM signals generated by the baseband signal processing device or the external device need to be transmitted to the FPGA at the same time, so as to implement the final decision of the transmission detection according to the above steps S501 to S505.
The I/Q data rate transmitted from a channel to a DAC (14 bits) is 80MHz, firstly, the I/Q data is converted into a signal amplitude value after being subjected to Cordic (IP core) conversion, and on one hand, a program state machine of the FPGA compares the amplitude value with a fixed threshold (5793); on the other hand, the amplitude value is simultaneously transmitted to the DAC, the DAC transmits the output analog signal out through the radio frequency channel, and the radio frequency channel comprises a detection analog circuit, so that when the amplitude of the transmitted signal is not lower than 5793, the radio frequency channel can output a detection mark signal to the FPGA. The FPGA carries out accumulation counting on detection mark signals output by the radio frequency channel through a program running state machine, and practice proves that: if the RF channel is faulty, the program state will continuously subtract 1 from the demodulation counter during transmission until the demodulation counter reaches the lower limit and (quickly) output the demodulation fault information; otherwise, the normal detection information is rapidly output.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (6)
1. A transmission detector circuit based on transceiver module detection flag signal processing, the transmission detector circuit comprising: the device comprises a detection control terminal, a transmitting signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel; the first output end of the detection control terminal is connected with the control signal input end of the radio frequency channel, and the second output end of the detection control terminal is connected with the control signal input end of the FPGA logic control circuit; the first output end of the transmitting signal source is connected with the transmitting signal input end of the FPGA logic control circuit, and the second output end of the transmitting signal source is connected with the transmitting signal input end of the DAC module; the transmitting signal output end of the DAC module is connected with the transmitting signal input end of the radio frequency channel; the first output end of the radio frequency channel is connected with the detection mark signal input end of the FPGA logic control circuit; wherein:
the detection control terminal provides a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel; the transmitting signal source provides a transmitting and detecting signal source for the FPGA logic control circuit and the DAC module;
the radio frequency channel detects and outputs a transmission signal in a radio frequency mode according to the received transmission detection control signal, or inputs a received signal in a radio frequency mode; meanwhile, feeding back a detection mark signal to the FPGA logic control circuit during radio frequency output;
the FPGA logic control circuit is connected with the control end of the DAC module to provide a clock signal and a control signal for the DAC module, and meanwhile, the FPGA logic control circuit outputs a detection result according to the received emission detection control signal, the signal source and the detection mark signal.
2. The transmission detection circuit based on transceiver component detection flag signal processing of claim 1, wherein the radio frequency path comprises a radio frequency transmission path, a radio frequency reception path, a radio frequency state switch circuit, a radio frequency power switch circuit, and a first power supply; the output end of the radio frequency transmitting channel and the input end of the radio frequency receiving channel are connected with a receiving and transmitting antenna, and the access of the radio frequency transmitting channel and the radio frequency receiving channel is controlled through a radio frequency state switch circuit; the radio frequency power supply switch circuit controls the connection and the access of the radio frequency channel and the first power supply.
3. The transmitting and detecting circuit based on the transceiving component detection mark signal processing as claimed in claim 2, wherein the rf channel further comprises a detection circuit, the detection circuit is connected to the rf transmitting channel and the receiving and transmitting antenna, and when the rf channel receives the signal source of the DAC module and transmits the output, the detection circuit returns the detection mark signal of the rf channel to the FPGA logic control circuit.
4. The transmit detector circuit based on transceiver component detection flag signal processing as claimed in claim 3, wherein said DAC module comprises a DAC chip, a DAC power switch circuit and a second power supply; the DAC chip receives a clock signal and a chip control signal sent by the FPGA logic control circuit, converts a digital signal transmitted by a transmitting signal source into an analog signal and transmits the analog signal to a radio frequency channel; and the DAC power switch circuit controls the connection and the access of the DAC chip and a second power supply.
5. The transmission/reception module demodulation mark signal processing-based transmission/detection circuit according to claim 4, wherein the detection control terminal is configured to send transmission/detection control signals to the rf channel and the FPGA logic control circuit, respectively, the detection control signals including a transmission/reception switching control signal TR and a transmission power switch control signal AM; the FPGA logic control circuit receives the detection marking signal sent by the radio frequency channel according to the receiving and sending switching control signal TR and the transmitting power switch control signal AM.
6. The transmit detector circuit of claim 5, wherein the FPGA logic control circuit implements the state machine to output the transmit detection result based on the amplitude value of the I/Q signal transmitted from the transmit signal source and the received detection flag signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021458094.4U CN212305345U (en) | 2020-07-22 | 2020-07-22 | Transmitting detection circuit based on receiving and transmitting assembly detection mark signal processing |
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| CN202021458094.4U CN212305345U (en) | 2020-07-22 | 2020-07-22 | Transmitting detection circuit based on receiving and transmitting assembly detection mark signal processing |
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| CN212305345U true CN212305345U (en) | 2021-01-05 |
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Inventor after: Du Ying Inventor after: Tan Zunlin Inventor after: Cao Chengjian Inventor after: He Hengzhi Inventor after: Xu Kexing Inventor before: Tan Zunlin Inventor before: Cao Chengjian Inventor before: He Hengzhi Inventor before: Xu Kexing |