CN212302471U - Multi-channel serial communication interface based on level conversion circuit - Google Patents

Multi-channel serial communication interface based on level conversion circuit Download PDF

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Publication number
CN212302471U
CN212302471U CN202020952781.5U CN202020952781U CN212302471U CN 212302471 U CN212302471 U CN 212302471U CN 202020952781 U CN202020952781 U CN 202020952781U CN 212302471 U CN212302471 U CN 212302471U
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circuit
level conversion
level
conversion module
serial communication
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左杰翰
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The utility model discloses a multi-path serial communication interface based on a level conversion circuit, which relates to the technical field of internet communication and comprises a control circuit and an interface circuit connected with the control circuit and used for realizing multi-path serial communication; the memory, the reset circuit, the clock circuit, the power circuit and the JTAG auxiliary circuit are respectively connected with the DSP; the interface circuit comprises a protocol processor, a decoder, an isolation circuit and a level conversion circuit, wherein the decoder is connected with the protocol processor, and the protocol processor is connected with the level conversion circuit through the isolation circuit. The TMS320C6748 is used as a core processor, parallel communication with an asynchronous communication protocol chip TL16C754 is realized through an EMIF bus, a multi-bit chip selection signal is expanded by a 3-8 decoder 74LS138, the function of integrally expanding a multi-path serial communication interface is realized, when a high-power-consumption device is applied to the working of low-power-consumption electronic equipment, the power consumption of the high-power-consumption device is controlled, and the working stability of the low-power-consumption electronic equipment is improved.

Description

Multi-channel serial communication interface based on level conversion circuit
Technical Field
The utility model relates to an internet communication technology field especially relates to a multichannel serial communication interface based on level shift circuit.
Background
At present, a microprocessor DSP is a device for implementing a digital signal processing algorithm, and the particularity of the hardware structure is that an internal memory adopts a harvard structure with a program bus and a data bus separated, and has a special hardware multiplier. However, in the application field of embedded DSP systems, it is generally required to perform data interaction and communication with multiple external devices at the same time, wherein the serial communication interface is still a widely adopted technology at present because of its simplicity and reliability, and the current DSP has fewer serial ports and cannot satisfy the capability of multiple serial communication interfaces.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that not enough the providing a multichannel serial communication interface based on level shift circuit to background art, it adopts TMS320C6748 as core processor, realizes through the EMIF bus and asynchronous communication agreement chip TL16C754 parallel communication, adopts 3-8 decoder 74LS138 to expand many chip select signals, realizes the function of integrated extension multichannel serial communication interface.
The utility model discloses a solve above-mentioned technical problem and adopt following technical scheme:
a multi-channel serial communication interface based on level conversion circuit comprises a control circuit and a multi-channel serial communication interface connected with the control circuit and used for realizing multi-channel serial communication
An interface circuit for serial communication;
the control circuit includes a DSP processor, a memory, a reset circuit, a clock circuit, a power circuit, and JTAG assistance
The memory, the reset circuit, the clock circuit, the power supply circuit and the JTAG auxiliary circuit are respectively connected with the DSP;
the interface circuit comprises a protocol processor, a decoder, an isolation circuit and a level conversion circuit, wherein the decoder is connected with the protocol processor, and the protocol processor is connected with the level conversion circuit through the isolation circuit;
the level conversion circuit comprises a signal input end, a signal output end, a first level conversion module and a second level conversion module, wherein the first level conversion module is used for converting a high level signal input by the signal input end into a low level signal, and the second level conversion module is used for converting a low level signal output by the first level conversion module into a high level signal; the level of the high level signal output by the second level conversion module after conversion is lower than that of the high level signal input by the signal input end;
the input end of the first level conversion module is connected with the signal input end, the output end of the first level conversion module is connected with the input end of the second level conversion module, and the output end of the second level conversion module is connected with the signal output end;
the first level conversion module comprises a first power supply, a first N-channel MOS tube, a first resistor and a first capacitor, wherein the grid electrode of the first N-channel MOS tube is connected with the input end of the first level conversion module, the source electrode of the first N-channel MOS tube is grounded, the drain electrode of the first N-channel MOS tube is connected with one end of the first resistor, the other end of the first resistor is connected with the first power supply, the anode of the first capacitor is connected with the drain electrode of the first N-channel MOS tube and the output end of the first level conversion module, and the cathode of the first capacitor is grounded;
the second level conversion module comprises a second power supply, a second N-channel MOS tube, a second resistor and a second capacitor, the grid electrode of the second N-channel MOS tube is connected with the input end of the second level conversion module, the source electrode of the second N-channel MOS tube is grounded, the drain electrode of the second N-channel MOS tube is connected with one end of the second resistor, the other end of the second resistor is connected with the second power supply, the anode of the second capacitor is connected with the drain electrode of the second N-channel MOS tube and the output end of the second level conversion module, and the cathode of the second capacitor is grounded.
As the utility model relates to a further preferred scheme of multichannel serial communication interface based on level shift circuit, DSP treater chooses for use the floating point operation low-power consumption chip TMS320C6748 of TI, and its dominant frequency is 456 MHz, has the operational capability up to 3648 MIPS and 2756 MFLOPS.
As a further preferred embodiment of the multi-channel serial communication interface based on the level shift circuit of the present invention, the clock circuit employs a clock signal output by a 24 MHz OSC external clock crystal.
As the utility model relates to a further preferred scheme of multichannel serial communication interface based on level shift circuit, power supply circuit adopts integrated power supply mode, and kernel voltage and IO voltage are supplied power through same power module promptly, and kernel voltage is 1.2V, and IO voltage is 1.8V and 3.3V, adopts power management chip TPS650061 RUK.
As a further preferred aspect of the present invention, the reset circuit employs a reset chip based on IPM 811.
As a preferred embodiment of the utility model relates to a multichannel serial communication interface based on level shift circuit, level shift circuit is still including the third electric capacity that is used for the filtering, the negative pole one end ground connection of third electric capacity, its positive pole one end connect in signal input part reaches the centre department of first level shift module input, and parallelly connected with first N channel MOS pipe, first electric capacity, second N channel MOS pipe and second electric capacity respectively
As the utility model relates to a further preferred scheme of multichannel serial communication interface based on level shift circuit, the memory contains RAM memory and Flash memory, RAM memory and Flash memory are connected with the DSP treater respectively, RAM memory adopts the high-speed RAMMT47H64M16 chip of low-power consumption of TI, Flash memory adopts the S29GL128N chip of SPANSION company.
As a further preferred scheme of multichannel serial communication interface based on level shift circuit of the utility model, RAM memory adopts the high-speed RAMMT47H64M16 chip of low-power consumption of TI, Flash memory adopts the S29GL128N chip of SPANSION company.
As a further preferred solution of the multi-channel serial communication interface based on the level shift circuit of the present invention, the protocol processor employs a TL16C754 chip.
As a further preferred scheme of the multi-channel serial communication interface based on the level shift circuit of the present invention, the isolation circuit employs a six-channel digital isolator ADuM7643 of the ADI company for digital isolation of the interface circuit.
As the utility model relates to a further preferred scheme of multichannel serial communication interface based on level shift circuit, level shift circuit adopts drive bus transceiver MAX490, realizes RS422 signal transceiver function.
The utility model adopts the above technical scheme to compare with prior art, have following technological effect:
1. the utility model discloses a satisfy the requirement of miniaturization and integration, need control a plurality of serial ports and external equipment communication, adopt TMS320C6748 as core processor, realize and asynchronous communication agreement chip TL16C754 parallel communication through the EMIF bus, adopt 3-8 decoder 74LS138 to expand many bit chip selection signals, realize the function of integrated extension multichannel serial communication interface, the bottom drive is based on TI's real-time operation system kernel SYS/BIOS develops, can reduce the degree of difficulty of design, and the development cycle has been shortened, can realize the complete receipt of multichannel data, data transmission is complete reliable;
2. the utility model adopts the EMIF control mode of DSP to complete the data transmission, realizes the integration and the expansion of the interface through the asynchronous communication protocol chip and the decoder, solves the speed problem of data transmission between the internal memory and the peripheral equipment of DSP, lightens the operation load of DSP, and improves the real-time performance and the reliability of serial traffic;
3. the utility model discloses realizing that the high-power consumption device is applied to low-power consumption electronic equipment during operation, controlling its consumption, improving the stability of low-power consumption electronic equipment work.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following embodiments or prior arts will be described
While the drawings that are needed to be utilized in the description of the invention have been described briefly, it should be apparent that the drawings in the description that follows are illustrative of the invention
It will be apparent to one of ordinary skill in the art that the embodiments may be practiced without the use of the inventive faculty
From these figures further figures are obtained.
Fig. 1 is a schematic diagram of the system structure of the present invention.
Fig. 2 is a circuit diagram of the level shift circuit of the present invention.
Reference numbers in the figures: 10-a first level conversion module, 20-a second level conversion module, 30-a signal input terminal, 40-a signal output terminal, 101-an input terminal of a first level conversion circuit, 102-an output terminal of the first level conversion circuit, 201-an input terminal of a second level conversion circuit, and 202-an output terminal of the second level conversion circuit.
Detailed Description
The technical scheme of the utility model is further explained in detail with the attached drawings as follows:
the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
A multi-channel serial communication interface based on a level conversion circuit is shown in figure 1 and comprises a control circuit and an interface circuit connected with the control circuit and used for realizing multi-channel serial communication;
the control circuit includes a DSP processor, a memory, a reset circuit, a clock circuit, a power circuit, and JTAG assistance
The memory, the reset circuit, the clock circuit, the power supply circuit and the JTAG auxiliary circuit are respectively connected with the DSP;
the interface circuit comprises a protocol processor, a decoder, an isolation circuit and a level conversion circuit, wherein the decoder is connected with the protocol processor, and the protocol processor is connected with the level conversion circuit through the isolation circuit.
As shown in fig. 2, the level shift circuit includes a signal input terminal 30, a signal output terminal 40, a first level shift module 10 for converting a high level signal input from the signal input terminal 30 into a low level signal, and a second level shift module 20 for converting a low level signal output from the first level shift module 10 into a high level signal; the level of the high level signal output by the second level shift module 20 after the shift is lower than that of the high level signal input by the signal input terminal 30.
The first level shift module 10 and the second level shift module 20 have an input end and an output end, the input end 101 of the first level shift module is connected to the signal input end 30, the output end 102 of the first level shift module is connected to the input end 201 of the second level shift module, and the output end 202 of the second level shift module is connected to the signal output end 40;
the first level shift module 10 includes a first power source VCC1, a first N-channel MOS transistor Q1, a first resistor R1, and a first capacitor C1, a gate G of the first N-channel MOS transistor Q1 is connected to the input terminal 101 of the first level shift module, a source S of the first N-channel MOS transistor Q1 is connected to a ground terminal GND, a drain D of the first N-channel MOS transistor Q1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the first power source VCC1, an anode of the first capacitor C1 is connected to the drain D of the first N-channel MOS transistor Q1 and the output terminal 102 of the first level shift module, and a cathode of the first capacitor C1 is connected to the ground terminal GND;
in the embodiment, the high level signal input by the signal input end 30 is converted into the low level signal through the first level conversion module 10, and then the low level signal is converted into the high level signal output by the power supply through the second level conversion module 20, the high level signal is output to the low power consumption electronic device through the signal output end 30, the high level signal output by the signal output end 40 is lower than the high level signal input by the signal input end 40, it is ensured that the level can be effectively controlled when the high power consumption device is applied to the low power consumption electronic device, and thus the working stability of the low power consumption electronic device is improved.
The pass signal input end 30 is connected to the input end 101 of the first level conversion module, and after a high level or a low level is input through the first level conversion module 10, the input high level is converted into the low level, and the input low level is converted into the high level, so that the conversion of the high level and the low level is completed. The first capacitor C1 is used for filtering the output of the first level shifter 10 and the input of the first level shifter 20, and the first resistor R1 is used for limiting the current.
The second level shift module 20 includes a second power source VCC2, a second N-channel MOS transistor Q2, a second resistor R2 and a second capacitor C2, the gate G of the second N-channel MOS transistor Q2 is connected to the input terminal 201 of the second level shift module, the source S of the second MOS transistor Q2 is grounded GND, the drain S of the second N-channel MOS transistor Q2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the second power source VCC2, the positive electrode of the second capacitor C2 is connected to the drain S of the second N-channel MOS transistor Q2 and the output terminal 202 of the second level shift module, and the negative electrode of the second capacitor C2 is grounded GND. In this embodiment, the input end 201 of the second level conversion module is connected to the output end 102 of the first level conversion module, after the high level or the low level is input through the second level conversion module 20, the input high level is converted into the low level, the input low level is converted into the high level, the conversion of the high level and the low level is completed, the output end 202 of the second level conversion module is connected to the signal output end 40, the output of the high level and the low level is controlled, the power-on function of the second power supply is controlled, and therefore the converted level is suitable for the operation of the low-power electronic device. It should be noted that the second capacitor C2 is used for filtering the output of the first level shifter module 20, and the second resistor R2 is used for limiting the current.
When the high-power-consumption device is applied to the low-power-consumption electronic equipment to work, the power consumption of the high-power-consumption device is controlled, and the working stability of the low-power-consumption electronic equipment is improved;
preferably, the core processor DSP selects a TI floating point operation low-power consumption chip TMS320C6748, the main frequency of the chip TMS is 456 MHz, and the chip TMS has the operation capability of 3648 MIPS and 2756 MFLOPS.
The clock circuit uses a clock signal as the output of a 24 MHz OSC external clock crystal.
The power supply circuit adopts an integrated power supply mode, namely, the core voltage and the I/O voltage are supplied by the same power supply module, the core voltage is 1.2V, the I/O voltage is 1.8V and 3.3V, the system adopts a power supply management chip TPS650061RUK with higher efficiency, the efficiency can reach 90 percent, and the required voltage drop is small.
The reset circuit is designed by adopting an IPM811 reset chip, the chip not only has power-on reset and manual reset functions, but also has a power supply voltage monitoring function, and low-level effective reset signals with the minimum duration of 140 ms can be output.
The RAM memory adopts a TI low-power-consumption high-speed RAMMT47H64M16 chip, and can provide larger program execution/data storage space for the DSP. The Flash memory adopts an S29GL128N chip of SPANSION company for solidified storage of system software.
The protocol processor adopts a TL16C754 chip which is a universal asynchronous serial communication controller, has automatic software/hardware flow control capability, has 64-byte FIFO which can store and buffer data transmission [6] between two asynchronous clocks, and can realize interruption by programming different trigger levels; the data can be programmed into 5 bit, 6 bit, 7 bit or 8 bit, and is used for format conversion of UART parallel data and serial data. The decoder adopts a 3-8 decoder 74LS138 chip and can carry out 8-bit data conversion.
The system is connected with an 8-bit data bus of 16C754A through an EMIF data bus of TMS320C6748, the address of TL16C754 is configured in an EMIF mapping space, the EMIF address bus of TMS320C6748 is used for expanding 8-bit chip selection signals through a 3-8 decoder 74LS138, and gating of 8 paths of RS422 interface signals is achieved.
The isolation circuit adopts a six-channel digital isolator ADuM7643 of ADI company to realize the digital isolation of the interface circuit.
The level conversion circuit adopts a driving bus transceiver MAX490 to realize the RS422 signal transceiving function. The transceiver is a low-power consumption transceiver, is used for [7] in serial data interface standard systems such as RS422 and the like, is internally provided with a driving module and a receiving module, and has the maximum transmission rate of 2.5 Mb/s.
The EMIF interface 8-bit data lines are in one-to-one correspondence with the TL16C754 ports, normal communication between the DSP and external equipment is guaranteed, and external interruption of the DSP can be triggered when external data are sent. In the decoder circuit, 8 different chip selection signals are generated through 3 address signals, when the decoder generates one path of gating, corresponding parallel data can be transmitted to a bus to wait for receiving.
The utility model discloses a satisfy the requirement of miniaturization and integration, need control a plurality of serial ports and external equipment communication, adopt TMS320C6748 as core processor, realize and asynchronous communication agreement chip TL16C754 parallel communication through the EMIF bus, adopt 3-8 decoder 74LS138 to expand many bit chip selection signals, realize the function of integrated extension multichannel serial communication interface, the bottom drive is based on TI's real-time operation system kernel SYS/BIOS develops, can reduce the degree of difficulty of design, and the development cycle has been shortened, can realize the complete receipt of multichannel data, data transmission is complete reliable;
the utility model discloses a transmission of data is accomplished to DSP's EMIF control mode, realizes the integration and the extension of interface through asynchronous communication agreement chip and decoder, has solved data transmission's between DSP internal memory and the peripheral hardware speed problem, has alleviateed DSP's operation load, has improved serial current real-time and reliability.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Above embodiment only is for explaining the utility model discloses a technical thought can not be injectd with this the utility model discloses a protection scope, all according to the utility model provides a technical thought, any change of doing on technical scheme basis all falls into the utility model discloses within the protection scope. Although the embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the scope of knowledge possessed by those skilled in the art.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims (10)

1. A multi-channel serial communication interface based on a level conversion circuit is characterized in that: the device comprises a control circuit and an interface circuit which is connected with the control circuit and is used for realizing multi-path serial communication;
the memory, the reset circuit, the clock circuit, the power circuit and the JTAG auxiliary circuit are respectively connected with the DSP;
the interface circuit comprises a protocol processor, a decoder, an isolation circuit and a level conversion circuit, wherein the decoder is connected with the protocol processor, and the protocol processor is connected with the level conversion circuit through the isolation circuit;
the level conversion circuit comprises a signal input end, a signal output end, a first level conversion module and a second level conversion module, wherein the first level conversion module is used for converting a high level signal input by the signal input end into a low level signal, and the second level conversion module is used for converting a low level signal output by the first level conversion module into a high level signal; the level of the high level signal output by the second level conversion module after conversion is lower than that of the high level signal input by the signal input end;
the input end of the first level conversion module is connected with the signal input end, the output end of the first level conversion module is connected with the input end of the second level conversion module, and the output end of the second level conversion module is connected with the signal output end;
the first level conversion module comprises a first power supply, a first N-channel MOS tube, a first resistor and a first capacitor, wherein the grid electrode of the first N-channel MOS tube is connected with the input end of the first level conversion module, the source electrode of the first N-channel MOS tube is grounded, the drain electrode of the first N-channel MOS tube is connected with one end of the first resistor, the other end of the first resistor is connected with the first power supply, the anode of the first capacitor is connected with the drain electrode of the first N-channel MOS tube and the output end of the first level conversion module, and the cathode of the first capacitor is grounded;
the second level conversion module comprises a second power supply, a second N-channel MOS tube, a second resistor and a second capacitor, the grid electrode of the second N-channel MOS tube is connected with the input end of the second level conversion module, the source electrode of the second N-channel MOS tube is grounded, the drain electrode of the second N-channel MOS tube is connected with one end of the second resistor, the other end of the second resistor is connected with the second power supply, the anode of the second capacitor is connected with the drain electrode of the second N-channel MOS tube and the output end of the second level conversion module, and the cathode of the second capacitor is grounded.
2. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the DSP processor selects a TI floating point operation low-power consumption chip TMS320C6748, the main frequency of the chip TMS is 456 MHz, and the DSP processor has the operation capability of 3648 MIPS and 2756 MFLOPS.
3. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the clock circuit adopts a clock signal to be output by a 24 MHz OSC external clock crystal.
4. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the power supply circuit adopts an integrated power supply mode, namely, the core voltage and the I/O voltage are supplied by the same power supply module, the core voltage is 1.2V, the I/O voltage is 1.8V and 3.3V, and a power supply management chip TPS650061RUK is adopted.
5. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the reset circuit adopts a chip reset based on IPM 811.
6. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the level conversion circuit further comprises a third capacitor for filtering, one end of the negative electrode of the third capacitor is grounded, and one end of the positive electrode of the third capacitor is connected to the middle of the signal input end and the input end of the first level conversion module and is respectively connected with the first N-channel MOS tube, the first capacitor, the second N-channel MOS tube and the second capacitor in parallel.
7. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the memory comprises an RAM memory and a Flash memory, the RAM memory and the Flash memory are respectively connected with the DSP, the RAM memory adopts a low-power-consumption high-speed RAMMT47H64M16 chip of TI, and the Flash memory adopts an S29GL128N chip of SPANSION corporation.
8. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the protocol processor employs a TL16C754 chip.
9. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the isolation circuit adopts a six-channel digital isolator ADuM7643 of ADI company for realizing digital isolation of the interface circuit.
10. The multi-channel serial communication interface based on the level shift circuit as claimed in claim 1, wherein: the level conversion circuit adopts a driving bus transceiver MAX490 to realize the RS422 signal transceiving function.
CN202020952781.5U 2020-05-29 2020-05-29 Multi-channel serial communication interface based on level conversion circuit Expired - Fee Related CN212302471U (en)

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CN212302471U true CN212302471U (en) 2021-01-05

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