CN212277911U - Overvoltage protection circuit - Google Patents

Abstract

The utility model discloses an overvoltage protection circuit, which comprises a first current mirror unit, a second current mirror unit, a resistance voltage division unit and a hysteresis comparator; the current input end of the first current mirror unit is connected with a circuit power ground through an NMOS tube NM1, a resistor R2 and an NMOS tube NM2, the mirror current end of the first current mirror unit is connected with the circuit power ground through a resistor voltage division unit, the current input end of the second current mirror unit is connected with a reference current source I1, and the mirror current end of the second current mirror unit is connected with a sampling signal end V of the resistor voltage division unit_GSConnected to another of the resistive voltage-dividing unitsThe sampling signal end Va is connected with the inverting input end of the hysteresis comparator, the positive phase input end of the hysteresis comparator is connected with the reference voltage Vref, and the output end of the hysteresis comparator outputs an overvoltage protection signal. Supply voltage protection circuit, circuit area is little, low in manufacturing cost not only is fit for using discrete device to build the practicality, and easily chip internal integration.

Description

Overvoltage protection circuit

Technical Field

The utility model relates to an electronic circuit technical field especially relates to an overvoltage crowbar.

Background

Electronic products all have its rated operating voltage scope, and mains voltage is too high or low excessively, can lead to the work of electronic product unusual, even causes the damage of consumer, therefore in electronic product's inside, generally design mains voltage protection circuit. For example, in a switching power supply control chip, an overvoltage protection circuit is a very important circuit module. The overvoltage protection circuit has the function of monitoring the power supply voltage of an electronic product in real time in the working process of the electronic product, and when the power supply voltage is too high, an overvoltage protection signal is output to stop a system from working, so that the chip is prevented from continuously working under the condition of the too high power supply voltage to cause the damage of an internal circuit. After the overvoltage protection circuit is used for protecting the hair, if the power supply voltage continues to rise, a power supply clamping circuit in the overvoltage protection circuit is started, the power supply voltage of the chip is limited within a safe range, and the chip is prevented from being damaged due to overhigh power supply voltage.

A common implementation of an over-voltage protection circuit is shown in fig. 1. In fig. 1, VDD _ HV is a high-voltage power supply, VCC is a low-voltage power supply, vb1 and vb2 are gate bias voltages of PMOS transistors PM1 and PM2, resistors R1, R2, R3, R4, zener diodes D1, D2, D3, and D4 form a VDD _ HV detection circuit, and high-voltage NMOS transistor NM4 is a power supply clamp device. The overvoltage protection working principle of the circuit is as follows: when the system works normally, the voltage VDD _ HV is smaller than the overvoltage protection voltage VDD _ OVP, and the VDD _ HV detection circuit is not conductedDo, therefore V_GSIs pulled down to a low level by the resistor R4 so that V_GSLess than threshold voltage V of high voltage NMOS transistor NM5_TH,NM5The switch tube NM5 is turned off, the potential of the point a is pulled up to high level by the PMOS tubes PM1 and PM2, and an overvoltage protection signal VDD _ OVP _ N is output to be high level after passing through the inverter inv1 and the Schmitt trigger smit 1. When VDD _ HV rises to make all the voltage stabilizing diodes D1-D4 break down reversely, the VDD _ HV detection circuit is conducted, current starts to flow through the resistor R3 and the resistor R4, VDD _ HV continues rising, and V_GSAlso increases when V_GSGreater than V_TH,NM5When the voltage at the point a is pulled down to a low level by the NM5, the overvoltage protection signal VDD _ OVP _ N is inverted to a low level, and the system enters an overvoltage protection state and stops working. NM4 and NM5 in the circuit are high-voltage NMOS tubes of the same type, when NM5 is started, a clamping device NM4 is also started to work, and at the moment, the circuit starts a power supply clamping function.

Another common over-voltage protection circuit scheme is shown in fig. 2. In fig. 2, resistors R1 and R2 form a resistor voltage dividing unit to monitor the power supply voltage VDD _ HV in real time, resistors R4, R5 and R6 form another resistor voltage dividing unit, and NPN triodes VT1 and VT2 and a PMOS transistor PM1 are used as switching devices to control the on and off of the circuit.

The working principle of the overvoltage protection circuit is as follows: when the power supply voltage is in a normal working voltage range, the sampling voltage value of the point a of the resistance voltage dividing unit is small and is not enough to conduct the NPN triode VT1, and at this time, the resistance voltage dividing unit formed by the resistors R4, R5 and R6 generates a high potential at the point B, so that the NPN triode VT2 is conducted, and the voltage at the point C is pulled down to a low level, so that the switching tube PM1 is normally conducted, and the output signal VDD is VDD _ HV, and a power supply signal is accessed to the device to normally supply power to the electric device. When the power supply voltage rises to exceed the normal working voltage range, the voltage at the point A is increased to the conducting voltage of the triode VT1, the VT1 is started, the voltage at the point B is pulled down to a low level, at the moment, the triode VT2 enters a turn-off state, the voltage at the point C is pulled up to a high level by the resistor R7 from the low level during normal working, the switching tube PM1 is turned off, the electric equipment is disconnected with the power supply, and the equipment is prevented from being damaged due to overhigh external voltage.

The power supply overvoltage protection and clamping circuit of the scheme 1 has the following defects:

(1) the scheme needs to be realized by connecting a plurality of voltage stabilizing diodes in series, and occupies a larger circuit area. The circuit mainly utilizes the reverse breakdown characteristic of the voltage stabilizing diode to realize the overvoltage protection function, and the higher the overvoltage protection voltage is, the more the number of the required voltage stabilizing diodes is. For example, the overvoltage protection voltage is designed to be 30V, the reverse breakdown voltage of the Zener diode is generally 5-7V, so at least 4 Zener diodes are needed, the circuit area of the Zener diodes is larger, and the circuit area is obviously increased due to the increase of the number of the Zener diodes.

(2) This solution does not allow for a flexible design of the overvoltage protection voltage. As described in (1), the scheme mainly uses the series connection of the reverse breakdown voltages of the zener diodes to obtain the overvoltage protection voltage value, and limits the flexibility of the VDD _ OVP value to a large extent, because the VDD _ OVP can only be designed as an integral multiple of the reverse breakdown voltage of the zener diodes in this case, which causes the VDD _ OVP design adjustment to be difficult, and the overvoltage protection voltage cannot be flexibly designed.

(3) The overvoltage protection signal output by the scheme is easy to generate error overturning. The overvoltage protection turnover threshold value of the circuit is the same as the turnover threshold value of overvoltage protection removal, and when overvoltage protection occurs to a system, if power supply voltage generates certain fluctuation due to external factors, V is enabled to be equal_GSVoltage at NM5 threshold voltage V_TH,NM5The nearby fluctuation causes the NM5 to be repeatedly turned on and off, so that the overvoltage protection signal VDD _ OVP _ N is mistakenly turned over, and the circuit cannot work normally.

The power supply overvoltage protection circuit of the scheme 2 has the following defects:

(1) the overvoltage protection circuit has more types of devices, and if the overvoltage protection circuit is designed in an integrated circuit as a circuit module, the manufacturing process of a chip is complicated, and the manufacturing cost of a wafer is increased. The scheme adopts a resistor as a sampling circuit, and respectively uses a triode and an MOS tube as switching devices to control the circuit to work, and the circuit also comprises a capacitance element. The more types of devices in the circuit, the more mask levels are required to be manufactured in the wafer manufacturing process, and meanwhile, the photoetching times in production are increased, so that the wafer manufacturing cost can be obviously increased.

(2) The overvoltage protection circuit of the scheme is susceptible to power supply voltage fluctuation and unstable in work. If the power supply voltage fluctuates above and below the minimum operating voltage, the voltage at the point B is unstable, and the switching tubes VT2 and PM1 are repeatedly turned on and off, the external power supply cannot be normally supplied, so that the electric product cannot work. When the power supply voltage fluctuates near the overvoltage protection voltage, the voltage fluctuation at the point A is easily caused, so that the VT1 tube is repeatedly turned on and off, the PM1 is repeatedly turned on and off, and the circuit cannot normally work.

(3) The overvoltage protection circuit of the scheme has larger static power consumption. The circuit adopts the triodes VT1 and VT2 as the switching devices, and because the triodes are driven by current to start to work, the switching tubes VT1 and VT2 consume certain base current when conducting to work, and static power consumption is increased.

SUMMERY OF THE UTILITY MODEL

Therefore, it is desirable to provide an overvoltage protection circuit, which solves the problems of the related art overvoltage protection circuit.

In order to achieve the above object, the present invention provides an overvoltage protection circuit, which includes a first current mirror unit, a second current mirror unit, a resistance voltage dividing unit, and a hysteresis comparator;

the current input end of the first current mirror unit is connected with a circuit power ground through an NMOS tube NM1, a resistor R2 and an NMOS tube NM2, the mirror current end of the first current mirror unit is connected with the circuit power ground through a resistor voltage division unit, the current input end of the second current mirror unit is connected with a reference current source I1, and the mirror current end of the second current mirror unit is connected with a sampling signal end V of the resistor voltage division unit_GSAnd the other sampling signal end Va of the resistance voltage division unit is connected with the inverting input end of the hysteresis comparator, the positive phase input end of the hysteresis comparator is connected with the reference voltage Vref, and the output end of the hysteresis comparator outputs an overvoltage protection signal.

Further, the first current mirror unit comprises a PMOS pipe PM1 and a PMOS pipe PM2, the source electrode of the PMOS pipe PM1 and the source electrode of the PMOS pipe PM2 are connected with the positive electrode of a circuit power supply, the grid electrode of the PMOS pipe PM1 and the drain electrode of the PMOS pipe PM1 are connected with the grid electrode of the PMOS pipe PM2 and the drain electrode of the NMOS pipe NM1, and the drain electrode of the PMOS pipe PM2 is connected with the resistance voltage division unit.

Further, the second current mirror unit comprises an NMOS transistor NM3, an NMOS transistor NM4 and an NMOS transistor NM5, the drain of the NMOS transistor NM3 is connected to the gate of the NMOS transistor NM3 and the reference current source I1, the source of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM4, the gate of the NMOS transistor NM4 and the gate of the NMOS transistor NM5, the source of the NMOS transistor NM4 and the source of the NMOS transistor NM5 are grounded, and the drain of the NMOS transistor NM5 is connected to a sampling signal terminal V of the resistive voltage divider unit_GSAnd (4) connecting.

Furthermore, the transistor further comprises an NMOS transistor NM2, the drain of the NMOS transistor NM2 is connected to one end of a resistor R2, the other end of the resistor R2 is connected to the source of the NMOS transistor NM1, the gate of the NMOS transistor NM2 is connected to the control signal UVLO _ P, and the source of the NMOS transistor NM2 is grounded.

Further, the voltage divider further comprises an NMOS tube NM6, a drain of the NMOS tube NM6 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to another sampling signal terminal Va of the resistor voltage divider, a gate of the NMOS tube NM6 is connected to the control signal UVLO _ P, a source of the NMOS tube NM6 is connected to a sampling signal terminal V of the resistor voltage divider_GSAnd (4) connecting.

Further, the resistance voltage dividing unit comprises a resistor R3, a resistor R4 and a resistor R5 which are connected in sequence, and another sampling signal end V of the resistance voltage dividing unit is arranged between the resistor R4 and the resistor R5_GSAnother sampling signal terminal Va of the resistance voltage dividing unit is between the resistance R3 and the resistance R4.

Further, the power supply circuit further comprises an NMOS tube NM1, the drain of the NMOS tube NM1 is connected with the current input end of the first current mirror unit, the source of the NMOS tube NM1 is connected with a resistor R2, the gate of the NMOS tube NM1 is connected with one end of a resistor R1 and the cathode of a diode D1, the other end of the resistor R1 is connected with the positive electrode of the power supply, and the anode of the diode D1 is grounded.

Further, the voltage divider further comprises an NMOS transistor NM7, the source of the NMOS transistor NM7 is grounded, and the gate of the NMOS transistor NM7 is connected to a sampling signal terminal V of the resistance voltage divider unit_GSAnd the drain electrode of the NMOS tube NM7 is connected with the positive electrode of the circuit power supply.

Further, the hysteresis comparator comprises a PMOS transistor PM3, a source of the PMOS transistor PM3 is connected to a comparator power supply VCCA, a source of the PMOS transistor PM4, a source of the PMOS transistor PM5, a source of the PMOS transistor PM6 and a source of the PMOS transistor PM7, a gate of the PMOS transistor PM3 is connected to a drain of the PMOS transistor PM3, a drain of the NMOS transistor NM3, a gate of the PMOS transistor PM3 and a gate of the PMOS transistor PM3, a gate of the NMOS transistor NM3 is connected to a bias voltage Vb 3, a source of the NMOS transistor NM3 is connected to a drain of the NMOS transistor NM3, a drain of the PMOS transistor PM3 is connected to a gate of the PMOS transistor PM3 and a source of the PMOS transistor PM3, a drain of the PMOS transistor NM3 is connected to a drain of the NMOS transistor NM3 and a gate of the NMOS transistor NM3, a gate vinpm Vinp of the hysteresis comparator is in-phase, a drain of the PMOS transistor PM3 and a drain of the PMOS transistor PM3 are connected to a drain of the PMOS transistor 3, a drain of the PMOS transistor PM3 and a drain of the PMOS transistor 3, a drain, the drain of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM12 and the gate of the NMOS transistor NM15, the gate of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM6, the source of the PMOS transistor PM11 and the source of the PMOS transistor PM12, the drain of the PMOS transistor PM11 is connected to the source of the NMOS transistor NM14, the drain of the NMOS transistor NM13 and the gate of the NMOS transistor NM13, the gate of the PMOS transistor PM11 and the gate of the PMOS transistor PM12 Vinm are the inverting input terminal of the hysteresis comparator, the drain of the PMOS transistor PM12 is connected to the drain of the NMOS transistor NM14, the drain of the NMOS transistor NM15 is connected to the drain of the PMOS transistor PM7 and the input terminal of the inverter, the output terminal of the inverter is connected to the gate of the NMOS transistor NM14 as the output terminal of the hysteresis comparator, and the source of the NMOS transistor NM9, the source of the NMOS transistor NM10, the source of the NMOS transistor NM11, the source of the NMOS transistor NM12, the source of the NMOS transistor NM 8253 and.

Further, the grounding of the source of the NMOS transistor NM9 includes: the source electrode of the NMOS transistor NM8 is connected with the drain electrode of the NMOS transistor NM9, the gate electrode of the NMOS transistor NM9 is connected with a bias voltage Vb2, and the source electrode of the NMOS transistor NM9 is grounded;

or: the source of the NMOS transistor NM10 grounded includes: the drain electrode of the PMOS tube PM10 is connected with the drain electrode of the NMOS tube NM10 and the grid electrode of the NMOS tube NM10, and the source electrode of the NMOS tube NM10 is grounded;

or: the source of the NMOS transistor NM13 grounded includes: the drain of the PMOS transistor PM11 is connected to the drain of the NMOS transistor NM13 and the gate of the NMOS transistor NM13, and the source of the NMOS transistor NM13 is grounded.

Compared with the prior art, the technical scheme has the following advantages:

1. supply voltage protection circuit, circuit area is little, low in manufacturing cost, easily chip internal integration. The utility model discloses a circuit adopts resistance partial pressure unit to add hysteresis comparator form and realizes the overvoltage protection function, compares with traditional zener diode implementation and has reduced circuit area, has reduced manufacturing cost. Therefore the utility model discloses the circuit not only is fit for using discrete device to build the use, also is fit for very much the integration and uses inside the chip.

2. In an embodiment of the present invention, the power consumption of the overvoltage protection circuit is low. The utility model discloses an overvoltage crowbar, start signal UVLO _ P control start-up work through inside under-voltage locking circuit output, before inside start signal does not export, overvoltage crowbar forbids work, guarantees that overvoltage crowbar does not produce quiescent current before the official start-up work of system. After the overvoltage circuit is started to work, the maximum working current of the resistance voltage division unit is limited by adjusting the bias proportion of the current mirror, the circuit current is effectively controlled, and the power consumption of the circuit is reduced.

3. Overvoltage protection circuit can adjust the overvoltage protection value in a flexible way, adapt to the requirement of different system designs. The utility model discloses an overvoltage protection adopts resistance partial pressure unit to add the comparator form and realizes the overvoltage protection function, and simple structure can know by circuit theory of operation when comparator COMP1 inverting input signal Va is greater than homophase input reference voltage Vref, exports the overvoltage protection signal promptly. The sampling signal Va is determined by the proportion of the resistance of the resistor R4 in the branch, and the overvoltage protection voltage value can be changed by adjusting the proportion of the resistance. Therefore the utility model discloses an overvoltage crowbar of resistance partial pressure form can set up VDD _ OVP parameter wantonly, and more traditional zener diode series connection form is convenient nimble more.

4. Overvoltage protection circuit, the overvoltage protection signal of output is stable, is difficult to produce mistake upset phenomenon. An overvoltage protection comparator COMP1 in the circuit is a hysteresis comparator, and the important function of the hysteresis comparator is to ensure that a rising turning point of a signal is not equal to a falling turning point, and a certain hysteresis quantity exists between the rising turning point and the falling turning point, so that overvoltage protection release voltage is smaller than overvoltage protection voltage by a certain value when the overvoltage protection circuit works, and if the fluctuation amplitude of the positive electrode VDD _ HV voltage of a circuit power supply is within the hysteresis range, the overvoltage protection signal cannot be influenced by power supply fluctuation and repeatedly turned over, and the normal operation of the overvoltage protection function of the circuit is effectively ensured.

Drawings

FIG. 1 is a circuit diagram of a power over-voltage protection and clamping circuit according to the prior art;

FIG. 2 is a circuit diagram of another power over-voltage protection circuit of the prior art;

FIG. 3 is a circuit diagram of an embodiment of an over-voltage protection circuit;

fig. 4 is a circuit diagram of a hysteresis comparator circuit according to an embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to fig. 4, the overvoltage protection circuit provided in the present embodiment is shown in fig. 3: the high voltage PMOS transistors PM1 and PM2 constitute a first current mirror unit. The reference current source I1 is a bias current generated by a reference current circuit inside the system, and the current I2 is obtained through the mirror image processing of the second current mirror unit. The resistors R3, R4 and R5 form a resistor voltage dividing unit, Va is a sampling voltage, and PM2 is operated in a linear region by setting a proper voltage dividing resistor, so that the linear change of Va with VDD _ HV is guaranteed. The high-voltage NMOS transistor NM7 is a clamping device and realizes a voltage clamping function. COMP1 is a hysteresis comparator. The high voltage NMOS transistors NM2 and NM6 are switching devices, and are turned on and off by the UVLO _ P signal. The UVLO _ P signal is a circuit starting signal output by an under-voltage locking circuit in the system, the UVLO _ P is at a low level before the system starts to work, and the UVLO _ P is at a high level after the system starts to work.

The utility model discloses a power overvoltage protection circuit theory of operation is: when the system starts to work, the UVLO _ P is turned to high level, NM2 and NM6 are conducted, the overvoltage protection circuit starts to work, and the power supply voltage VDD _ HV is monitored. At the moment, the voltage stabilizing diode D1 clamps the grid voltage of the high-voltage NMOS tube NM1 to the voltage stabilizing voltage, at the moment, NM1 is conducted, the branch where NM1 is located starts to generate current, and the first current mirror unit biases to provide working current for the resistance voltage dividing unit.

When the system works normally, the sampling voltage Va on the resistance voltage dividing unit is smaller than the reference voltage Vref of the non-inverting input end of the hysteresis comparator COMP1, and the output signal VDD _ OVP _ N of the COMP1 is at a high level. The sampling voltage Va gradually increases along with the gradual increase of VDD _ HV, when VDD _ HV increases to VDD _ OVP, Va is larger than the reference voltage Vref, the overvoltage protection signal VDD _ OVP _ N output by COMP1 is inverted to a low level, and the control system enters an overvoltage protection state. The voltage V at the resistor R5_GSThreshold voltage V less than NM7_TH,NM7The NM7 tube remains off and the circuit does not turn on the clamp function. When VDD _ HV continues to rise, let V_GSIncreased to equal V_TH,NM7At this time, NM7 is turned on and the circuit enters a clamp protection state. The supply voltage at which the required clamping current is reached is typically referred to as the clamping voltage VDD _ CLAMP.

Then there is the VDD _ OVP equation according to circuit principles as follows:

when VDD is VDD _ OVP,

when VDD is VDD _ CLAMP,

in the above formula V_GS1V when VDD _ HV is VDD _ OVP_GSVoltage, V_GS2V when VDD _ HV is VDD _ CLAMP_GSA voltage. In the design process, by selecting appropriate resistance values of R3, R4 and R5, V is ensured when VDD _ HV is VDD _ OVP_GS1＜V_TH,NM7NM7 cannot be turned on, when VDD _ HV is slightly larger than VDD _ OVP, the circuit turns on the clamp function. When VDD _ HV is VDD _ CLAMP, V_GS＝V_GS2At this time, the current flowing through NM7 is the clamp current required by the design.

The utility model discloses an its overvoltage protection voltage of overvoltage protection circuit sets up through adjusting the resistance proportion. Analysis of the circuit principle shows that the size of Va can be adjusted by changing the proportion of the resistor R4 in the resistor voltage dividing unit. When the proportion of R4 is reduced, Va generated by the same VDD _ HV is reduced, and a larger VDD _ HV is needed to enable the output signal of the comparator COMP1 to be inverted, i.e. the overvoltage protection voltage is increased. Similarly, when the proportion of R4 is increased, VDD _ HV is required to be smaller to flip VDD _ OVP _ N, i.e. the overvoltage protection voltage is decreased.

The utility model discloses a required clamper size of power supply clamping circuit is less. On a pure resistance voltage-dividing unit, V is increased along with VDD _ HV_GSThe voltage change is slow and a large clamp device is required to generate the required clamp current at the designed clamp voltage. The utility model discloses a current mirror structure that the circuit passes through NM3, NM4 and NM5 and constitutes carries out the mirror image processing to biasing current I1 and obtains electric current I2, makes V_GSThe voltage VDD _ HV increases rapidly, and only a small clamp device is needed to achieve the required clamp current at the designed clamp voltage. Consequently compare with simple resistance voltage divider unit, the utility model discloses an introduced bias current I2 in the circuit, used the less clamp device of size just can produce bigger clamp current under same clamp voltage, effectively reduced clamp device size in the design, further reduced the area expense, reduced manufacturing cost.

The utility model discloses comparator COMP1 that adopts in the circuit is hysteresis comparator, can solve the output signal mistake upset problem that arouses because of voltage fluctuation to a certain extent, makes the overvoltage protection signal not influenced when mains voltage has little fluctuation, improves the stability of overvoltage protection signal. The turnover threshold values of the common comparator in the rising and falling processes of the input signal are the same, and when the input signal has slight interference, the output signal can generate corresponding fluctuation. Specifically, the output signal of a common comparator switches states when two input voltages are equal, so that when the two input signals are close to each other, the output of the comparator has uncertainty, and if the input signal has interference noise, the output signal of the comparator switches states repeatedly, that is, the output is turned over by mistake, so that the circuit cannot work normally. The hysteresis comparator has a hysteresis effect, and provides different forward flipping threshold values and reverse flipping threshold values for the sampling signal Va at the input end, so that the hysteresis comparator has strong anti-jamming capability. For avoiding VDD _ HV voltage fluctuation to arouse overvoltage comparator output signal mistake upset, consequently the utility model discloses used hysteresis comparator in the circuit, guaranteed that overvoltage protection removes and has certain hysteresis quality between voltage and the overvoltage protection voltage, when supply voltage fluctuation range is less than the hysteresis quality, can not cause the upset of overvoltage protection signal mistake. The overvoltage protection signal output when the power supply VDD _ HV signal fluctuates within the hysteresis quantity range is ensured to be stable, the circuit can be ensured to enter a protection state correctly, and the reliability of the circuit is improved.

The structure of the hysteresis comparator in the circuit of the present invention is shown in fig. 4. Vb1 and Vb2 in the circuit of FIG. 4 are internal bias signals and provide bias voltages for the hysteresis comparators to generate bias currents required for operation. Compared with the common comparator, the two input signals of the hysteresis comparator are not directly transmitted to the differential pair grid of the comparator, but are respectively connected to the differential pair grid for comparison through PMOS tubes PM10, PM11 and PM 12. Wherein NM14 is a switch tube, and is connected with PM12 in series, and the output signal Vout of the comparator is used for controlling the on and off of NM14, thereby controlling whether PM12 is connected into the circuit, so as to change the ratio of width-to-length ratios of PM10, PM11 and PM12, and realize the hysteresis function of the comparator.

The working principle of the hysteresis comparator is as follows: if Vinm is selected as the reference voltage input terminal, Vinp is the comparison signal input terminal. Vinp is gradually increased from a low level, when Vinp is less than Vinm, the output Vout of the comparator is at a low level, NM14 is turned off, and PM12 is not switched into the circuit. When Vinp increases to make Vb equal to Vc, Vout inverts to a high level, and the inversion threshold voltage at this time is referred to as a positive inversion voltage V +. When Vout is changed into a high level, the NM14 is controlled to be started, the PM12 is connected into the circuit, at the moment, the PM11 is connected with the PM12 in parallel, the size proportion of MOS (metal oxide semiconductor) tubes at two signal input ends is changed, therefore, the overturning threshold value is also changed when Vinp is reversely changed, the overturning threshold value voltage at the moment is called as a reverse overturning voltage V-, and therefore the purpose of comparing hysteresis is achieved.

The comparator hysteresis equation can be described as:

V_HYS＝(V+)-(V-) (4)

the comparator circuit principle shows that:

V+＝Vinm+V_GS,PM11-V_GS,PM10；

V-＝Vinm+V_GS,PM11'-V_GS,PM10。

therefore, there are:

V_HYS＝V_GS,PM11-V_GS,PM11' (5)

for forward comparison, PM11 gate-source voltage:

PM11 gate-source voltage at reverse comparison:

the formula (4), the formula (5), the formula (6) and the formula (7) are combined to obtain:

in the above formula I_PM6Is the PM6 tube current, the magnitude of which is equal to PCurrent mirror ratio of M3, K_PFor PMOS tube process parameters, (W/L)_PM11Is the width to length ratio of the PM11 tube, (W/L)_PM12Is the width to length ratio of the PM12 tube. Equation (8) above demonstrates that comparator hysteresis can be adjusted by adjusting PM11, PM12 size, and PM6 tube current I_PM6And (5) controlling.

In the above embodiment, the first current mirror unit, the second current mirror unit, the resistance voltage dividing unit, and the hysteresis comparator are not limited to the structures listed in the above embodiments, and may be other structures that can achieve the same function. The NMOS transistors NM2 and NM6 may be turned on and off, and may be omitted in some embodiments, so that the circuit is always turned on. The NMOS transistor NM7 implements a voltage clamp, which may be omitted in non-essential embodiments.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims (10)

1. An overvoltage protection circuit, characterized by: the circuit comprises a first current mirror unit, a second current mirror unit, a resistance voltage division unit and a hysteresis comparator;

the current input end of the first current mirror unit is connected with a circuit power ground through an NMOS tube NM1, a resistor R2 and an NMOS tube NM2, the mirror current end of the first current mirror unit is connected with the circuit power ground through a resistor voltage division unit, the current input end of the second current mirror unit is connected with a reference current source I1, and the mirror current end of the second current mirror unit is connected with a sampling signal end V of the resistor voltage division unit_GSThe other sampling signal end Va of the resistance voltage division unit is connected with the inverting input end of the hysteresis comparator, the positive phase input end of the hysteresis comparator is connected with the reference voltage Vref, and the hysteresis comparatorThe output terminal of the over-voltage protection circuit outputs an over-voltage protection signal.

2. The overvoltage protection circuit of claim 1, wherein: the first current mirror unit comprises a PMOS pipe PM1 and a PMOS pipe PM2, the source electrode of the PMOS pipe PM1 and the source electrode of the PMOS pipe PM2 are connected with the positive electrode of a circuit power supply, the grid electrode of the PMOS pipe PM1 and the drain electrode of the PMOS pipe PM1 are connected with the grid electrode of the PMOS pipe PM2 and the drain electrode of the NMOS pipe NM1, and the drain electrode of the PMOS pipe PM2 is connected with the resistance voltage division unit.

3. The overvoltage protection circuit of claim 1, wherein: the second current mirror unit comprises an NMOS tube NM3, an NMOS tube NM4 and an NMOS tube NM5, the drain of the NMOS tube NM3 is connected with the grid of the NMOS tube NM3 and the reference current source I1, the source of the NMOS tube NM3 is connected with the drain of the NMOS tube NM4, the grid of the NMOS tube NM4 and the grid of the NMOS tube NM5, the source of the NMOS tube NM4 and the source of the NMOS tube NM5 are grounded, and the drain of the NMOS tube NM5 is connected with a sampling signal end V of the resistance voltage dividing unit_GSAnd (4) connecting.

4. The overvoltage protection circuit of claim 1, wherein: the NMOS transistor NM2 is further included, the drain of the NMOS transistor NM2 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with the source of the NMOS transistor NM1, the gate of the NMOS transistor NM2 is connected with a control signal UVLO _ P, and the source of the NMOS transistor NM2 is grounded.

5. The overvoltage protection circuit of claim 1, wherein: the voltage divider further comprises an NMOS tube NM6, the drain electrode of the NMOS tube NM6 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the other sampling signal end Va of the resistor voltage dividing unit, the grid electrode of the NMOS tube NM6 is connected with a control signal UVLO _ P, and the source electrode of the NMOS tube NM6 is connected with one sampling signal end V of the resistor voltage dividing unit_GSAnd (4) connecting.

6. The overvoltage protection circuit of claim 1, wherein: the resistance voltage division unit comprises a resistor R3, a resistor R4 and a resistor R5 which are sequentially connected, wherein a resistor R4 and a resistor R5 are arranged betweenAnother sampling voltage V of the resistance voltage-dividing unit_GSAnother sampling voltage Va of the resistance voltage dividing unit is between the resistance R3 and the resistance R4.

7. The overvoltage protection circuit of claim 1, wherein: the power supply circuit further comprises an NMOS tube NM1, the drain of the NMOS tube NM1 is connected with the current input end of the first current mirror unit, the source of the NMOS tube NM1 is connected with a resistor R2, the grid of the NMOS tube NM1 is connected with one end of a resistor R1 and the cathode of a voltage stabilizing diode D1, the other end of the resistor R1 is connected with the positive electrode of the circuit power supply, and the anode of the voltage stabilizing diode D1 is grounded.

8. The overvoltage protection circuit of claim 1, wherein: the voltage divider further comprises an NMOS tube NM7, the source electrode of the NMOS tube NM7 is grounded, and the grid electrode of the NMOS tube NM7 is connected with a sampling voltage V of the resistance voltage dividing unit_GSAnd the drain electrode of the NMOS tube NM7 is connected with the positive electrode of the circuit power supply.

9. The overvoltage protection circuit of claim 1, wherein: the hysteresis comparator comprises a PMOS tube PM3, the source of the PMOS tube PM3 is connected with a comparator power supply VCCA, the source of the PMOS tube PM4, the source of the PMOS tube PM5, the source of the PMOS tube PM6 and the source of the PMOS tube PM7, the gate of the PMOS tube PM3 is connected with the drain of the PMOS tube PM3, the drain of the NMOS tube NM3, the gate of the PMOS tube PM3 and the gate of the PMOS tube PM3, the gate of the NMOS tube NM3 is connected with a bias voltage 36vb, the source of the NMOS tube NM3 is connected with the drain of the NMOS tube NM3, the drain of the PMOS tube PM3 is connected with the gate of the NMOS tube NM3, the drain of the PMOS tube PM3 is connected with the drain of the NMOS tube NM3 and the gate of the NMOS tube NM3, the VinPvNM gate of the PMOS tube PM3 is connected with the drain of the PMOS tube PM3, the drain of the PMOS tube PM3 and the drain of the NMOS tube PM3, the PMOS tube PM3 is connected with the drain of the NMOS tube PM3, the drain of the NMOS tube PM3 and the drain of the, the drain of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM12 and the gate of the NMOS transistor NM15, the gate of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM6, the source of the PMOS transistor PM11 and the source of the PMOS transistor PM12, the drain of the PMOS transistor PM11 is connected to the source of the NMOS transistor NM14, the drain of the NMOS transistor NM13 and the gate of the NMOS transistor NM13, the gate of the PMOS transistor PM11 and the gate of the PMOS transistor PM12 Vinm are the inverting input terminal of the hysteresis comparator, the drain of the PMOS transistor PM12 is connected to the drain of the NMOS transistor NM14, the drain of the NMOS transistor NM15 is connected to the drain of the PMOS transistor PM7 and the input terminal of the inverter, the output terminal of the inverter is connected to the gate of the NMOS transistor NM14 as the output terminal of the hysteresis comparator, and the source of the NMOS transistor NM9, the source of the NMOS transistor NM10, the source of the NMOS transistor NM11, the source of the NMOS transistor NM12, the source of the NMOS transistor NM 8253 and.

10. The overvoltage protection circuit of claim 9, wherein: the source of the NMOS transistor NM9 grounded comprises: the source electrode of the NMOS transistor NM8 is connected with the drain electrode of the NMOS transistor NM9, the gate electrode of the NMOS transistor NM9 is connected with a bias voltage Vb2, and the source electrode of the NMOS transistor NM9 is grounded;

or: the source of the NMOS transistor NM10 grounded includes: the drain electrode of the PMOS tube PM10 is connected with the drain electrode of the NMOS tube NM10 and the grid electrode of the NMOS tube NM10, and the source electrode of the NMOS tube NM10 is grounded;

or: the source of the NMOS transistor NM13 grounded includes: the drain of the PMOS transistor PM11 is connected to the drain of the NMOS transistor NM13 and the gate of the NMOS transistor NM13, and the source of the NMOS transistor NM13 is grounded.

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