CN212276289U - High-performance CMOS voltage reference source with negative feedback - Google Patents
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Abstract
The utility model discloses a high performance CMOS voltage reference source with negative feedback relates to integrated circuit technical field. The high-performance CMOS voltage reference source with negative feedback comprises a starting circuit module, a current source module and an active load module, wherein the starting circuit module, the current source module and the active load module are sequentially connected; the starting circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can reach a stable state all the time; the current source module is used for generating a bias current which is in direct proportion to the electron mobility and the square of the temperature under the condition of not using special devices, and the bias current is smaller, so that the power consumed by the current is smaller; the active load module generates output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback, and has the advantages of low temperature coefficient, low voltage linearity, high power supply rejection ratio, low power consumption and better process compatibility.
Description
Technical Field
The utility model relates to an integrated circuit technical field specifically is a high performance CMOS voltage reference source with negative feedback.
Background
The voltage reference source is taken as an important component of a modern analog integrated circuit and is widely applied to the fields of the Internet of things, wearable equipment, power management and the like. As the most commonly used modules in the power management module, the low dropout regulator and the dc regulator all need to use a voltage reference source to generate a reference voltage independent of process, power voltage and temperature variation, and the accuracy of the voltage reference source outputting the reference voltage will directly affect the performance of these modules.
Several indexes commonly used for measuring the voltage reference source include temperature coefficient, voltage linearity, power supply rejection ratio, power consumption, temperature coefficient and the like. The temperature coefficient and the voltage linearity are respectively used for measuring the influence of the temperature and voltage reference source change on the reference voltage; the power supply rejection ratio is used for measuring the capacity of a circuit for suppressing power supply noise; power consumption is a performance parameter that measures the power loss of a circuit; the coefficient of variation is used to measure how well the process affects the performance of the circuit.
In order to obtain an output reference voltage independent of temperature during the design process of the voltage reference source, it is usually necessary to obtain the output reference voltage with temperature compensation by weighted addition of positive and negative temperature coefficients. The traditional voltage reference source mainly utilizes a negative temperature coefficient of a base electrode-emitter voltage of a Bipolar Junction Transistor (BJT) tube and a positive temperature coefficient of a thermoelectric force to realize a zero temperature coefficient through linear addition, and a reference voltage of about 1.2V is obtained. This makes it difficult to achieve low power consumption, as the supply voltage will be higher than 1.2V. In addition, since the conventional voltage reference source uses a resistor of a resistor and a bipolar transistor, the chip area is greatly increased. Therefore, CMOS voltage reference sources have been widely developed by virtue of their low power consumption and low process sensitivity. The CMOS voltage reference source based on the resistor obtains a zero temperature coefficient by linear weighted addition by utilizing a positive temperature coefficient of MOS tube grid source voltage difference and a negative temperature coefficient of threshold voltage. The circuit utilizes the sub-threshold characteristic of the MOS tube to reduce the power consumption of the circuit, but the area of the chip is still large due to the resistor used by the circuit. To further reduce chip area, high threshold voltage based CMOS voltage reference sources have been proposed. The voltage reference source is obtained by linear weighted addition of a negative temperature coefficient of the threshold voltage difference of a high-threshold MOS tube and a standard MOS tube and a positive temperature coefficient of thermoelectric force. The chip area is small because no resistor is used, but the process compatibility of the circuit is poor and the cost is high because a high-threshold MOS tube is used. For better temperature stability and process compatibility, only a CMOS voltage reference source of a standard threshold voltage MOS transistor is proposed. The circuit obtains better process compatibility due to the fact that only standard MOS tubes are used, but the voltage linearity of the circuit is still poor.
Based on the above analysis, it is difficult to cover all the key characteristics of the voltage reference source during the design and research process of the voltage reference source.
SUMMERY OF THE UTILITY MODEL
The utility model provides a high performance CMOS voltage reference source with negative feedback overcomes the defect that above-mentioned voltage reference source can not cover all key performances, possesses low temperature coefficient, low-voltage linearity, high power suppression ratio simultaneously, low-power consumption and the compatible advantage of better technology.
In order to achieve the above purpose, the utility model discloses a following technical scheme realizes: the high-performance CMOS voltage reference source with negative feedback comprises a starting circuit module, a current source module and an active load module, wherein the starting circuit module, the current source module and the active load module are sequentially connected.
The starting circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can reach a stable state all the time.
The current source module is used for generating a bias current which is in direct proportion to the electron mobility and the square of the temperature under the condition of not using special devices, and the bias current is smaller, so that the power consumed by the current is smaller.
The active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback.
As the utility model discloses a high performance CMOS voltage reference source with negative feedback is preferred, the starting circuit module includes PMOS pipe M14, NMOS pipe M15, M16 and M17, M14's in the starting circuit drain electrode and source electrode all link to each other with mains voltage, M14's grid links to each other with M15 and M16's grid, M15 and M16's drain electrode link to each other, and draw forth as the first output of starting circuit and provide the enabling signal for current source module, M15 and M16's source electrode and the second and third output that draw forth as the enabling signal respectively link to each other with current source module, M17's drain electrode and M14's grid link to each other, M17's grid links to each other with output reference voltage VREF, M17's source ground connection.
As a preferred embodiment of the present invention, the high performance CMOS voltage reference source with negative feedback comprises an operational amplifier, PMOS transistors M9, NMOS transistors M9, M9 and M9, wherein the M9, M9 and M9 form a current mirror, i.e. the drain and gate of M9 are connected, M9, the source of M9 is connected to a power supply voltage, M9, the gate of M9 is connected to an operational amplifier OP-AMP, and is connected to a first output terminal of the start-up circuit and led out to the active load module, the M9, M9 and M9 are all diode connected, i.e. the gates and drains of M9, M9 and M9 are connected together, the drain of M9 is connected to the drain of M9, the gate of M9 is connected to the drain of M9, the source of M9 is connected to the drain of M9, the gate of M9 is connected to the operational amplifier OP-AMP, the drain of M9 is connected to the drain of the operational amplifier, the M9 is connected to the drain of the operational amplifier OP-AMP, the drain of M3 is connected to the second output terminal of the start-up circuit, the gate of M4 is connected to the inverting input terminal of the operational amplifier OP-AMP and to the third output terminal of the start-up circuit, the drain of M4 is connected to the drain of M11, and the source of M4 is connected to ground.
As a preferred embodiment of the present invention, in the current source module, M2, M4, M9, M10 and M11 operate in the subthreshold region, and M1 and M3 operate in the saturation region.
As a preferred embodiment of the present invention, the high performance CMOS voltage reference source with negative feedback includes PMOS transistors M12, M13, NMOS transistors M5, M6, M7 and M8, M12 and M12 are connected to the gates of M12, M12 and M12 in the current source module as the output terminals of the active load module, so as to form a current mirror, the sources of M12 and M12 are connected to the power voltage, the drain of M12 is connected to the drain of M12, the gate of M12 is connected to the gate of M12, the source of M12 is connected to the drain of M12, the source of M12 is grounded, M12 and M12 are both diode-connected, that the respective drains of M12 and M12 are connected to the gate, the source of M12 is connected to the drain of M12, and the output terminal of the active load module is also connected to VREF, the gate of the whole gate of M12 is connected to the reference voltage source of M12, and the gate of M12 is connected to the output terminal of the active load module.
As the utility model discloses a high performance CMOS voltage reference source with negative feedback is preferred, PMOS pipe M12, M13, NMOS pipe M5, M6, M7 and M8 all work in subthreshold region in the active load module.
As the utility model discloses a high performance CMOS voltage reference source is preferred with negative feedback, mains voltage's scope is 0.95V-3V.
The utility model provides a high performance CMOS voltage reference source with negative feedback. The method has the following beneficial effects:
the high-performance CMOS voltage reference source with the negative feedback provides a high-performance CMOS voltage reference source with the negative feedback, and comprises a starting circuit module, a current source module and an active load module which are connected in sequence; the starting circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can always reach a stable state, and the current source module is used for generating a bias current which is in direct proportion to the electron mobility and the square of the temperature under the condition of not using special devices, and the bias current is small, so that the power consumed by the current is small. The active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback. Meanwhile, the method has the advantages of low temperature coefficient, low voltage linearity, high power supply rejection ratio, low power consumption and better process compatibility.
Drawings
FIG. 1 is a circuit diagram of a high performance CMOS voltage reference source circuit with negative feedback according to the present invention;
fig. 2 is a small signal diagram of the high performance CMOS voltage reference active load module with negative feedback of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.
Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention.
Referring to fig. 1-2, the present invention provides a technical solution: a high-performance CMOS voltage reference source with negative feedback sequentially comprises a starting circuit module, a current source module and an active load module.
The starting circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can reach a stable state all the time.
The current source module is used for generating a bias current which is proportional to the electron mobility and the square of the temperature under the condition of not using special devices, and the bias current is smaller, so that the power consumed by the current is smaller.
The active load module generates output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback while realizing zero temperature coefficient.
The threshold voltage of the MOS tube is in a negative correlation with the temperature, namely the threshold voltage has a negative temperature coefficient, and the expression thereof is as follows:
VTH＝VTH0-αT(T-T0)#(1)
wherein, VTH0Represents the threshold voltage, alpha, of the MOS transistor at room temperatureTTemperature coefficient representing threshold voltage, T represents temperature of circuit working environment0Indicating room temperature.
When the voltage between the source electrode of the MOS transistor and the substrate is not zero, a body effect is introduced, so that the threshold voltage of the MOS transistor changes, and the threshold voltage after the body effect is considered can be represented as follows:
where η is the sub-threshold slope factor, VSBIs the voltage between the source electrode and the substrate of the MOS transistor
When the NMOS tube works in a saturation region, the expressions of drain-source current and gate-source voltage are as follows:
when the NMOS tube works at a sub-threshold value, the expressions of drain-source current and gate-source voltage are as follows:
wherein, mu and COXRespectively electron mobility and oxide layer capacitance under the grid, K is the width-to-length ratio of MOS, VGSIs the voltage between the gate and the source, VTIs a thermoelectric potential, and VTWith a positive temperature coefficient with respect to temperature.
The utility model discloses in, the mains voltage scope that the circuit can normally work is 0.95V ~ 3V, and this high performance CMOS voltage reference source realizes low temperature coefficient and low-voltage linearity under the condition that does not use special threshold value MOS pipe and resistance for the process compatibility and the chip area of circuit have obtained fine improvement.
Further, the starting circuit module comprises a PMOS transistor M14 and NMOS transistors M15, M16 and M17; the drain and the source of the M14 in the starting circuit are both connected with a power supply voltage, the grid of the M14 is connected with the grids of the M15 and the M16, and the drains of the M15 and the M16 are connected, and are led out to serve as a first output end of the starting circuit to provide a starting signal for the current source module. The sources of M15 and M16 are connected with the second and third output terminals respectively led out as starting signals and the current source module. The drain of M17 is connected to the gate of M14, the gate of M17 is connected to the output reference voltage VREF, and the source of M17 is connected to ground.
Further, the current source module includes an operational amplifier, PMOS transistors M9, M10, and M11, and NMOS transistors M1, M2, M3, and M4. M9, M10 and M11 form a current mirror, namely the drain electrode of M9 is connected with the grid electrode, the source electrodes of M9, M10 and M11 are connected with a power supply voltage, and the grid electrodes of M9, M10 and M11 are connected with an operational amplifier OP-AMP, and are also connected with the first output end of the starting circuit and led out to the active load module. M1, M2 and M4 are all diode-connected, that is, the gates and drains of M1, M2 and M4 are connected together, the drain of M1 is connected with the drain of M9, the source of M1 is connected with the drain of M2, the gate of M2 is connected with the drain of M1, the source of M2 is grounded, the source of M3 is connected with the drain of M2, the gate of M3 is connected with the non-inverting input terminal of an operational amplifier OP-AMP, the drain of M3 is connected with the second output terminal of the start-up circuit, the gate of M4 is connected with the inverting input terminal of the operational amplifier OP-AMP and is connected with the third output terminal of the start-up circuit, the drain of M4 is connected with the drain of M11, and the source of M4 is grounded.
Further, in the active load module, the PMOS transistors M12 and M13 and the NMOS transistors M5, M6, M7 and M8 all operate in the sub-threshold region.
The starting circuit module is connected with the current source module, so that the CMOS power reference source can be quickly started, the consumed power consumption can be ignored after the whole CMOS power reference source is successfully started and enters a normal state, and other performances of the circuit cannot be influenced.
In the current source module, M2, M4, M9, M10 and M11 operate in a subthreshold region, M1 and M3 operate in a saturation region, and according to the connection relations of M1, M2, M3 and M4, the following results are obtained:
wherein,
and
the gate-source voltage after taking the bulk effect into account is shown. Substituting formulae (2), (4) and (6) into formula (7) can yield:
where α, β and γ are the proportions of the currents. Simplified by equation (8), the current generated by the current source can be expressed as follows:
further, the active load module comprises PMOS transistors M12 and M13 and NMOS transistors M5, M6, M7 and M8; m12 and M13 are connected as the output terminals of the active load module to the gates of M9, M10 and M11 in the current source module to form a current mirror, the sources of M12 and M13 are connected to the power supply voltage, the drain of M12 is connected to the drain of M5, the drain of M13 is connected to the drain of M7, the gate of M5 is connected to the gate of M7, the source of M5 is connected to the drain of M6, the source of M6 is grounded, M6 and M7 are both diode-connected, i.e. the drains of M6 and M7 are connected together, the source of M7 is connected to the drain of M8 and is used as the output terminal of the active load module, and also the output terminal VREF of the whole voltage reference source, the gate of M8 is connected to the gate of M6, and the source of M8 is grounded.
Further, in the active load module, M7, M5, M6 and M8 sequentially form a negative feedback loop, and the main pole of the circuit is pushed far to improve the low-frequency power supply rejection ratio of the circuit, and a conjugate complex pole is introduced to improve the high-frequency power supply rejection ratio of the circuit. The current generated by the current source is mirrored by the current mirror and injected into the active load module. The active load module is used to generate a reference voltage independent of supply voltage and temperature. According to M5, M6, M7 and M8, the expression of the available output reference voltage is as follows:
substituting equations (2), (4), and (6) into (7), the expression of the output reference voltage can be expressed as:
in order to obtain a temperature compensated reference voltage, the following conditions must be satisfied:
by adjusting the width-length ratio of the relevant MOS tube in the expression, the output reference voltage with zero temperature coefficient can be obtained.
Further, in the active load module, M7, M5, M6 and M8 form a negative feedback loop in sequence. Assuming that the voltage at node Z increases with the change in the power supply voltage, the voltage at node Y rises and then the output reference voltage VREF will decrease. Because the gain of the negative feedback loop consisting of M7, M5, M6, and M8 is greater than the gain of the positive feedback loop consisting of M7, the output reference voltage VREF eventually decreases, and vice versa. The existence of the negative feedback loop further improves the precision of the reference voltage, so that the voltage reference source realizes lower voltage linearity. As shown in fig. 2, a small signal diagram of a high performance CMOS voltage reference source active load module with negative feedback. From the small signal analysis, the PSRR expression is calculated as follows:
wherein the expression is as follows:
wherein, gmiAnd roiRespectively representing MOS transistors MiTransconductance and output resistance of (a); goiIs roiA derivative of (a); a. thedcIs the dc gain of the operational amplifier. The active load with negative feedback provided by the present invention actually improves the PSRR of the circuit, and the main reasons thereof are as follows. First, the dominant pole z0The low frequency PSRR of the circuit is improved by the zooming-out. Second, a complex conjugate pole p is introducedcpAnd complex conjugate pole pcpDesigned as the complex conjugate zero point zczMuch smaller to improve the circuit high frequency PSRR.
The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.
Claims (7)
1. The utility model provides a high performance CMOS voltage reference source with negative feedback, includes starting circuit module, current source module, active load module and mains voltage, its characterized in that: the starting circuit module, the current source module and the active load module are connected in sequence;
the starting circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can reach a stable state all the time;
the current source module is used for generating a bias current which is in direct proportion to the electron mobility and the square of the temperature under the condition of not using a device, and the bias current is small, so that the power consumed by the current is small;
the active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback.
2. A high performance CMOS voltage reference source with negative feedback as claimed in claim 1 wherein: the starting circuit module comprises a PMOS tube M14, NMOS tubes M15, M16 and M17, the drain and the source of M14 in the starting circuit are connected with power supply voltage, the grid of M14 is connected with the grids of M15 and M16, the drains of M15 and M16 are connected, a first output end which is led out to serve as the starting circuit provides a starting signal for the current source module, the sources of M15 and M16 are connected with a second output end and a third output end which are respectively led out to serve as the starting signal and the current source module, the drain of M17 is connected with the grid of M14, the grid of M17 is connected with output reference voltage VREF, and the source of M17 is grounded.
3. A high performance CMOS voltage reference source with negative feedback as claimed in claim 2, wherein: the current source module comprises an operational amplifier, PMOS tubes M, M, M, NMOS tubes M, M, M and M, wherein the M, M and M form a current mirror, namely the drain electrode of the M is connected with the grid electrode, the source electrodes of the M, M and M are connected with a power supply voltage, the grid electrodes of the M, M and M are connected with an operational amplifier OP-AMP and are simultaneously connected with the first output end of the starting circuit and led out to the active load module, the M, M and M are in diode connection, namely the grid electrodes and the drain electrodes of the M, M and M are respectively connected together, the drain electrode of the M is connected with the drain electrode of the M, the source electrode of the M is grounded, the source electrode of the M is connected with the drain electrode of the M, the grid electrode of the M is connected with the positive input end of the operational amplifier-OP, the drain electrode of the M is connected with the second output end, the gate of M4 is connected to the inverting input of the operational amplifier OP-AMP and to the third output of the start-up circuit, the drain of M4 is connected to the drain of M11, and the source of M4 is connected to ground.
4. A high performance CMOS voltage reference source with negative feedback as claimed in claim 3 wherein: m2, M4, M9, M10 and M11 in the current source module work in a subthreshold region, and M1 and M3 work in a saturation region.
5. The high performance CMOS voltage reference source with negative feedback of claim 4, wherein: the active load module comprises PMOS tubes M12, M13, NMOS tubes M5, M6, M7 and M8, wherein the M12 and the M12 are used as output ends of the active load module and are connected with gates of M12, M12 and M12 in the current source module to form a current mirror, sources of the M12 and the M12 are connected with a power supply voltage, a drain of the M12 is connected with a drain of the M12, a gate of the M12 is connected with a gate of the M12, a source of the M12 is connected with a drain of the M12, and is used as an output end of the active load module, and is also used as an output end of the whole voltage reference source VREF, a gate of the M12 is connected with a gate of the M12, and a source of the M12 is connected with a source of the M12.
6. The high performance CMOS voltage reference source with negative feedback of claim 5, wherein: the PMOS tubes M12, M13, the NMOS tubes M5, M6, M7 and M8 in the active load module work in a subthreshold region.
7. A high performance CMOS voltage reference source with negative feedback according to any of claims 1-6, wherein: the range of the power supply voltage is 0.95V-3V.
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| CN115357085A (en) * | 2022-08-30 | 2022-11-18 | 广东工业大学 | Self-biased CMOS voltage reference source and method for determining linear sensitivity and power supply rejection ratio |
| CN115357085B (en) * | 2022-08-30 | 2023-08-08 | 广东工业大学 | Self-bias CMOS voltage reference source and method for determining linear sensitivity and power supply rejection ratio |
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