CN2122407U

CN2122407U - Digital inspection monitor

Info

Publication number: CN2122407U
Application number: CN 92213143
Authority: CN
Inventors: 吴金泉
Original assignee: Individual
Current assignee: Individual
Priority date: 1992-01-24
Filing date: 1992-01-24
Publication date: 1992-11-18

Abstract

The utility model relates to a digital inspection monitor. The utility model is characterized in that the utility model is composed of a reference generator (1), a frequency divider (2), a first period signal sampling circuit (3), a self locking switch (4) used for accepting the input signal of a mutually button (10), a counter (5) carrying out counting for the effective output signals of the self locking switch (4), a decoder driver (6), and a display (7). The output signal of the first period signal sampling circuit (3) is connected to the gate control end of the self locking switch (4). The utility model can open the counter in the set time periodically, and supplies the operators on duty to press the counting button; when the set time is exceeded, the counter is locked and receives signals of the button no longer.

Description

Digital inspection monitor

The utility model relates to a kind of counter that is used to write down the tours of inspection number of times.

In electric power, chemical process, often need the ruuning situation of operations staff's quantitative check plant equipment, the various data of time recording equipment.Also there is not at present special-purpose device can write down operations staff's quality on duty effectively.

The purpose of this utility model is to provide a kind of digital type scanning check monitor, can regularly open a period of time periodically and trigger for the operations staff, thereby can write down the operations staff in official hour whether at the scene, can also prevent cheating simultaneously effectively.

The purpose of this utility model can realize by following technical proposal:

The utility model comprises the reference generator that is used to produce the benchmark oscillator signal; Be used for the oscillator signal of described reference generator output is carried out different fractions frequency divider frequently; Be used for the square-wave signal of frequency divider output is taken a sample and the period 1 signal sampling circuit of cycle output useful signal; Be used to accept first pulse signal of hand push button input, all signals that elimination is imported subsequently, the self-lock switch of a useful signal of output, the output signal of described period 1 signal sampling circuit is connected to the gating control end of self-lock switch; Be used for counter that the useful signal of self-lock switch output is counted; Be used for decoder driver that the digital signal of counter output is deciphered, driven; Be used to show the display of the demonstration sign indicating number of decoder driver output.Described reference generator can produce the square wave of fixed cycle, carry out frequency division not at the same level as required by frequency divider, the period 1 signal sampling circuit is from the frequency divider square-wave signal of taking a sample, export one tunnel periodic signal of square wave, the cycle that the cycle of square-wave signal should regularly patrol and examine for the operations staff, the effective value time of each cycle square wave (time of high level or low level time) can be triggered the utility model to record the permission time of play number for the operations staff, in this time, counter is opened, can count pulse from hand push button, self-lock switch only can guarantee in the above-mentioned permission time by once from the pulse of hand push button, block all pulses subsequently, make counter once add " 1 " counting at the most in the time that allows, the data in the counter send display to show behind decoder driver.The utility model also comprises and is used for the square-wave signal of frequency divider output is taken a sample and signal sampling circuit second round of cycle output useful signal, and described second round, the output signal of signal sampling circuit was connected to the reseting controling end of counter.Described second round, signal sampling circuit was in order to reset to counter cycle, made counter O reset in for example per 24 hours or per 8 hours, also can be without signal sampling circuit second round, and self-zeroing when the counter data full scale.The utility model also comprises and is used for the square-wave signal of frequency divider output is taken a sample and the period 3 signal sampling circuit of cycle output useful signal; The input signal of described period 3 signal sampling circuit is by gauge tap ［ 12 ］ control, and its output signal is connected to the gating control end of self-lock switch.Described period 3 signal sampling circuit is opened at the time inside counting device of quick gating in order to the quick gating of counter, can write down the pulse from hand push button, with the shown data of levelling counter.The utility model also comprises the reset button that can export the effective impulse signal, and the effective impulse signal of being exported is connected on the reseting controling end of frequency divider.This reset button is in order to determine counting zero-time of the present utility model.Gauge tap ［ 12 ］ and reset button all are sealed in inside of the present utility model, to prevent cheating.

The utlity model has following advantage:

Since adopted self-lock switch, can only be by first pulse, so can prevent cheating effectively from hand push button.

The period 3 signal sampling circuit can be adjusted the usefulness that shows number when needed by pressing gauge tap 12 quick gated counters for managerial personnel.Reset button can arbitrarily be set the zero-time of counter for managerial personnel in addition.Gauge tap 12 and reset button all are sealed in inside of the present utility model, can prevent cheating.

The utility model will be further described below in conjunction with drawings and Examples:

Accompanying drawing 1 is a circuit block diagram of the present utility model;

Accompanying drawing 2 is the circuit theory diagrams of an embodiment of the present utility model;

With reference to accompanying drawing, the model of integrated package in the accompanying drawing 2 ［ 13 ］ is ZC702, is a second reference generator; The model of integrated package ［ 14 ］ is CC4518B, is two decade counters; The model of integrated package ［ 15 ］ is CC4518B, is two decade counters; Integrated package ［ 14 ］, integrated package ［ 15 ］ use as frequency divider at this.The model of integrated package ［ 16 ］ is CC4013, is double D trigger; The model of integrated package ［ 17 ］ is CC4518B, is two decade counters; The model of integrated package ［ 21 ］ and integrated package ［ 20 ］ is CC4543, is the liquid crystal decoder driver; Integrated package ［ 18 ］ and integrated package ［ 19 ］ are LCD.The square wave of the 12nd pin output 256HZ of integrated package ［ 13 ］, the 1st pin by integrated package ［ 16 ］ behind first trigger frequency division of this signal in integrated package ［ 16 ］ obtains the 128HZ square-wave signal, and this signal is as the AC driving signal of integrated package ［ 18 ］ and integrated package ［ 19 ］.The 5th pin output 1HZ square-wave signal of integrated package ［ 13 ］, this signal is input to the 10th pin of integrated package ［ 14 ］ as second reference signal of the present utility model, the 11st pin output cycle of integrated package ［ 14 ］ is 2 seconds a square-wave signal, this signal through rejection gate ［ 39 ］ and or door ［ 41 ］ deliver to the 7th pin of integrated package ［ 21 ］ and integrated package ［ 20 ］ respectively, as the gating flashing signal (being that display glimmered with 2 seconds cycle) of LCD.The 14th pin output cycle of integrated package ［ 14 ］ is 10 seconds, 8 seconds effective square-wave signals in phase weekly, this signal send counting input end the 2nd pin of second counter of integrated package ［ 14 ］, with door ［ 22 ］ the output cycle be 60 seconds square-wave signal, warp or door ［ 23 ］ send the reset terminal of second counter of integrated package ［ 14 ］, so every mistake of second counter 60 seconds of integrated package ［ 14 ］ clearly once zero, the 5th pin output cycle of integrated package ［ 14 ］ is the square-wave signal of 1 minute (60 seconds), this signal is input to the 10th pin of integrated package ［ 15 ］, and the 14th pin output cycle of integrated package ［ 15 ］ is 10 minutes, 8 fens effective square-wave signals in phase weekly.Identical with the principle of integrated package ［ 14 ］, the 4th pin of integrated package ［ 15 ］ and the 5th pin connect the input end with door ［ 25 ］, so and door ［ 25 ］ output cycle is one hour a square-wave signal, this square-wave signal through or door ［ 24 ］ deliver to the reset terminal of second counter of integrated package ［ 15 ］, per 1 hour of second counter of integrated package ［ 15 ］ clearly once zero.By or door ［ 36 ］, rejection gate ［ 37 ］, rejection gate ［ 38 ］ form the period 1 signal sampling circuit, was the cycle by rejection gate ［ 38 ］ output with 1 hour, and 0～10 fen effective square-wave signal in the phase is as the gating control signal of electronics self-lock switch ［ 16 ］ weekly.The input signal of rejection gate ［ 37 ］ has five the tunnel, and wherein when arbitrary road was high level, rejection gate ［ 37 ］ was output as low level, and it is oppositely with door ［ 29 ］ output signal that the signal of rejection gate ［ 38 ］ output equals.Under the normal condition, gating button ［ 26 ］ and reset button ［ 30 ］ are therefore closed with door ［ 29 ］ all by 0 level fast, and it is output as 0.8 seconds useful signals of the 14th pin output of integrated package ［ 14 ］ can not be by arriving rejection gate ［ 38 ］ with door ［ 29 ］.For or the door ［ 36 ］, the 3rd pin of integrated package ［ 15 ］ is depended in its output, therefore in normal operation, have only and work as the 3rd in the integrated package ［ 15 ］, 4,5 pins are at 0 o'clock, rejection gate ［ 38 ］ just equals level "0", this level gating is as the integrated package ［ 16 ］ of self-lock switch, this state was since 0 minute, broken from the 2nd pin input of integrated package ［ 15 ］ up to first 10 sub-signal, therefore self-lock switch ［ 16 ］ stays open 10 fens kinds, and in after this 50 minutes, the 3rd of integrated package ［ 15 ］, 4,5 pins always have one to be not equal to level "0", so self-lock switch ［ 16 ］ locking kept 50 minutes.Because of automatically return-to-zero of integrated package ［ 15 ］, cycle count again so self-lock switch ［ 16 ］ is opened again, and kept 10 minutes, and so forth endlessly after 60 minutes.By reverser ［ 28 ］, form the period 3 signal sampling circuit with door ［ 29 ］, rejection gate ［ 38 ］, by the effective square-wave signal of 10 second cycle, 8 seconds of the 14th pin of integrated package ［ 14 ］ output through reverser ［ 28 ］ to door ［ 29 ］ again to rejection gate ［ 38 ］, was the cycle by rejection gate ［ 38 ］ output with 10 seconds, 8 seconds effective square-wave signals in phase weekly, gating switch ［ 26 ］ is as the gauge tap of this signal fast, and this signal is as the quick gating signal of self-lock switch integrated package ［ 16 ］.Under quick strobe state, self-lock switch ［ 16 ］ was opened once in per 10 seconds, continued to open 8 seconds at every turn, and strobe state can be set the interior data of counter for the commissioning staff fast.One of them trigger of integrated package ［ 16 ］ is as frequency division usefulness, and the 256HZ square-wave signal frequency division that integrated package ［ 13 ］ the 12nd pin is imported becomes 128HZ.Another trigger of integrated package ［ 16 ］ is as self-lock switch, when by gating, self-lock switch is used to first pulse signal of selecting hand push button ［ 34 ］ to send, elimination all pulses except that first pulse, and, use for counter ic ［ 17 ］ counting from the 13rd pin of integrated package ［ 16 ］ output count pulse; When self-lock switch ［ 16 ］ locking, self-lock switch ［ 16 ］ does not receive any extraneous signal.Integrated package ［ 17 ］ is 24 system counters, step-by-step counting to the input of integrated package ［ 17 ］ the 1st pin, 3rd, the binary code of 4,5,6 a pins output position, 11st, 12,13,14 pins are exported ten binary code, this counter is self-zeroing behind meter full 24, so do not need signal sampling circuit second round, for the count cycle of different needs, can design signal sampling circuit second round, regularly counter is carried out zero clearing, also can set the range of counter, behind the counting full scale, it be resetted.The data of counter ［ 17 ］ are driven by integrated package ［ 21 ］ and integrated package ［ 20 ］ decoding, are displayed it by display ［ 18 ］ and display ［ 19 ］.［ 26 ］ be quick gating button, the resistance of resistance ［ 27 ］ is 10K.［ 30 ］ be reset button, the resistance of resistance ［ 31 ］ is 10K, reset signal is divided into five the tunnel, wherein four the tunnel send ［ 14 ］, the reset terminal of ［ 15 ］ of making frequency divider, another road is sent or door ［ 36 ］, make or door ［ 36 ］ moment output equals high level, cause rejection gate ［ 37 ］ to be output as low level, owing to also equal low level with door ［ 29 ］ output, thereby rejection gate ［ 38 ］ output equals high level, the 10th pin moment that is integrated package ［ 16 ］ equals 1, and integrated package ［ 16 ］ is resetted, and the 13rd pin of ［ 16 ］ recovers 0.Rejection gate ［ 39 ］ is because the 13rd, the 10th pin of ［ 16 ］ is 0, so the output of integrated package ［ 14 ］ the 11st pin 2 seconds being that the square-wave signal in cycle can pass through rejection gate ［ 39 ］, the demonstration control end (the 7th pins of ［ 20 ］ and ［ 21 ］) that arrives code translator makes display reliably glisten after zero clearing, represents gating.［ 34 ］ be hand push button, the resistance of resistance ［ 32 ］ is 10K, and the resistance of resistance ［ 33 ］ is 500 ohm, and not gate ［ 35 ］ is to the signal inversion of hand push button, so that ［ 16 ］ receive.Be used to make integrated package ［ 17 ］ counting to reach 24 back self-zeroings with door ［ 23 ］.Can identify 0 numeral of the tens of integrated package ［ 17 ］ with rejection gate ［ 40 ］, at 0～24(decimal system) scope in, have only when two input ends of rejection gate ［ 40 ］ are equal to 0, the output of rejection gate ［ 40 ］ just equals 1, otherwise export 0, the demonstration control end of the output may command integrated package ［ 20 ］ of rejection gate ［ 40 ］ is when the tens of integrated package ［ 17 ］ equals 0, the tens of display does not show that promptly ［ 18 ］ do not show.

Claims

1, a kind of digital type scanning check monitor is characterized in that: it comprises the reference generator [1] that is used to produce the benchmark oscillator signal; Be used for the oscillator signal of described reference generator [1] output is carried out different fractions frequency divider [2] frequently; Be used for the square-wave signal of frequency divider [2] output is taken a sample and the period 1 signal sampling circuit [3] of cycle output useful signal; Be used to accept first pulse signal of hand push button [10] input, all signals that elimination is imported subsequently, the self-lock switch [4] of a useful signal of output, the output signal of described period 1 signal sampling circuit [3] is connected to the gating control end of self-lock switch [4]; Be used for counter [5] that the useful signal of self-lock switch [4] output is counted; Be used for decoder driver [6] that the digital signal of counter [5] output is deciphered, driven; Be used to show the display [7] of the demonstration sign indicating number of decoder driver [6] output.

2, digital type scanning check monitor according to claim 1, it is characterized in that: it comprises also and is used for the square-wave signal of frequency divider ［ 2 ］ output is taken a sample and signal sampling circuit second round ［ 11 ］ of cycle output useful signal that the output signal of described signal sampling circuit second round ［ 11 ］ is connected to the reseting controling end of counter ［ 5 ］.

3, digital type scanning check monitor according to claim 1 is characterized in that: it also comprises and is used for the square-wave signal of frequency divider ［ 2 ］ output is taken a sample and the period 3 signal sampling circuit ［ 9 ］ of cycle output useful signal; The input signal of described period 3 signal sampling circuit ［ 9 ］ is by gauge tap ［ 12 ］ control, and its output signal is connected to the gating control end of self-lock switch ［ 4 ］.

4, digital type scanning check monitor according to claim 1 is characterized in that: it also comprises the reset button ［ 8 ］ that can export the effective impulse signal, and the effective impulse signal of being exported is connected on the reseting controling end of frequency divider ［ 2 ］.