CN212210852U - Synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit - Google Patents
Synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit Download PDFInfo
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- CN212210852U CN212210852U CN202021300292.8U CN202021300292U CN212210852U CN 212210852 U CN212210852 U CN 212210852U CN 202021300292 U CN202021300292 U CN 202021300292U CN 212210852 U CN212210852 U CN 212210852U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model discloses a synchronous rectification BUCK circuit afterflow MOS pipe parallel connection self-adaptation adjusting circuit, including control chip U1, current sampling resistor R1, current sampling resistor R1 is connected with diode D2's negative pole, is connected with divider resistor R3 and R4 between transportation amplifier's Vcc + pin and the Vcc-pin, and transportation amplifier's positive input end is connected divider resistor R3 and R4; an OUT pin of the transport amplifier is connected with a collector of a PNP triode Q5, an emitter of the PNP triode Q5 is connected with an output end of a control chip U1, a base of the PNP triode Q5 is connected with a G pole of an MOS tube Q4, and the MOS tube Q4 is connected with an MOS tube Q3 in parallel; a diode D1 is connected between the emitter and the base of the PNP triode Q3, and the G pole of the MOS transistor Q3 is connected with the anode of the diode D1; the synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit can realize higher conversion power by connecting two or more MOS tubes in parallel, can also obviously reduce the no-load standby power consumption of a power supply, and is favorable for saving energy consumption and improving the reliability of the power supply.
Description
Technical Field
The utility model relates to an electronic instrument technical field specifically is synchronous rectification BUCK circuit afterflow MOS manages parallelly connected self-adaptation adjusting circuit.
Background
Among the topologies of the switching power supply, the BUCK circuit is one of the most commonly used topologies. When the output power is higher, two or more BUCK switch MOS tubes and follow current MOS tubes are required to be connected in parallel to meet the current requirement of high-power output. When the switching power supply is fully loaded and output, the use of the multiple MOS tubes is beneficial to improving the conversion efficiency, but when the switching power supply works in light load and no load, the output current is very small, the switching loss of the MOS tubes can be additionally increased by the parallel connection of two or more MOS tubes, and the no-load standby power consumption of the switching power supply is increased. In order to reduce the standby power consumption of the switching power supply, a synchronous rectification BUCK circuit freewheeling MOS (metal oxide semiconductor) tube is connected with a self-adaptive adjusting circuit in parallel to reduce the switching loss of the switching tube.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a synchronous rectification BUCK circuit afterflow MOS manages parallelly connected self-adaptation adjusting circuit, solves the problem that proposes in the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme:
the synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit comprises a control chip U1, wherein the input end of the control chip U1 is connected with two MOS tubes Q1 and Q2 which are mutually connected in parallel; the MOS tube Q1 and the MOS tube Q2 are connected with the input end of the circuit; a current sampling resistor R1 is connected between the circuit input end and the circuit output end, a current sampling resistor R1 is connected with the negative electrode of a diode D2, and the positive electrode of a diode D2 is connected with the negative input end of an operational amplifier U2 and a capacitor C7; voltage dividing resistors R3 and R4 are connected between a Vcc + pin and a Vcc-pin of the transport amplifier, and the positive input end of the transport amplifier is connected with the voltage dividing resistors R3 and R4; an OUT pin of the transport amplifier is connected with a collector of a PNP triode Q5, an emitter of the PNP triode Q5 is connected with an output end of a control chip U1, a base of the PNP triode Q5 is connected with a G pole of an MOS tube Q4, and an MOS tube Q3 is connected with an MOS tube Q4 in parallel; a diode D1 is connected between the emitter and the base of the PNP triode Q3, and the G pole of the MOS transistor Q3 is connected with the anode of the diode D1.
Preferably, the circuit further comprises input filter capacitors C1 and C2 connected between the input terminal of the circuit and the output terminal of the circuit; and output filter capacitors C3, C4, C5, and C6.
Preferably, the current sampling resistor R1 is connected between the output filter circuits C4 and C5.
Preferably, a current limiting resistor R2 is further connected between the collector of the PNP transistor Q5 and the OUT pin of the transport amplifier.
Preferably, the control chip U1 is a PWM control chip.
When the BUCK power supply load is in a full-load state, the output peak current is the highest, the sampling voltage on the current sampling resistor R1 is the highest, the sampling signal is sampled and held by the diode D2 and the capacitor C7 and then is compared with the preset voltage division level of the VCC by the R3 and the R4, the sampling holding level is higher than the voltage division level when the BUCK power supply load is in the full load state, the operational amplifier U2 outputs a low level and pulls down the base level of the Q5, when the PWM control chip U1 outputs a high level, the emitter of the PNP triode Q5 is correspondingly high level, the Q5 can be conducted, the MOS tube Q4 can be normally driven by the U1 to be turned on, parallel logic is formed by the U1 and the MOS tube Q3, and.
When the load of the switching power supply is no-load or light load, the input peak current is small, the sampling voltage on the current sampling resistor R1 is low, the sampling signal is lower than the voltage division level of R3 and R4 after being sampled and held by D2 and C7, the operational amplifier U2 outputs high level, when the PWM control chip U1 outputs high level, the emitter and the base of Q5 are both high level, potential difference cannot be formed, the MOS transistor Q4 cannot be conducted, the Q4 cannot perform follow current switching operation, only the MOS transistor Q3 performs follow current switching operation, the switching loss of the MOS transistor Q4 is reduced, and finally the standby power consumption of the switching power supply is reduced.
Compared with the prior art, the beneficial effects of the utility model are that: the synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit can realize higher conversion power by connecting two or more MOS tubes in parallel, can also obviously reduce the no-load standby power consumption of a power supply, and is favorable for saving energy consumption and improving the reliability of the power supply.
Drawings
Fig. 1 is the circuit diagram of the parallel self-adaptive adjusting circuit of the follow current MOS transistor of the synchronous rectification BUCK circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, the synchronous rectification BUCK circuit freewheeling MOS transistor parallel adaptive adjustment circuit includes a control chip U1, an input end of the control chip U1 is connected to two MOS transistors Q1 and Q2 that are connected in parallel; the MOS tube Q1 and the MOS tube Q2 are connected with the input end of the circuit; a current sampling resistor R1 is connected between the circuit input end and the circuit output end, a current sampling resistor R1 is connected with the negative electrode of a diode D2, and the positive electrode of a diode D2 is connected with the negative input end of an operational amplifier U2 and a capacitor C7; voltage dividing resistors R3 and R4 are connected between a Vcc + pin and a Vcc-pin of the transport amplifier, and the positive input end of the transport amplifier is connected with the voltage dividing resistors R3 and R4; an OUT pin of the transport amplifier is connected with a collector of a PNP triode Q5, an emitter of the PNP triode Q5 is connected with an output end of a control chip U1, a base of the PNP triode Q5 is connected with a G pole of an MOS tube Q4, and an MOS tube Q3 is connected with an MOS tube Q4 in parallel; a diode D1 is connected between an emitter and a base of the PNP triode Q3, a G pole of the MOS transistor Q3 is connected with an anode of the diode D1, and the PNP triode Q3 further comprises input filter capacitors C1 and C2 which are connected between an input end of the circuit and an output end of the circuit; and output filter capacitors C3, C4, C5 and C6, a current sampling resistor R1 is connected between the output filter capacitors C4 and C5, a current limiting resistor R2 is connected between the collector of the PNP triode Q5 and the OUT pin of the transport amplifier, and a control chip U1 is a PWM control chip.
The working principle is as follows: when the BUCK power supply load is in a full-load state, the output peak current is the highest, the sampling voltage on the current sampling resistor R1 is the highest, the sampling signal is sampled and held by the diode D2 and the capacitor C7 and then is compared with the preset voltage division level of the VCC by the R3 and the R4, the sampling holding level is higher than the voltage division level when the BUCK power supply load is in the full load state, the operational amplifier U2 outputs a low level and pulls down the base level of the Q5, when the PWM control chip U1 outputs a high level, the emitter of the PNP triode Q5 is correspondingly high level, the Q5 can be conducted, the MOS tube Q4 can be normally driven by the U1 to be turned on, parallel logic is formed by the U1 and the MOS tube Q3, and.
When the load of the switching power supply is no-load or light load, the input peak current is small, the sampling voltage on the current sampling resistor R1 is low, the sampling signal is lower than the voltage division level of R3 and R4 after being sampled and held by D2 and C7, the operational amplifier U2 outputs high level, when the PWM control chip U1 outputs high level, the emitter and the base of Q5 are both high level, potential difference cannot be formed, the MOS transistor Q4 cannot be conducted, the Q4 cannot perform follow current switching operation, only the MOS transistor Q3 performs follow current switching operation, the switching loss of the MOS transistor Q4 is reduced, and finally the standby power consumption of the switching power supply is reduced.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. Synchronous rectification BUCK circuit afterflow MOS pipe connects in parallel self-adaptation adjustment circuit, its characterized in that: the circuit comprises a control chip U1, wherein the input end of the control chip U1 is connected with two MOS tubes Q1 and Q2 which are mutually connected in parallel; the MOS tube Q1 and the MOS tube Q2 are connected with the input end of the circuit; a current sampling resistor R1 is connected between the circuit input end and the circuit output end, a current sampling resistor R1 is connected with the negative electrode of a diode D2, and the positive electrode of a diode D2 is connected with the negative input end of an operational amplifier U2 and a capacitor C7; voltage dividing resistors R3 and R4 are connected between a Vcc + pin and a Vcc-pin of the transport amplifier, and the positive input end of the transport amplifier is connected with the voltage dividing resistors R3 and R4; an OUT pin of the transport amplifier is connected with a collector of a PNP triode Q5, an emitter of the PNP triode Q5 is connected with an output end of a control chip U1, a base of the PNP triode Q5 is connected with a G pole of an MOS tube Q4, and an MOS tube Q3 is connected with an MOS tube Q4 in parallel; a diode D1 is connected between the emitter and the base of the PNP triode Q3, and the G pole of the MOS transistor Q3 is connected with the anode of the diode D1.
2. The synchronous rectification BUCK circuit freewheeling MOS pipe parallel connection adaptive adjustment circuit of claim 1, characterized in that: the circuit also comprises input filter capacitors C1 and C2 connected between the input end of the circuit and the output end of the circuit; and output filter capacitors C3, C4, C5, and C6.
3. The synchronous rectification BUCK circuit freewheeling MOS pipe parallel connection adaptive adjustment circuit of claim 2, characterized in that: the current sampling resistor R1 is connected between the output filter circuits C4 and C5.
4. The synchronous rectification BUCK circuit freewheeling MOS pipe parallel connection adaptive adjustment circuit of claim 1, characterized in that: and a current-limiting resistor R2 is also connected between the collector of the PNP triode Q5 and the OUT pin of the transport amplifier.
5. The synchronous rectification BUCK circuit freewheeling MOS pipe parallel connection adaptive adjustment circuit of claim 1, characterized in that: the control chip U1 is a PWM control chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021300292.8U CN212210852U (en) | 2020-07-06 | 2020-07-06 | Synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021300292.8U CN212210852U (en) | 2020-07-06 | 2020-07-06 | Synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit |
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| Publication Number | Publication Date |
|---|---|
| CN212210852U true CN212210852U (en) | 2020-12-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202021300292.8U Active CN212210852U (en) | 2020-07-06 | 2020-07-06 | Synchronous rectification BUCK circuit follow current MOS tube parallel connection self-adaptive adjusting circuit |
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| Country | Link |
|---|---|
| CN (1) | CN212210852U (en) |
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2020
- 2020-07-06 CN CN202021300292.8U patent/CN212210852U/en active Active
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