CN212112266U - High-stability LDO circuit without off-chip capacitor - Google Patents

Abstract

The utility model discloses a high-stability LDO circuit without off-chip capacitor, which relates to the technical field of integrated circuits based on 0.18 mu mBCD technology and comprises a band gap reference voltage circuit, a voltage comparison circuit, a compensation circuit, a power switch tube and an adjusting resistor; comprises an access power supply, a voltage comparator, a PMOS tube, an NMOS tube and a Miller capacitor. The load capacitor of the circuit is integrated in the chip, an off-chip capacitor is not needed, a pin can be reduced in external packaging, and meanwhile, the load capacitor can be integrated in an SoC system without an external discrete element.

Description

High-stability LDO circuit without off-chip capacitor

Technical Field

The invention belongs to the field of power supply circuits, and relates to the technical field of integrated circuits based on a 0.18 mu mBCD process.

Background

Nowadays, with the rapid development of the integrated circuit industry, the chip integration level is higher and higher, and the design of the power management chip for supplying power to the chip is more and more complex. Currently, many power management schemes are in the mainstream, and for the application in the voltage reduction situation, when the input voltage and the output voltage are relatively close, the LDO regulator becomes the first choice. The LDO regulator has a great and persistent demand because the LDO chip can provide stable and low-noise voltage for subsequent circuits, and occupies only a small amount of PCB area and consumes extremely low power consumption. Furthermore, the circuit architecture of the LDO is well suited for integration as an IP into a system on chip (SoC). With market changes and technological advances, the performance requirements for LDO regulators are also increasing. Higher conversion efficiency, lower power consumption, and fewer peripheral devices have become the research hotspot and development trend of LDO regulators.

Therefore, it is desirable to design a high-stability LDO circuit without an off-chip capacitor to solve the above problems.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that, under the condition that does not use electric capacity, use traditional operational amplifier, its stability is very poor, and phase margin can be below 40, is the burden even to produce great peak, its output voltage Vout can regularly vibrate in certain extent.

The utility model discloses a solve above-mentioned technical problem and adopt following technical scheme:

a high stability LDO circuit without off-chip capacitor, characterized in that: the band-gap reference voltage circuit comprises a band-gap reference voltage circuit, a voltage comparison circuit, a compensation circuit, a power switch tube and an adjusting resistor;

the band-gap reference voltage circuit generates a stable voltage Vref irrelevant to temperature to the positive terminal of the voltage comparison circuit, and the negative terminal of the voltage comparison circuit is connected with the adjusting resistance network to form negative feedback; the output end of the voltage comparator is connected with the grid of the power switch tube M1, and the on and off of the power switch tube are controlled by the band-gap reference voltage Vref and the feedback voltage Vfb, so as to control the on and off of the whole circuit.

As a further preferable solution of the high-stability LDO circuit without off-chip capacitor of the present invention, the bandgap reference voltage circuit includes a first NPN transistor D1, a second NPN transistor D2, a capacitor Cap1, a capacitor Cap2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, and an operational amplifier U1;

one end of a resistor R1 is connected to a source terminal potential Vin, the other end of the resistor R1 is connected to a source of a PMOS tube P1, a drain of the PMOS tube P1 is connected to a drain of an NMOS tube N5, sources of NMOS tubes N5 are respectively connected to one ends of a resistor R2 and a resistor R7, the other end of the resistor R7 is connected to an output terminal Vout, one end of a capacitor Cap1 and one end of a capacitor Cap1, the other ends of the capacitor Cap1 and the capacitor Cap1 are respectively grounded, the other end of the resistor R1 is connected to a drain of the NMOS tube N1, a source of the NMOS tube N1 is connected to a drain of the NMOS tube N1, a base of the second NPN 1 is connected to a collector of the NMOS tube D1, a first collector of the second NPN 1 is connected to a collector of the NPN emitter 1, a first collector of the NPN 1, and a negative emitter of the NPN 1 is connected to a first collector 1, The negative power supply end of the operational amplifier U1, the output end of the operational amplifier U1 is connected with the grid of an NMOS tube N5, a resistor R3 is connected between the source and the drain of the NMOS tube N1, a resistor R4 is connected between the source and the drain of an NMOS tube N2, a resistor R5 is connected between the source and the drain of the NMOS tube N3, a resistor R6 is connected between the source and the drain of the NMOS tube N4, and a resistor R3, a resistor R4, a resistor R5 and a resistor R6 are sequentially connected in series.

As a further preferable scheme of the LDO circuit without off-chip capacitor of the present invention, the voltage comparison circuit includes a PMOS transistor M1, a PMOS transistor M2, an NOMS transistor M3, an NMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NOMS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, an NOMS transistor M17, a PMOS transistor M18, a PMOS transistor M19, an NMOS transistor M20, and a capacitor C1;

wherein, the grid of the PMOS tube M1 is connected with Vref, the grid of the PMOS tube M2 is connected with Vb, the source of the PMOS tube M1 is connected with the source of the PMOS tube M2, the drain of the PMOS tube M2 is connected with the drain of the NOMS tube M2, the grid of the NOMS tube M2 is connected with the drain of the NOMS tube M2, the source of the NOMS tube M2 is connected with the source of the NMOS tube M2 and grounded, the grid of the NOMS tube M2 is connected with the grid of the NMOS tube M2, the grid of the NOMS tube M2 is connected with the source of the NMOS tube M2, the drain of the NMOS tube M2 is connected with the drain of the PMOS tube M2, the drain of the NMOS tube M2 is connected with the source of the NMOS tube M2, the drain of the PMOS tube M2 and the drain of the NMOS tube M2 are connected with the drain of the NMOS tube M2, the drain of the PMOS tube M2, the drain of the NMOS tube M2, the NMOS tube M2 and the drain of, One end of a capacitor C1, the other end of the capacitor C1 is connected to the source of the PMOS transistor M19, the drain of the PMOS transistor M18, and the voltage output terminal Vop, the source of the PMOS transistor M18 is connected to the drain of the PMOS transistor M11, the source of the PMOS transistor M5, and the voltage input terminal Vin, the drain of the PMOS transistor M5 is connected to the source of the PMOS transistor M5, and the source of the PMOS transistor M5, the drain of the PMOS transistor M5 is connected to the drain of the PMOS transistor M5, the source of the PMOS transistor M5 is connected to the source of the PMOS transistor M5, the gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M5, the drain of the NMOS transistor M5 is connected to the drain of the NMOS transistor M5, and the gate of the NMOS transistor M5 are connected to the drain of the NMOS transistor M5, the grid electrode of the NMOS tube M14 is respectively connected with the grid electrode of the NMOS tube M17 and the grid electrode of the NMOS tube M13 and is connected back to the source electrode of the NMOS tube M14, the drain electrode of the NMOS tube M14 is connected with the source electrode of the NMOS tube M17, and the drain electrode of the NMOS tube M17 is respectively connected with the source electrode of the NMOS tube M13 and the source electrode of the NMOS tube M16 and is grounded.

The utility model adopts the above technical scheme to compare with prior art, have following technological effect:

the utility model discloses a design of no LDO of off-chip capacitor based on 0.18 mu mBCD technology to theoretical analysis improves traditional circuit structure as the basis. The band-gap reference voltage with zero temperature coefficient is generated by linear superposition of Vbe (negative temperature coefficient) of two bipolar transistors and difference delta Vbe (positive temperature coefficient) of the Vbe, and meanwhile, the temperature drift coefficient of the output voltage is improved by adopting a negative feedback circuit and a filter circuit. In addition, a novel two-stage operational amplifier structure is designed based on the traditional structure for voltage comparison. The upper potential is isolated by adding a specific power switch tube into the operational amplifier, so that the power supply rejection ratio of the LDO is improved; meanwhile, in order to solve the problem of insufficient stability, a new pole is added by introducing the Miller capacitor. The off-chip capacitor can be effectively replaced by the Miller capacitor, discrete devices of the capacitor are not needed in the structure, and one pin can be reduced in packaging.

Drawings

FIG. 1 is a schematic diagram of an LDO design.

Fig. 2 is a bandgap reference voltage circuit.

Fig. 3 is a voltage comparison circuit.

Detailed Description

The technical scheme of the invention is further explained in detail by combining the attached drawings:

the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1, a high-stability LDO circuit without off-chip capacitor is characterized in that: the band-gap reference voltage circuit comprises a band-gap reference voltage circuit, a voltage comparison circuit, a compensation circuit, a power switch tube and an adjusting resistor;

the band-gap reference voltage circuit generates a stable voltage Vref irrelevant to temperature to the positive terminal of the voltage comparison circuit, and the negative terminal of the voltage comparison circuit is connected with the adjusting resistance network to form negative feedback; the output end of the voltage comparator is connected with the grid of the power switch tube M1, and the on and off of the power switch tube are controlled by the band-gap reference voltage Vref and the feedback voltage Vfb, so as to control the on and off of the whole circuit.

When the power switch tube is turned on, the adjusting resistor network divides the input voltage Vin to obtain the feedback voltage Vfb, and when the Vfb voltage value is too much larger than the Vref, the output of the voltage comparator is at a low level. At this time, the gate voltage of the power switch tube is at a low level, which is much smaller than the source terminal potential Vin of the power switch tube, and the power switch tube is turned on. When the input voltage Vin is a fixed value and the power switch tube is in a saturation region, the current flowing through the adjusting resistor network is basically unchanged, so that the aim of converting the high level of Vin into the low level of Vout to supply power to the internal module is fulfilled.

When the voltage value of Vin is variable, for the power switch tube, when the value of Vin satisfies the voltage condition that the power switch tube is in the saturation region within a certain range, the result is the same as the above result; if the voltage value of Vin forces the power switch tube to enter the linear region, as Vin increases, its current also increases, and Vout increases as the current increases. At this time, the value of Vfb is also increased, the gate voltage of the power switch tube is reduced through the negative feedback network, the power switch tube enters a saturation region, and the voltage values of Vout and Vfb are kept unchanged.

As shown in fig. 2, as a further preferable embodiment of the LDO circuit without off-chip capacitor of the present invention, the bandgap reference voltage circuit includes a first NPN transistor D1, a second NPN transistor D2, a capacitor Cap1, a capacitor Cap2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, and an operational amplifier U1;

one end of a resistor R1 is connected to a source terminal potential Vin, the other end of the resistor R1 is connected to a source of a PMOS transistor P1, a drain of a PMOS transistor P1 is connected to a drain of an NMOS transistor N5, sources of NMOS transistors N5 are respectively connected to one ends of a resistor R2 and a resistor R7, the other end of a resistor R7 is connected to an output terminal Vout, one end of a capacitor Cap1 and one end of a capacitor Cap1, the other ends of the capacitor Cap1 and the capacitor Cap1 are respectively grounded, the other end of the resistor R1 is connected to a drain of the NMOS transistor N1, a source of the NMOS transistor N1 is connected to a collector of a second NPN 1, a base of the second NPN 1 is connected to a collector of the NPN 1, a first collector of the NPN 1, and a negative emitter of the NPN 1 are respectively connected to a first collector 1, The negative power supply end of the operational amplifier U1, the output end of the operational amplifier U1 is connected with the grid of an NMOS tube N5, a resistor R3 is connected between the source and the drain of the NMOS tube N1, a resistor R4 is connected between the source and the drain of an NMOS tube N2, a resistor R5 is connected between the source and the drain of the NMOS tube N3, a resistor R6 is connected between the source and the drain of the NMOS tube N4, and a resistor R3, a resistor R4, a resistor R5 and a resistor R6 are sequentially connected in series.

The bandgap reference is mainly a bandgap reference voltage with zero temperature coefficient generated by linear superposition of Vbe (negative temperature coefficient) of two bipolar transistors and difference value delta Vbe (positive temperature coefficient) of the Vbe.

If the two bipolar transistors are operated at unequal current densities, the difference in their base-emitter voltages is proportional to absolute temperature.

The temperature coefficient is positive and is independent of temperature and collector current, and a band gap reference circuit is designed based on the principle.

When the switching signal Switch1 is low, the circuit is enabled. The adjusting MOS tube is controlled by an adjusting signal Adjust1-4 to control the total resistance of the whole branch, and voltage drop is generated when the upper potential Vin flows through a band-gap reference voltage network formed by two NON type triodes D1 and D2 and the adjusting resistance. Compared voltage operational amplifier is additionally added on the basis of the traditional band gap reference structure, so that the whole module forms a negative feedback structure, the performance is more optimized, and the stability is greatly improved. An RC filter network is added at an output port to achieve the purpose of outputting stable voltage.

As shown in fig. 3, as a further preferable embodiment of the LDO circuit without off-chip capacitor of the present invention, the voltage comparison circuit includes a PMOS transistor M1, a PMOS transistor M2, an NOMS transistor M3, an NMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NOMS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, an NOMS transistor M17, a PMOS transistor M18, a PMOS transistor M19, an NMOS transistor M20, and a capacitor C1;

wherein, the grid of the PMOS tube M1 is connected with Vref, the grid of the PMOS tube M2 is connected with Vb, the source of the PMOS tube M1 is connected with the source of the PMOS tube M2, the drain of the PMOS tube M2 is connected with the drain of the NOMS tube M2, the grid of the NOMS tube M2 is connected with the drain of the NOMS tube M2, the source of the NOMS tube M2 is connected with the source of the NMOS tube M2 and grounded, the grid of the NOMS tube M2 is connected with the grid of the NMOS tube M2, the grid of the NOMS tube M2 is connected with the source of the NMOS tube M2, the drain of the NMOS tube M2 is connected with the drain of the PMOS tube M2, the drain of the NMOS tube M2 is connected with the source of the NMOS tube M2, the drain of the PMOS tube M2 and the drain of the NMOS tube M2 are connected with the drain of the NMOS tube M2, the drain of the PMOS tube M2, the drain of the NMOS tube M2, the NMOS tube M2 and the drain of, One end of a capacitor C1, the other end of the capacitor C1 is connected to the source of the PMOS transistor M19, the drain of the PMOS transistor M18, and the voltage output terminal Vop, the source of the PMOS transistor M18 is connected to the drain of the PMOS transistor M11, the source of the PMOS transistor M5, and the voltage input terminal Vin, the drain of the PMOS transistor M5 is connected to the source of the PMOS transistor M5, and the source of the PMOS transistor M5, the drain of the PMOS transistor M5 is connected to the drain of the PMOS transistor M5, the source of the PMOS transistor M5 is connected to the source of the PMOS transistor M5, the gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M5, the drain of the NMOS transistor M5 is connected to the drain of the NMOS transistor M5, and the gate of the NMOS transistor M5 are connected to the drain of the NMOS transistor M5, the grid electrode of the NMOS tube M14 is respectively connected with the grid electrode of the NMOS tube M17 and the grid electrode of the NMOS tube M13 and is connected back to the source electrode of the NMOS tube M14, the drain electrode of the NMOS tube M14 is connected with the source electrode of the NMOS tube M17, and the drain electrode of the NMOS tube M17 is respectively connected with the source electrode of the NMOS tube M13 and the source electrode of the NMOS tube M16 and is grounded.

The voltage comparator is the core part of the LDO design, and is also the most important innovation point of the utility model. In the case of using a conventional operational amplifier without using a capacitor, the stability is very poor, the phase margin is below 40 °, even negative, so that a large peak is generated, and the output voltage Vout regularly oscillates within a certain range. Therefore, a voltage comparator circuit as shown in fig. 3 is designed on the basis of the conventional operational amplifier.

The Iref part on the left side is externally connected with a PMOS tube which has the same size as M16 and is short-circuited with the grid electrode and the drain electrode of the PMOS tube, so that a current mirror is formed, and the influence brought by the secondary effect of the current mirror can be effectively reduced. A current source is connected to the drain of the external MOS to provide bias current Iref, the Iref transfers the current to M12 through the M13-M14 current mirror, and then the current is provided to the differential operation circuit module through the M12-M5 current mirror.

In the middle differential operational amplifier circuit, the positive electrode is Vref, the negative electrode is Vfb, M3-M6 and M4-M7 transmit differential signals to the grid of M19, and qualitative analysis is carried out below that Vrf is a constant value,When Vfb is much larger than Vrf and is close to the upper potential Vin, M1 is turned on, M2 is turned off, the Iref current flows into the M1-M3 circuit completely, and the right circuit is turned off. The output voltage Vop is close to the voltage of the upper potential Vin, and as can be seen from the structure of fig. 1, the switching tube is turned off, and the LDO does not work; when Vfb is gradually reduced to a value, the M2 transistor is opened, is in a linear working region, the drain voltage of the transistor changes along with the change of Vfb, and the voltage is transmitted to the gate of the M19 to determine whether the M19 is switched on or not, and the voltage of Vop is determined by the states of the M18 and the M19; as Vfb continues to decrease, M1 and M2 are both in saturation, and at this time, the current is equally distributed to the two branches, the relationship between the current and the voltage is basically fixed, and the output voltage of the differential operational amplifier circuit is transmitted to the gate of M19.

The right side is the output part of the whole voltage comparator. The main functions are to provide a stable, desired gain and to obtain low noise performance, not only stable but also good performance. These requirements are dependent on the zero pole position of the amplifier. In order to reduce power consumption, the method of increasing the bias current is abandoned, and a Miller capacitor is added to add a new pole to improve stability. The non-dominant pole is shifted to a high enough frequency to make the amplifier similar to a single pole system. In order to provide sufficient phase margin, the non-dominant pole is about 3 times GBW, and the PM is between 60-70 deg..

Additionally, the utility model provides an LDO structure is used in the SoC system. In the whole SoC system, noise generated by the analog signal and the digital signal may affect each other, so that the loop stability is reduced. On the basis of the research of traditional LDO, the utility model discloses added power isolation pipe M11, M17 in voltage comparison operational amplifier circuit, in normal work, the power isolation pipe is turn-offed. This makes it possible to isolate the upper potential of the current bias circuit from the power supply of the input voltage even in a high-frequency circuit, and to prevent noises at both ends from interfering with each other. The power supply rejection ratio is obviously improved, the output ripple under high frequency is reduced, and the stability is improved.

Considering that the LDO is applied without a discrete device, research and design are performed on the LDO without an off-chip capacitor and an off-chip resistor, and the LDO can also output a stable voltage without an external capacitor to be applied in a DC-DC converter to supply power to an internal circuit module. And the zero pole of the LDO is adjusted by adjusting the structure of the operational amplifier in the LDO and performing Miller compensation on the operational amplifier, and meanwhile, the power supply rejection ratio of the LDO can be obviously improved by performing power supply isolation treatment in the operational amplifier. And finally, by utilizing an integrated circuit technology of a 0.18 mu mBCD process, the structure has high stability and can output stable voltage.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Above embodiment only is for explaining the utility model discloses a technical thought can not be injectd with this the utility model discloses a protection scope, all according to the utility model provides a technical thought, any change of doing on technical scheme basis all falls into the utility model discloses within the protection scope. Although the embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the scope of knowledge possessed by those skilled in the art.

Claims (3)

1. A high stability LDO circuit without off-chip capacitor, characterized in that: the band-gap reference voltage circuit comprises a band-gap reference voltage circuit, a voltage comparison circuit, a compensation circuit, a power switch tube and an adjusting resistor;

the band-gap reference voltage circuit generates a stable voltage Vref irrelevant to temperature to the positive terminal of the voltage comparison circuit, and the negative terminal of the voltage comparison circuit is connected with the adjusting resistance network to form negative feedback; the output end of the voltage comparator is connected with the grid of the power switch tube M1.

2. The high stability LDO circuit without off-chip capacitor of claim 1, wherein: the band gap reference voltage circuit comprises a first NPN tube D1, a second NPN tube D2, a capacitor Cap1, a capacitor Cap2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a PMOS tube P1, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5 and an operational amplifier U1;

one end of a resistor R1 is connected to a source terminal potential Vin, the other end of the resistor R1 is connected to a source of a PMOS transistor P1, a drain of a PMOS transistor P1 is connected to a drain of an NMOS transistor N5, sources of NMOS transistors N5 are respectively connected to one ends of a resistor R2 and a resistor R7, the other end of a resistor R7 is connected to an output terminal Vout, one end of a capacitor Cap1 and one end of a capacitor Cap1, the other ends of the capacitor Cap1 and the capacitor Cap1 are respectively grounded, the other end of the resistor R1 is connected to a drain of the NMOS transistor N1, a source of the NMOS transistor N1 is connected to a collector of a second NPN 1, a base of the second NPN 1 is connected to a collector of the NPN 1, a first collector of the NPN 1, and a negative emitter of the NPN 1 are respectively connected to a first collector 1, The negative power supply end of the operational amplifier U1, the output end of the operational amplifier U1 is connected with the grid of an NMOS tube N5, a resistor R3 is connected between the source and the drain of the NMOS tube N1, a resistor R4 is connected between the source and the drain of an NMOS tube N2, a resistor R5 is connected between the source and the drain of the NMOS tube N3, a resistor R6 is connected between the source and the drain of the NMOS tube N4, and a resistor R3, a resistor R4, a resistor R5 and a resistor R6 are sequentially connected in series.

3. The high stability LDO circuit without off-chip capacitor of claim 1, wherein: the voltage comparison circuit comprises a PMOS tube M1, a PMOS tube M2, an NOMS tube M3, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6, an NMOS tube M7, a PMOS tube M8, a PMOS tube M9, an NOMS tube M10, a PMOS tube M11, a PMOS tube M12, an NMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M16, an NOMS tube M17, a PMOS tube M18, a PMOS tube M19, an NMOS tube M20 and a capacitor C1;

wherein, the grid of the PMOS tube M1 is connected with Vref, the grid of the PMOS tube M2 is connected with Vb, the source of the PMOS tube M1 is connected with the source of the PMOS tube M2, the drain of the PMOS tube M2 is connected with the drain of the NOMS tube M2, the grid of the NOMS tube M2 is connected with the drain of the NOMS tube M2, the source of the NOMS tube M2 is connected with the source of the NMOS tube M2 and grounded, the grid of the NOMS tube M2 is connected with the grid of the NMOS tube M2, the grid of the NOMS tube M2 is connected with the source of the NMOS tube M2, the drain of the NMOS tube M2 is connected with the drain of the PMOS tube M2, the drain of the NMOS tube M2 is connected with the source of the NMOS tube M2, the drain of the PMOS tube M2 and the drain of the NMOS tube M2 are connected with the drain of the NMOS tube M2, the drain of the PMOS tube M2, the drain of the NMOS tube M2, the NMOS tube M2 and the drain of, One end of a capacitor C1, the other end of the capacitor C1 is connected to the source of the PMOS transistor M19, the drain of the PMOS transistor M18, and the voltage output terminal Vop, the source of the PMOS transistor M18 is connected to the drain of the PMOS transistor M11, the source of the PMOS transistor M5, and the voltage input terminal Vin, the drain of the PMOS transistor M5 is connected to the source of the PMOS transistor M5, and the source of the PMOS transistor M5, the drain of the PMOS transistor M5 is connected to the drain of the PMOS transistor M5, the source of the PMOS transistor M5 is connected to the source of the PMOS transistor M5, the gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M5, the drain of the NMOS transistor M5 is connected to the drain of the NMOS transistor M5, and the gate of the NMOS transistor M5 are connected to the drain of the NMOS transistor M5, the grid electrode of the NMOS tube M14 is respectively connected with the grid electrode of the NMOS tube M17 and the grid electrode of the NMOS tube M13 and is connected back to the source electrode of the NMOS tube M14, the drain electrode of the NMOS tube M14 is connected with the source electrode of the NMOS tube M17, and the drain electrode of the NMOS tube M17 is respectively connected with the source electrode of the NMOS tube M13 and the source electrode of the NMOS tube M16 and is grounded.

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