CN211555882U

CN211555882U - Multi-chip stacking structure

Info

Publication number: CN211555882U
Application number: CN201922327924.3U
Authority: CN
Inventors: 孙鹏; 孙立明
Original assignee: National Center for Advanced Packaging Co Ltd
Current assignee: National Center for Advanced Packaging Co Ltd
Priority date: 2019-12-20
Filing date: 2019-12-20
Publication date: 2020-09-22
Anticipated expiration: 2029-12-20

Abstract

The utility model belongs to the technical field of the encapsulation, concretely relates to multi-chip stacked structure. The structure includes a substrate; the plurality of chips are stacked along the direction vertical to the substrate, and a supporting structure is arranged between every two adjacent chips; the chip and the substrate are electrically interconnected; the multi-chip stacking structure can realize repeated stacking of a plurality of upright chips through the supporting structure, and realizes electrical interconnection with the substrate respectively, thereby effectively reducing the volume of the multi-chip stacking structure and further reducing the size of a packaged product; the multi-chip stacking structure can be used in the traditional packaging of the normally-installed chip, and has lower precision requirement and cost on the packaging process.

Description

Multi-chip stacking structure

Technical Field

The utility model belongs to the technical field of the encapsulation, concretely relates to multi-chip stacked structure.

Background

With the rapid development of semiconductor integrated circuits, the functional requirements of the integrated circuits are more and more, the requirement of improving the integration level of multi-chip interconnection is more and more prominent, and meanwhile, in order to meet the requirements of miniaturization and light weight, the stacking structure is rapidly developed according to the requirement. The three-dimensional stacking structure can improve the packaging density, reduce the interconnection length and the packaging volume between chips, improve the operation performance of an integrated circuit and realize the diversification of chip combinations.

Chinese patent document CN107579009A discloses a multi-chip stacked package structure, including at least two dual-chip stacked packages stacked in sequence from top to bottom, the dual-chip stacked package includes a lead bonding chip, a flip chip, a passivation layer, a rewiring layer, a bonding wire and a vertical array lead, the flip chip is bonded on the lead bonding chip and the two are integrated by injection molding to form a plastic package body, the upper surface and the lower surface of the plastic package body are further provided with passivation layers, the rewiring layer is disposed between the plastic package body and the passivation layers and realizes electrical interconnection of the lead bonding chip and the flip chip through the bonding wire and the vertical array lead. The preparation method comprises the steps of manufacturing or attaching a layer of temporary bonding film on the upper surface of a first carrier wafer; manufacturing a passivation layer and a rewiring layer; the back surface of the lead bonding chip is attached to the passivation layer, and then the back surface of the flip chip is attached to the front surface of the lead bonding chip by using insulating glue; bonding, plastic packaging and re-wiring to form a double-chip laminated packaging body; however, the packaging structure needs to be subjected to temporary bonding, surface mounting and plastic packaging, is suitable for the process requirements of wafer-level chip packaging, is not suitable for packaging of traditional chips, and has high requirements on process precision, complex process and high cost.

Disclosure of Invention

Therefore, the to-be-solved technical problem of the utility model lies in overcoming the chip package among the prior art size big, to the requirement height of encapsulation technology precision, defect such as technology complicacy to a multichip stack structure is provided.

Therefore, the utility model provides the following technical scheme.

The utility model provides a multi-chip stacking structure, which comprises,

a substrate;

the plurality of chips are stacked along the direction vertical to the substrate, and a supporting structure is arranged between every two adjacent chips;

the chip and the substrate are electrically interconnected.

The chip is a front-mounted chip.

And in the plurality of chips which are arranged in a stacked manner, the chip at the bottommost layer is attached to the substrate.

And a supporting structure is also arranged between the substrate and the chip.

The support structure is a silicon column.

The substrate is attached to the support structure.

A bonding pad is arranged on the back surface of the substrate; the bonding pad is square or round.

The multi-chip stacking structure further comprises a plastic packaging layer which coats the chip, the substrate and the supporting structure.

The utility model discloses technical scheme has following advantage:

1. the utility model provides a multi-chip stacking structure, which comprises a substrate; the plurality of chips are stacked along the direction vertical to the substrate, and a supporting structure is arranged between every two adjacent chips; the chip and the substrate are electrically interconnected; the multi-chip stacking structure can realize repeated stacking of a plurality of upright chips through the supporting structure, and realizes electrical interconnection with the substrate respectively, thereby effectively reducing the volume of the multi-chip stacking structure and further reducing the size of a packaged product; the multi-chip stacking structure can be used in the traditional packaging of the normally-installed chip, and has lower precision requirement and cost on the packaging process.

The multi-chip stacking structure can also improve the feasible space of subsequent SMT pasting pieces.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a front view of a multi-chip stack in an embodiment of the invention;

FIGS. 2-7 are flow diagrams of a multi-chip stack structure packaging method according to an embodiment of the present invention;

reference numerals:

1-a second chip; 2-a first chip; 3-a substrate; 4-a second silicon column; 5-a pad; 6-a first silicon column; 7-plastic packaging layer; 8-a third silicon column; 9-a fourth silicon column; 10-a fifth silicon column; 11-PCB circuit board.

Detailed Description

The following examples are provided for better understanding of the present invention, and are not limited to the best mode, and do not limit the scope and content of the present invention, and any product that is the same or similar to the present invention, which is obtained by combining the features of the present invention with other prior art or the present invention, falls within the scope of the present invention.

The examples do not show the specific experimental steps or conditions, and can be performed according to the conventional experimental steps described in the literature in the field. The reagents or instruments used are not indicated by manufacturers, and are all conventional reagent products which can be obtained commercially.

Examples

The present embodiment provides a multi-chip stack structure, which is shown in fig. 1 in a front view, includes,

a substrate 3, wherein a bonding pad 5 is arranged on the back surface of the substrate, the bonding pad is square or circular, and the bonding pad is circular in the embodiment; in addition, the front surface of the substrate may be provided with a PCB 11 or the like.

The two chips are respectively a first chip 2 and a second chip 1, the first chip and the second chip are stacked along the direction vertical to the substrate, a supporting structure is arranged between the first chip and the second chip and respectively attached to the supporting structure, each chip is electrically interconnected with the substrate 3 through bonding, the first chip positioned at the bottom layer is attached to the substrate, the first chip and the second chip are both upright chips, the first chip is arranged on the substrate in an upright manner, the second chip is arranged above the supporting structure in an upright manner, the size and thickness of the first chip and the second chip can be designed and adjusted according to the use requirement, and the size of the first chip is smaller than that of the second chip; a supporting structure is arranged between the second chip and the substrate, and can realize repeated stacking of a plurality of upright chips, so that the volume of the multi-chip stacking structure is reduced; the supporting structure is a silicon column, and the number and the position of the silicon column can be adjusted according to the requirements of the chip; including 5 silicon columns in this embodiment, be first silicon column 6, second silicon column 4, third silicon column 8, fourth silicon column 9 and fifth silicon column 10 respectively, first silicon column sets up between first chip and second chip, second silicon column, third silicon column, fourth silicon column and fifth silicon column set up between second chip and base plate, laminate mutually with the base plate, 5 silicon columns are on same level, the height and the position of silicon column are adjusted according to the requirement of first chip and second chip.

And the plastic package layer 7 wraps the first chip 2, the second chip 1 and the supporting structure and is arranged on the front surface of the substrate.

The method for packaging the multi-chip stack structure in the embodiment, the flow charts of which are shown in fig. 2-7, includes the following steps,

the front surface of the substrate is pasted with a first chip 2, and the pasted structure is shown in figure 2;

then, silicon columns are attached to the substrate and the first chip to form a supporting structure, the first silicon column 6 is attached to the first chip, the second silicon column 4, the third silicon column 8, the fourth silicon column 9 and the fifth silicon column 10 are attached to the substrate, the five silicon columns are at the same horizontal height, and the structure after the silicon columns are attached is shown in figure 3;

electrically interconnecting the first chip and the substrate by bonding, wherein the bonded structure is shown in fig. 4;

attaching a second chip 1 on the support structure, and then realizing electrical interconnection between the second chip and the substrate through bonding, wherein the structure of the bonded second chip and the substrate is shown in fig. 5;

carrying out plastic packaging on the structure, and forming a plastic packaging layer on the front surface of the substrate, as shown in fig. 6;

the substrate is then provided with pads 5 on its back side for packaging, see fig. 7.

The packaging method can reduce the packaging volume by arranging the supporting structure between the adjacent chips, is simple, has low precision requirement and low cost, and is more suitable for actual production.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A multi-chip stacking structure, comprising,

a substrate;

the chip and the substrate are electrically interconnected;

in the plurality of chips arranged in a stacked manner, the chip at the bottommost layer is attached to the substrate;

and a supporting structure is also arranged between the substrate and the chip.

2. The multi-chip stack structure of claim 1, wherein the chip is a face-up chip.

3. The multi-chip stack structure of claim 1, wherein the support structures are silicon pillars.

4. The multi-chip stack structure of claim 1, wherein the substrate is attached to the support structure.

5. The multi-chip stack structure of claim 1, wherein a back side of the substrate is provided with pads; the bonding pad is square or round.

6. The multi-chip stack structure of claim 1, further comprising a molding layer encapsulating the chips, the substrate, and the support structure.